Symposia on VLSI Technology and Circuits
Synthetic Electric Field Tunnel FETs: Drain Current Multiplication Demonstrated by
Wrapped Gate Electrode Around Ultrathin Epitaxial Channel�
Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O’uchi, Yongxun Liu, Meishoku Masahara, and Hiroyuki Ota
Green Nanoelectronics Center(GNC) Nanoelectronics Research Institute (NeRI)
AIST
Outline
• Background – Why tunnel FET? – Proposal of Synthetic electric fielfd tunnel FET
• Experimental setup – Operation mechanism – Device fabrication
• Results and Discussion – Measurement of Si SE-TFET
• Summary
Slide 2
Why tunnel FET ?
• TFET: Different operation mechanism from MOSFET – Sub-60 mV/dec SS operation
Slide 4
Potential modulation by gate field�
Metal-oxide-semiconductor FET (MOSFET)�
p Source�
n Channel�
Hole�
p Drain�
Tunnel FET (TFET)�
p Source� i Channel�
BTBT transport�
Electron�
n Drain�
Potential modulation by gate field�
Why tunnel FET ?
• Reduction of operation voltage – Steeper SS than MOSFET is indispensable.
Slide 5
Gate voltage (V)�
Log(
Id)
(A/u
m)�
Sub-threshold swing (SS)
MOSFET�
Sub 60mV/decade Tunnel FET�
Operation voltage�
Transfer characteristic of FET
Issues in the tunnel FET
• Small drain current – Intrinsic problem on tunnel transport
Boosting tunnel probability • Steep dopant profile • High mobility channel • Energy-band alignment
Enhancing electrostatic controllability • EOT scaling • Vertical tunneling architecture
Slide 6
Lateral & vertical TFETs
• Two types of TFET architectures ever studied
Slide 7
Conventional (Lateral) TFET� Vertical TFET �
BTBT is perpendicular to the gate field. � BTBT is parallel to the gate field.�
Similar architecture to the conventional MOSFET�
Modified architecture to enhance electrostatic controllability �
BOX�
high-k�
Gate �
n+ S� p+ D�
BOX�
high-k�
Gate �
EGATE�
IT� p+ D�n+ S�EGATE�
IT�
Vertical tunneling TFETs
Slide 8
R. Li et.al., Phys. Status Solidi C 9, 389 (2012).
Epitaxial channel
BOX�
high-k�
G �
S� D�
Y. Morita et.al, SSDM2012, Jpn. J. Appl. Phys. 52, 04CC25 (2013).�
Buried Oxide�
G �N+ Source� P+ Drain�
P-�
P+ Pocket�
Green FET �
C. Hu et.al., VLSI-TSA 2008, 14 (2008).�
Si epitaxial channel TFET �
InAs/AlGaSb heterojunction TFET �
Proposal of synthetic electric field TFET
• To enhance electrostatic controllability using lateral & vertical electric fields
Slide 9
Conventional (Lateral) TFET�
Parallel electric file TFET�
(c)�
n+ S� p+ D�BOX�
IT�
Gate�
(d)�
Gate�
BOX�
n+ S�ETop�
ESide�IT�ESynth�
WCH�
WCH� DEPI�DEPI�
High-k�
LOV�
Synthetic electric filed TFET�(a) �
(b) �
BOX�
Gate �
n+ S� p+ D�
EGATE�
IT�
BOX�
Gate �
p+ D�n+ S�EGATE�
IT�
Operation mechanism
Slide 12
Conventional (lateral) TFET�SE-TFET�
Top E-field� Side + Top E-fields�
BTBT window�
IT�IT�
BO
X�
n+ D�
p+ S�
EC�
IT�
BOX�
Gate �
n+ S� p+ D�EGATE�
IT�
Simulation of electric field
• Electric field at edges is enlarged by SE-effect. • Scaling of channel thickness and width enahnces
SE-effect
Slide 13
3x106�
1x104�
3x104�
9x104�
3x105�
9x105�
Electric field (V/cm)�
EC�
n+ S�
Electric field enhancement�
Electric field distribution�
WCH = 20 nm DEPI = 10 nm�
Process flow
Slide 17
As ion implantation�Mask�Mask� Mask�
BF2 ion implantation�(b)� (c)� (d)�
p-TFET� n-TFET�
SOI�BOX�
(a)�
SOI�BOX� BOX�
Channel epitaxial growth�
BOX�
Mesa-etching�(e)�
BOX�
Gate insulator & Gate electrode�
(f)�
BOX�
Gate etch�(g)�
BOX�D�S�DS�
• Based on source/drain-first CMOS process
Device structures
Slide 18
50 nm�n+ Source�
Epitaxial channel�Gate electrode (TiN)�
Gate insulator (HfO2)�
50 nm�
Channel cross-section �
Gate cross-section �
• Small amount of diffects at epitaxial channel/source interface
Gate (TiN)� HfO2 �
Source �
Epitaxial channel�
Slide 19
1016
1017
1018
1019
1020
1021
10 20 30 40 50
Conc
entra
tion
(cm
-3)
Depth (nm)
as-epi.
900 oC
1000 oC
As
Epitaxialchannel
n+ S
1
10
100
600 800 1000
Dopa
nt g
radi
ent (
nm/d
ec)
Post-anneal temp.(oC)
B
As
• Dopant steepness is maintained below 900 ˚C.
SIMS analysis of dopant profiles
Slide 21
Impact of SE effect
10-8
10-6
10-4
10-2
100
-2.0 -1.0 0.0
I D (uA/
um)
VG (V)
With SE effect
Without SE effect
WCH
= 10 um DEPI
= 10 nmGate�
BOX�n+ S�
EC �
Gate�
BOX�n+ S�
EC �
• Singificant current increase in the SE-TFET
SE-TFET�
Parallel electric field TFET�
ID-VG �
Slide 22
10-8
10-6
10-4
10-2
100
102
-2.0 -1.0 0.0VG (V)
I D (uA/
um)
VD = -0.05 V
SSM
IN =
52
WCH0.17 um1 um10 um
DEPI = 10 nm
LOV = 400 nm
Impact of channel width
40
60
80
100
102 103 104
SSMI
N (mV/
deca
de)
WCH (nm)
DEPI = 10 nm VD = -0.05 VLOV = 400 nm
• Better performance in narrower channel device ID-VG �
Slide 25
0.0
0.5
1.0
1.5
2.0
2.5
0 5 10 15 20
I D (uA)
WCH (um)
DEPI = 10 nm
DEPI = 16 nm
LOV = 400 nm VD = -1 VVG = -2 V
Impact of channel width
5.4 x 10-3 uA/um �
0.1 uA/um �
0.7 uA �
0.2 uA �
• Edge current is enhanced by DEPI scaling.
Slide 26
Impact of channel width
0.0
0.5
1.0
1.5
2.0
2.5
0 5 10 15 20
I D (uA)
WCH (um)
DEPI = 10 nm
DEPI = 16 nm
LOV = 400 nm VD = -1 VVG = -2 V Gate�
BOX�n+ S�
EC �Gate�
BOX�n+ S�
EC �
ID at Edge
= �3.5 um�
DEPI = 10 nm�
Gate�
BOX�n+ S�
EC �Gate�
BOX�n+ S�
EC �
ID at Edge
= �18.5 um�
DEPI = 16 nm�
• Significant current at edge region�
Slide 27
10-4
10-2
100
102
100 101 102 103 104 105
I D (uA/
um)
WCH (nm)
4 nm(Prediction)
10 nmDEPI = 16 nm
Impact of channel width
• Scaling of both DEPI and WCH enhance performance
EC�
Gate�
n+ S�
EC�
Gate�
n+ S�
FinFET-like structure is better�
DEPI = 16 nm �
Conclusion
• Synthetic electric field effect to enhance TFET performance is proposed. – Enlarged electric field at channel edge region – Scaling-induced performance enhancement in channel
thicknnes and width
• FinFET-like slim device is promissing for the SE-TFET
• Ge or III-V SE-TFETs will be possible.
Slide 30
Acknowledgement
This research was granted by JSPS.
Slide 31
Thank you for your kind attention.�