Testing forDesigned Board
FPGA138.24M-
SPSDATA
DAC3484 241.92MHz
1.1 Customer Concept
ADC241.92MHz
- sampling frequency : 138.24MHz / Interpolation : 4x- Enable Digital Mixer fs/2- Disable NCO
1.2 Test Result
[DAC3484 Register]
4x_intp.txt
1.3 Question
-- Why signal is break ?-- Center Freq is not 241.92MHz. Why?
Testing forTSW1400 + DAC3484 EVM
TSW1400 DAC34H84EVM
Signal Generator
PC
Spectrum
1. Test Configuration
3. Test Result - Signal source file: single tone - F sampling frequency : 307.2MHz / Interpolation : 4x
[TSW1400] [DAC3484]
[Spectrum]
Test Result : Normal
[DAC34H84 Register]
EVM_Test_307p2DACCLK_4x_intp.txt
3. Test Result
[TSW1400] [DAC3484]
[Spectrum]
Test Result : Normal
[DAC34H84 Register]
EVM_Test_307p2DACCLK_4x_intp.txt
- Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000- F sampling frequency : 307.2MHz / Interpolation : 4x
3. Test Result
[TSW1400] [DAC3484]
[Spectrum]
Test Result : Normal
[DAC34H84 Register]
- Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000- F sampling frequency : 307.2MHz / Interpolation : 2x
EVM_Test_307p2DACCLK_2x_intp.txt
3. Test Result - Signal source file: single tone - F sampling frequency : 138.24MHz / Interpolation : 4x
[TSW1400] [DAC3484] PLL unlock
[Spectrum]
Test Result : Abnormal1. Signal unstable2. Center Freq mismatch
[DAC34H84 Register]
EVM_Test_138p24DACCLK_4x_intp.txt
3. Test Result - Signal source file: single tone - F sampling frequency : 138.24MHz / Interpolation : 2x
[TSW1400] [DAC3484] PLL unlock
[Spectrum]
[DAC34H84 Register]
EVM_Test_138p24DACCLK_2x_intp.txt
Test Result : Abnormal1. Signal unstable2. Center Freq mismatch