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AAYAM13
Presents
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Introduction to Verilog
Hardware Description
Language
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Hardware Description Language
(HDL) Basic idea is a programming language to
describe hardware
Initial purpose was to allow abstract design
and simulation Design could be verified then implemented in
hardware
Now Synthesis tools allow directimplementation from HDL code.
Large improvement in designer productivity
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Purpose of HDL:
1. Describe the circuit in algorithmic level (likec) and in gate-level (e.g. And gate)
2. Simulation
3. Synthesis
4. Words are better than pictures
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Aug 9, 2001 FPGA System Design with Verilog 5
What HDL is NOT HDL is not a programming language
(HDL is a description language)
HDL is not highly abstract, e.g., implementthe DSP algorithm y(n) = 0.75y(n-1) + 0.3x(n)(HDL is at the RTL level (register transfer))
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Aug 9, 2001 FPGA System Design with Verilog 6
Synthesizable Subset
Verilog (and VHDL) began life as simulationand modelingtools
Hardware synthesis developed during the
1990s
Need to use a subset of Verilog and specificcoding styles to allow synthesis tool to infer
correct (and realizable) hardware
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Aug 9, 2001 FPGA System Design with Verilog 7
Synthesizable Subset
Synthesizable
Verilog
Verilog
Use this to writetestbenches for
behavioral simulation
Use this to
make hardware
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Aug 9, 2001 FPGA System Design with Verilog 8
Most Likely Learning Hurdle
May try to write HDL code as if it willeventually be executed by some mysterious
processor device in the FPGA
Code is written sequentially (like a program),but you are simply writing descriptions of thevarious hardware entities in your system
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Design Methodologies:
1. Top Down Approach
2. Bottom Up Approach
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Synthesis
Place andRoute
clb 1clb 2
Alwaysinst1inst2
inst3
Modern Project Methodology
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Verilog Basics
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helloWorld.v
module helloWorld ;
initial
begin
$display ("Hello World!!!");
$finish;
end
endmodule
This is aproceduralblock.
There are two types of procedural
blocks: initialand always.
More than one statement must be
put in a begin-endgroup.
Modules are the unit building-blocks
(components) Verilog uses to describe
an entire hardware system. Modules are
(for us) of three types: behavioral, dataflow,
gate-level. We ignore theswitch-levelin
this course.
This module is behavioral. Behavioral
modules contain code in proceduralblocks.System calls.
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Modeling Structures: Modules
Module
CircuitInput
X
Y
Z
Output
O
Wire
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Points to remember about modules in
Verilog:
All code is contained in modules
A module can invoke other modules
Modules cannot be contained in anothermodule
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Module declaration
ModuleCircuitInput
X
Y
Z
Output
O
Wire
module sample (X,Y,Z,O);input X,Y,Z;output O;// Describe the circuit using logic symbolsassign O = (X^Y)&Z;endmodule
Module name
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Typical Module Components Diagram
Module name, Port list (optional, if there are ports)
Port declarations
Parameter list
Declaration of variables (wires, reg, integer etc.)
Instantiation of inner (lower-level) modules
Structural statements (i.e., assign and gates)
Procedural blocks (i.e., always and initial blocks)
Tasks and functions
endmodule declaration
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Modeling Structure: Ports
Module Ports Similar to pins on a chip
Provide a way to communicate with outside world
Ports can be input, output or inout
i0
i1
o
Module AND (i0, i1, o);input i0, i1;output o;
endmodule
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Modeling Structure: Instances Module instances
Verilog models consist of a hierarchy of module instances In C++ speak: modules are classes and instances are
objects
AND3
i0
i1
i2o
Module AND3 (i0, i1, i2, o);
input i0, i1, i2;output 0;
wire temp;
AND a0 (temp,i0,i1));AND a1 (o,i2,temp);
endmodule
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Port Connection
Connect module port by order list FA1 fa1(c_o, sum, a, b, c_i);
Connect module port by name(Recommended)
Usage: .PortName (NetName)
FA1 fa2(.A(a), .B(b), .CO(c_o), .CI(c_i), .S(sum));
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System Tasks
$monitor $monitor ($time,"%d %d %d",address,sinout,cosout); Displays the values of the argument list whenever any
of the arguments change except $time.
$display $display ("%d %d %d",address,sinout,cosout); Prints out the current values of the signals in the
argument list
$finish $finish Terminate the simulation
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System Tasks
$display examples: $display(Hello Verilog World!);
Output:Hello Verilog World!
$display($time);Output:230
reg [0:40] virtual_addr;
$display(At time %d virtual address is %h,
$time, virtual_addr);Output:At time 200 virtual address is 1fe000001c
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System Tasks
$monitor Examples:
initial
begin
$monitor($time, Value of signals clock=%b,
reset=%b, clock, reset);end
Output:0 value of signals clock=0, reset=1
5 value of signals clock=1, reset=110 value of signals clock=0, reset=0
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Lexicography
Comments:Two Types: // Comment
/*These comments extend
over multiple lines. Good
for commenting out code*/
Character Set:0123456789ABCD..YZabcd...yz_$
Cannot start with a number or $
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Number Representation
Format:
- decimal specification of bits count Default: unsized and machine-dependent but at least 32
bits
- ' followed by arithmetic base ofnumber d orD decimal (default if no base format given)
h orH hexadecimal
o orO octal b orB binary
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Number Representation
Format:
- value given in base of baseformat
_can be used for reading clarity
x and z are automatically extended
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Number Representation
Examples: 6b010_111 gives 010111
8b0110 gives 00000110
4bx01 gives xx01 16H3AB gives 0000001110101011
24 gives 00011000
5O36 gives 11110
16Hx gives xxxxxxxxxxxxxxxx
8hz gives zzzzzzzz
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Data Types
Nets and Registers
Vectors
Integer, Real, and Time Register Data Types
Arrays
Memories
Parameters
Strings
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Value Set in Verilog
0
1
X
Z0
4-value logic system in Verilog :
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Nets
Used to represent connections between HW elements Values continuously driven on nets
Keyword: wire Default: One-bit values
unless declared as vectors Default value: z
Fortrireg, default is x
Examples wire a;
wire b, c; wire d=1b0;
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Registers
Registers represent data storage elements Retain value until next assignment
NOTE: this is not a hardware register or flipflop
Keyword: reg
Default value: x
Example:reg reset;
initial
beginreset = 1b1;
#100 reset=1b0;
end
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Vectors
Net and register data types can be declared asvectors (multiple bit widths)
Syntax:
wire/reg [msb_index : lsb_index] data_id;
Examplewire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;
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Vectors (contd)
Considerwire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr;
Access to bits or parts of a vector is possible:busA[7]
bus[2:0] // three least-significant bits of bus
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits* of virtual_addr
*/
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Integer, Real, and Time
Register Data Types
Integer Keyword: integer
Very similar to a vector ofreg integer variables are signed numbers
reg vectors are unsigned numbers
Bit width: implementation-dependent (at least 32-bits) Designer can also specify a width:
integer [7:0] tmp;
Examples:integer counter;initial
counter = -1;
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Integer, Real, and Time
Register Data Types (contd)
Real Keyword: real Values:
Default value: 0 Decimal notation: 12.24 Scientific notation: 3e6 (=3x106)
Cannot have range declaration Example:
real delta;
initial
begin
delta=4e10;
delta=2.13;end
integer i;
initial
i = delta; // i gets the value 2 (rounded value of 2.13)
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Integer, Real, and Time
Register Data Types (contd)
Time Used to store values of simulation time
Keyword: time
Bit width: implementation-dependent (at least 64) $time system function gives current simulation time
Example:time save_sim_time;
initialsave_sim_time = $time;
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Arrays
Syntax: [start_idx : end_idx];
Allowed in reg, integer, time, real and vector register data types.
Examples:
integer count[0:7];reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][4:0]; // two dimensional array
count[5]chk_point[100]
port_id[3]
Note the difference between vectors and arrays
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Data Types ~ summary
Data Values:0,1,x,z
Wire- Synthesizes into wires
- Used in structural code
Reg- May synthesize into latches, flip-flops or wires
- Used in procedural code
Integer32-bit integer used as indexes
Input, Output, inoutDefines ports of a module (wire by default)
module sample (a,b,c,d);
input a,b;
output c,d;
wire [7:0] b;
reg c,d;
integer k;
i bl l i
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Variable Declaration Declaring a net
wire [] [*];Range is specified as [MSb:LSb]. Default is one bit wide
Declaring a registerreg [] [*];
Declaring memoryreg [] [ : ];
Examplesreg r; // 1-bit reg variablewire w1, w2; // 2 1-bit wire variablereg [7:0] vreg; // 8-bit registerreg [7:0] memory [0:1023]; a 1 KB memory
P d D T
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Ports and Data Types
Correct data types for ports
inout
input output
net net
net
net
Register/net register/net
Module
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Operators
Arithmetic:*,+,-, /,% Relational=,==, !=
Bit-wise Operators Not: ~ XOR: ^ And : & 5b11001 & 5b01101 ==> 5b01001 OR: | XNOR: ~^ or ^~
Logical OperatorsReturns 1or 0, treats all nonzero as 1
! : Not && : AND 27 && -3 ==> 1 || : OR
reg [3:0] a, b, c, d;wire[7:0] x,y,z;parameter n =4;
c = a + b;d = a *n;
If(x==y) d = 1; else d =0;
d = a ~^ b;
if ((x>=y) && (z)) a=1;else a = !x;
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Operators
Reduction Operators:Unary operations returns single-bit values & : and | :or ~& : nand ~| : nor ^ : xor ~^ :xnor
Shift OperatorsShift Left: >
Concatenation Operator
{ } (concatenation){ n{item} } (n fold replication of an item)
Conditional OperatorImplements if-then-else statement(cond) ? (result if cond true) : (result if cond false)
module sample (a, b, c, d);input [2:0] a, b;output [2;0] c, d;wire z,y;
assign z = ~| a;
c = a * b;If(a==b) d = 1; else d =0;
d = a ~^ b;
if ((a>=b) && (z)) y=1;else y = !x;
assign d
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Net Concatenation
3o7
Module A
Module B
Module C
Representations Meanings{b[3:0],c[2:0]} {b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}
{a,b[3:0],w,3b101} {a,b[3] ,b[2] ,b[1] ,b[0],w,1b1,1b0,1b1}
{4{w}} {w,w,w,w}
{b,{3{a,b}}} {b,a,b,a,b,a,b}
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Gate Level Modelling
Logic circuit can be described using basiclogic gates.
The module is a text description of the circuit
layout. Verilog has all the standard gates
and, nand
or, nor xor, xnor
not, buf
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Primatives
The standard logic gates are Verilog systemprimatives.
It is possible to specify new user-defined
primatives (UDPs). UDPs are specified by there truth-table.
UDPs may only have one output.
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Using a Primative
A Primative by itself is not a module.
To use it (e.g. for testing), it needs to beinstantiated in a module.
Its not necessary to explicitly give a name
while instantiating a primitive.
e.g. and (op,in1,in2);
not (op,in);
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Example: Simple Circuit Diagram
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Circuit to code
module smpl_circuit(A,B,C,x,y);input A,B,C;
output x,y;
wire e;
andg1(e,A,B);not g2(y, C);
or g3(x,e,y);
endmodule
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Input signals
In order to simulate a circuit the input signalsneed to be known so as to generate anoutput signal.
The input signals are often called the circuitstimulus.
An HDL module is written to provide the
circuit stimulus. This is known as atestbench.
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Testbench
The testbench module includes the module to betested.
There are no input or output ports for the testbench.
The inputs to the test circuit are defined with regand the outputs withwire.
The input values are specified with the keywordinitial
A sequence of values can be specified betweenbegin and end.
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Stimulus module for simple circuit
module stimcrct;
reg A,B,C;
wire x,y;
Smpl_circuit cwd(A,B,C,x,y);
initialbegin
A = 1'b0; B = 1'b0; C = 1'b0;
#100
A = 1'b1; B = 1'b1; C = 1'b1;#100 $finish;
end
endmodule
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Case Study: Full Adder
A B
CiCo
S
Full
Adder
Ci A B SCo
0 0 0 00
0 0 1 10
0 1 0 10
0 1 1 01
1 0 0 10
1 0 1 01
1 1 0 01
1 1 1 11
51
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Case Study: Full Adder
Co = AB + BCi + CiA
52
A
B
B
CiCi
A
Co
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Case Study: Full Adder
sum = a b ci
53
ab
c
sum
a
b
csum
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Case Study: Full Adder
Full Adder Connection
Instance ins_cfrom FA_co
Instance ins_sfrom FA_sum
54
abc
sum
abb
c
c
a
co
carry out
connection
sumconnection
full adder
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2 to 1 multiplexer
Write the Verilog description for 2 to 1 multiplexer.