1. Chien-Jung Li Nov. 2013 Analog Devices ADF4113 Frequency
Synthesizer
2. 2 Analog Devices ADF4113
3. 3 ADF4113 Spec. Abstract RF characteristics were not shown,
since we are focusing the design of digital interface here.
DSN-3019 Spec. (I guess 3.3V DVDD is used in the packaged
module)
4. 4 Timing Diagram 10 ns 10 ns 25 ns 25 ns 10 ns 2 ns Its
quite easy to meet the timing requirement. MSB go first
24-bits
5. 5 ADF4113 Pin Function Digital Section: 1. 24-bit input
shift register / 14-bit R counter / 19-bit N counter (6-bit A
counter + 13-bit B counter). 2. Data is clocked into the 24-bit
shift register on each rising edge of CLK MSB first. 3. Data is
transferred from the shift register to one of four latches on the
rising edge of LE. The destination latch is determined by the state
of the two control bits (C2, C1) in the shift register. These are
the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table
for these bits is shown in Table 5.
6. 6 4 Types of the Latches
7. 7 R Counter Latch (0, 0) 14-bits div. ratio (0 is not
allowed) PFD deadzone cancel (0, 0) normal How LD is set (not
important) Not important Byte[2] Byte[1] Byte[0]
8. 8 N Counter Latch Byte[2] Byte[1] Byte[0]
9. 9 Function Latch Byte[2] Byte[1] Byte[0] Datasheet
