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Hardware design languageکالس حل تمرین معماری کامپیوتر
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VHDL vs Verilog Verilog
Simpler Hard to switch Almost the same
VHDL VHSIC HDL Based on ADA Preferred by Americans
Just grammarian different!
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Levels of abstractionBehavioral level
Register transfer levelGate level
layout
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VHDL Structural Elements
Entity Architecture Process
library
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Entity Interface description No behavior /
implementation definition
entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end entity HALFADDER;
entity ADDER is port( A, B: in integer range 15 to 0; SUM: out integer range 15 to 0; CARRY: out bit );end ADDER;
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architecture
entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end HALFADDER;
architecture RTL of HALFADDER isbegin SUM <= A xor B; CARRY <= A and B;end architecture RTL;
Implementation of the design Always connected with a specific
entity • one entity can have several
architectures • entity ports are available as
signals within the architecture Contains concurrent statements
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Architecture Structure Declarative part Statement part (after 'begin')
architecture RTL of STRUCTURE is subtype DIGIT is integer range 0 to 9; constant BASE: integer := 10; signal DIGIT_A, DIGIT_B: DIGIT; signal CARRY: DIGIT;begin DIGIT_A <= 3; SUM <= DIGIT_A + DIGIT_B; DIGIT_B <= 7; CARRY <= 0 when SUM < BASE else 1;end EXAMPLE ;
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Entity Port Modes
in buffer inout out
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Component Declaration entity FULLADDER is
port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;
architecture STRUCT of FULLADDER is
component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component;
component ORGATE port (A, B : in bit; RES : out bit); end component;begin signal W_SUM, W_CARRY1, W_CARRY2 : bit;. . .
entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end entity HALFADDER;
entity ORGATE is port( A, B: in bit; RES: out bit);end entity ORGATE;
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Component Instantiationarchitecture STRUCT of FULLADDER is
component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component; component ORGATE port (A, B : in bit; RES : out bit); end component; signal W_SUM, W_CARRY1, W_CARRY2: bit;begin MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 ); MODULE2: HALFADDER port map ( W_SUM, CARRY_IN, SUM, W_CARRY2 ); MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY );
end STRUCT;
Thank you…