Space Codesign Systems Inc.

HW/SW Co-design for Rapid Development

of SoC Embedded Systems

CMC Microsystems, February 2015

Value Proposition

2

Design Optimization, Increase Productivity, Improve/Maintain Quality

System design is dealing with

larger, more complex systems of

Hardware and Software

Development approaching/exceeds

Product life

Design Changes/Errors can be

costly

Costly also in Time Late to

Market!

Traditional HW-Centric Workflow

3

Methodology Impacts Product Development Cycle Time

• Hardware and Software developed on separate paths

• Long design exploration cycles late problem discovery

• Long HW Prototype debug (FPGA, Emulation, etc.)

• Virtual Prototyping has improved speed but not approach

• Risks in Integration Problems prolong time-to-market

time

HW

architecture

C/C++

application

Weeks!

System

Integration

& Test

HW Design

SW & Firmware Devel.

Mapped

Architecture

(Fixed)

SpaceStudio Agile Workflow

4

Methodology Improvement Enabled By Next Generation ESL Technology

• Automated transformation of functions between HW and SW • Reuse the Same Model … Without Recoding

• Automatic Firmware Generation

• Fast High Level Simulation Rapid Virtual Prototyping & Analysis

• Agile Work Flow Immediate Integration and Problem Detection

• Rapid Design Exploration Enabled!

time

HW architecture

with

SystemC TLM

layer

Multi-threaded

C/C++

application

System

Integration

& Test

SW Devel.

HW Design

Architectural Exploration Loop

Mapped

Architecture

(not Fixed)

Co-synthesis

Co

de

sign

SpaceStudio Agile Workflow II

5

Methodology Improvement Enabled By Next Generation ESL Technology

• Automated transformation of functions between HW and SW • Reuse the Same Model … Without Recoding

• Automatic Firmware Generation

• Fast High Level Simulation Rapid Virtual Prototyping & Analysis

• Agile Work Flow Immediate Integration and Problem Detection

• Rapid Design Exploration Enabled!

time

HW architecture

with

SystemC TLM

layer

Multi-threaded

C/C++

application

System

Integration

& Test

SW Devel.

HW Design

Architectural Exploration Loop

Mapped

Architecture

(not Fixed)

Co-synthesis

Co

de

sign

GenX

Sim

tek

Time

Hardware Software Integration and Test

Traditional HW-Centric Workflow Profile Methodology Improvement Enabled By Next Generation ESL Technology

Effort

Time

Value Creation: 1. Getting your product to market in the right time window

Maximize the overlap between the 3 processes 2. Design Quality

HW not fixed => Design Space Exploration yields Optimal Solution

Hardware Software Integration and Test

Methodology Improvement Enabled By Next Generation ESL Technology

Effort

Design time is decreased significantly

SpaceStudio Agile Workflow Profile

Space Codesign’s SpaceStudio

8

The Newest ESL Design Technology

Algorithm / Functional Specification

- Requirements for System Architecture

Architectural Design Exploration

- HW/SW Co-design

- Automation supports HW/SW

Partitioning

- Development of System Architecture

Implementation

Focus on System Architects

9

Algorithm / Functional Specification

Elix

System Specification

Functional validation of specifications

Untimed or Timed functional simulations (loosely timed)

Automatically generated SystemC simulation model of the system

Knowledge of SystemC not required

Multi-threaded C/C++ application specification

Supported communication mechanisms: FIFO-based message passing

Shared-memory communications

Register-based and memory-mapped communications

DMA-based communications (new)

10

Architectural Design Exploration

Simtek (Flow)

QoR

Constraints

Met?

Refinement of

Selected

Architecture

QoR

Constraints

No

Yes

Design SpaceExploration

Loop

ES

L F

low

RT

L F

low

Target

Platform

Executable

Specification

Architecture

Specification

Architecture

Evaluation

Candidate

Architecture

Metrics

11

Architectural Design Exploration

Target Platform

Library of TLM-2.0 models for: Processors Busses and interconnects Memories I/O peripherals

Extensions for third-party or user-defined IPs TLM-2.0 simulation model IP-XACT description for parameters and interfaces of the component

12

Architectural Design Exploration

Architecture Specification

12

3

Target Platform

ConfigureParameters

Mappingto HW or SW

13

Architectural Design Exploration

Architecture Evaluation (1)

Execution (Play/Stop) to run a simulation (Run/Options menu):

• Run/Debug… Hardware: Hardware Modules

– Eclipse-based Debugger (change of view)

• Run/Debug… Software: Software Modules

– Eclipse-based Debugger (change of view)

– Links HW-SW execution (via socket)

• Run/Debug… HW/SW Co-debug

– Eclipse-based Debugger (change of view)

– Links HW-SW execution (via socket)

– Debugging of HW *and* SW interactively in the same engine!

14

Architectural Design Exploration

Architecture Evaluation (2)

Non-intrusive monitoring Metrics for both HW- and SW-mapped tasks:

Task execution times

Inter-task communication timing and traffic volume

Queue and memory usage

Interconnect bandwidth usage

Additional metrics for SW-mapped tasks Processor load

Cache metrics

Read/Write Hit/Miss – per core/interface/level

Task scheduling and context switching

Global metrics or drill down by task

Automation supports HW/SW Partitioning

15

Same Functions are Retargeted for HW or SW

Drag + Drop Configuration 1: All SW Configuration 2: All SW minus IDCT

Drag and Drop Mechanism Eases Design Iteration

Iteration

Task

Coprocessor

16

Automatic Integration

GenX

Export RTL implementation of architecture RTL hardware IPs and glue logic

Embedded firmware and software

Project and files for downstream tools

Supported downstream technologies and tools FPGA Platform Libraries

Automated flow for application-specific accelerators Support of HLS (high level synthesis) flows

RTL generation from C/C++ and SystemC

Space Codesign Implementation Flow

17

Design Creation from Algorithm to Architecture to Implementation

Elix GenX

Functional (algorithm)

Implementation

SpaceStudio Architectural (design exploration, hw/sw co-design)

….

C/C++

Specifica

tion

Simtek

SoC Virtual Platform

CPU Core Models (ISS)

IP Reuse (Mapping)

High Level Synthesis

Silicon SoC

Soft

war

e G

ener

atio

n

Space Codesign in Xilinx Vivado Flow

18

Design Creation Front-End for Xilinx Vivado (including Vivado HLS)

Elix GenX IP

(EDK/ISE)

Synthesis (Vivado HLS)

Xilinx FPGA

Functional (algorithm)

Implementation

SpaceStudio Architectural (design exploration, hw/sw co-design)

Soft

war

e G

ener

atio

n

….

C/C++

Specifica

tion

Simtek

Xilinx Virtual Platform

CPU Core Models (ISS)

Space Codesign Ecosystem

19

Making use of Industry Standards and Leading Technologies

Processor Models

• QEMU (Intel, ARM, PPC, etc.)

• ARM Fast Models (Cortex-A9 dual core)

OS

Standards

HLS Tools

FPGA

IP Modeling

SystemC, TLM-2.0 (IEEE 1666)

IP-XACT (IEEE 1685)

Current R&D Projects

20

University and/or Industry-supported Research Programs

GNSS (various)

• ISAE, U de Toulouse (2010)

MPEG

• Polytechnique/Grass Valley (Belden)

M-JPEG

IRT Saint-Exupery

• Aerospace & Avionics

Space Codesign

Simulate to Stimulate Innovations

21

www.spacecodesign.com