SystemC Overview

林敬倫 , 蘇文鈺成大資訊

2010

Architecture

• C++ and STL– SystemC Simulation Kernel– Thread and Method– TLM 2.0 Lib– AMS (Not Stable yet)– Event and Sensitivity– Channel and Interface– Modules– Data Type

• Predefined Channels: Mutex, FIFO and Signals– IP– User Lib

Environment

• SystemC as a C++ class library, you need– SystemC Library: can be downloaded at:• http://www.systemc.org/downloads

– C++ Compiler: GNU C++, Sun C++,…– O.S.: Solaris, Linux, UNIX, Windows– Compiler command sequence, makefile, or others

similar– GUI (Option available in tools like CoWare and

OpenESL)

Simple Example: Hello world

• Program 規格如下– 用 SC_Method– Clock=10 ns– 每個 clock 印一下” Hello World” 以及現在的時

間– 跑 100 cycles– 可用一般 command line 的方式 compile– 可用 makefile– 執行的過程與結果

Hello World 程式專案說明• 其中包含三個檔案 main.cpp ，

hello_module.h hello_module.cpp• 可將 main.cpp 視同電路板，我們可以在上

面做接線等等的動作。• hello_module 可以被視為是一個具有

process 功能的硬體元件。

Main.cpp將所需元件的 .h 檔和 systemC.h 引

入Sc_main 是 systemC 程式的進入點

宣告一組 clk 的訊號 週期為 10ns

宣告一組 hello_module 的元件

將 clk 接上 module 的 clk 訊號上

開始進行模擬 模擬 1000ns 內的硬體運作

Hello_module.h宣告一組元件定義 hello_module

宣告 hello_module 的訊號線 clk

宣告 hello_module 的運作函式

hello_module 的建構子

整組元件具有 process(method) process 執行的函式 Method_func

Process 會經由 clk 正緣觸發

Hello_module.cpp運作函式本體

訊號有產生改變才執行

印出模擬時間

印出 hello word!

執行結果

Component

• A HW system is usually divided into several separate components.

• Normally, components work independently until communication is needed among components.

• Components can work synchronously or asynchronously• In HW design, certain hierarchy built from components

is required.• Similar development methodology can be found in

CBSD (Component Based Software Development).• In SystemC, components are usually called modules.

Wikipedia says:• CBSD is a branch of software engineering, the priority of which is the

separation of concerns in respect of the wide-ranging functionality available throughout a given software system. Components are considered to be part of the starting platform for service orientation throughout software engineering, for example Web Services, and more recently, Service-Oriented Architecture (SOA) - whereby a component is converted into a service and subsequently inherits further characteristics beyond that of an ordinary component.

• With regards to system-wide co-ordination, components communicate

with each other via interfaces. When a component offers services to the rest of the system, it adopts a provided interface which specifies the services that can be utilized by other components and how.

DataFlow

• CBSD is often incorporated with dataflow model.

• 顧名思義 : 元件之間所需與所產出的資料是用類似資料流的方式傳遞

• 而彼此之間也經常靠資料流在同步其動作

Wikipedia says:

• Dataflow is a software architecture based on the idea that changing the value of a variable should automatically force recalculation of the values of other variables.

• SO, how to use dataflow in programming? – Flow Based Programming.

Wikipedia says:• flow-based programming (FBP) is a programming paradigm that defines applications as networks of "black

box" processes, which exchange data across predefined connections by message passing. These black box processes can be reconnected endlessly to form different applications without having to be changed internally. FBP is thus naturally component-oriented.

• The FBP development approach views an application not as a single, sequential, process, which starts at a point in time, and then does one thing at a time until it is finished, but as a network of asynchronous processes communicating by means of streams of structured data chunks, called "information packets" (IPs). In this view, the focus is on the application data and the transformations applied to it to produce the desired outputs. The network is defined externally to the processes, as a list of connections which is interpreted by a piece of software, usually called the "scheduler".

• The processes communicate by means of fixed-capacity connections. A connection is attached to a process by means of a port, which has a name agreed upon between the process code and the network definition. More than one process can execute the same piece of code. At any point in time, a given IP can only be "owned" by a single process, or be in transit between two processes. Ports may either be simple, or array-type, as used e.g. for the input port of the Collate component described below. It is the combination of ports with asynchronous processes that allows many long-running primitive functions of data processing, such as Sort, Merge, Summarize, etc., to be supported in the form of software black boxes.

• The network definition is usually diagrammatic, and is converted into a connection list in some lower-level language or notation. FBP is thus a visual programming language at this level. More complex network definitions have a hierarchical structure, being built up from subnets with "sticky" connections.

字太多 , 看圖說故事比較快

http://www.edrawsoft.com/Data-Flow-Model-Diagram.php

How components are implemented in SystemC?

• SC_Module: registered in SystemC simulation kernel

• Elaboration– Thread: SC_THREAD or SC_CTHREAD(now seldom

used, but may be useful for synthesizable SystemC syntax)

– Method: SC_Method

SC_METHOD

• A simple member function of SC_MODULE class.

• No arguments and no return values• During simulation, SystemC simulation kernel

calls it repeatedly.• It is also concurrently executed (in concept or

in user’s point of view).

SC_THREAD

• It can suspend itself. So, it allows time to pass by.• Hence, when SC_THREAD is executed one time,

SC_METHOD may have been executed several times.• Conceptually, it is like a software thread, but not

exactly because of the nature of the current simulation kernel. We will touch this later when we introduce the mechanism of this simulation kernel.

• SC_CTHREAD is a SC_THREAD requiring the sensitivity with respect to a clock signal. That is why it may be considered as synthesizable syntax.

Concurrency and Synchronization Mechanisms

• Since all modules have to be executed concurrently in user’s point of view, mechanisms have to be built to maintain the consistency of concurrent execution.

• Events and Notification are applied.• Event is implemented by sc_event class. notify, which is a

member function of sc_event, can be used.• A module is invoked through the sensitivity to certain

events. For example, sensitive to a clock event or a bus event.

• In SystemC, Static and Dynamic of event sensitivity implementations are available.

Communication

• Like all dataflow or CB programming models, communication among modules is important.

• Unlike Verilog, SystemC separates the implementation mechanisms of computation and communication. That is, modules are mainly for computation. Communication is done through provided interface and channel.

• Channel is used to interconnect modules.• Port is used to connect channel to module.• Interface can be used when implementing channels.

Modules

Ports Ports

Events

Threads&Methods

Channels

Interface Only Port plus Interface

System Component

Hierarchical Structure

• A component may contain several modules and the component is itself a module.

• A component contains intra-communication mechanisms such as ports interfaces, and channels.

• A component also contains ports for inter-communication, which will be connected to some channels.

• Events are contained for synchronization and execution.

• Computation part is realized in internal modules.

Spec. of Example program

• 規格 :– 系統有兩個 modules, 每一個 module 又包含兩個

modules, 利用 clock 來做 event– 主要的兩個 modules 的工作只是互相交換資料 , 簡單

運算後再傳回給對方– 主要模組中的內部兩個模組又分成運算與存檔的工作 .– 主要的兩個 modules 用簡單的 bus 連接 , 內部兩個模

組用簡單的 channel 連接– 用 SC_METHOD 與 SC_THREAD 來實現之 , 也就是一個

module 用 SC_METHOD, 另外一個 module 用SC_THREAD

Example Program Abstract

• Thread module 內有兩組 sub module 為 save module 及 alu module– save module 用於將 thread module 現存的費氏數

列兩個數字存入檔案中– alu module 利用已存費氏數列數字計算下兩組數

字• 兩組 thread module 透過 bus 連接將計算好的

下兩位數字透過 bus 傳給另一組 thread module使整份檔案輸出一組完整的費氏數列並標註寫入檔案的 module

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

Data(1,1)

save aluprocess

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

Data(1,1)

save aluprocess

Data(2,3)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(2,3)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(2,3)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(2,3)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(2,3) Data(5,8)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(5,8)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

save aluprocess

Data(5,8)

save alu

CLK

BUS

Thread module0

Thread module

Write port

Write port

Write port

Write port

process

Data(5,8)

save aluprocess

Main.cpp

Bus_if.h

Alu.h

Alu.cpp

Bus.h

Bus.cpp

Save.h

Save.cpp

Thread.h

Thread.h

Thread.cpp