A Standard VME Chassis

BT AB/CO/MI 18th September 2007

Safe Machine ParametersChassis

Safe Machine Parameters System 2 of 26 benjamin.todd@cern.ch

A Standard VME Chassis

Has 21 Slots!

The cards that were proposed by Bruno last time are:

Frame Receiver – CISREnergy Down Sampler – CISE

Frame Transmitter – CISTTiming Receiver VME – CTRV

Timing Receiver Interface – CISIFlag Generator – CISG

Generator Arbiter – CISASMP Transmission Cross-Checker – CISCBeam Interlock System Interface – CISF

Chassis Debugger – CISD

Safe Machine Parameters System 3 of 26 benjamin.todd@cern.ch

A Standard VME Chassis

Has 21 Slots!

The cards that were proposed by Bruno last time are:

Frame Receiver – CISREnergy Down Sampler – CISE

Frame Transmitter – CISTTiming Receiver VME – CTRV

Timing Receiver Interface – CISIFlag Generator – CISG

Generator Arbiter – CISASMP Transmission Cross-Checker – CISCBeam Interlock System Interface – CISF

Chassis Debugger – CISDCISB

Safe Machine Parameters System 4 of 26 benjamin.todd@cern.ch

A Standard VME Chassis

Has 21 Slots!

Frame Receiver – CISREnergy Down Sampler – CISE

Frame Transmitter – CISTTiming Receiver VME – CTRV

Timing Receiver Interface – CISIFlag Generator – CISG

Generator Arbiter – CISASMP Transmission Cross-Checker – CISCBeam Interlock System Interface – CISB

Chassis Debugger – CISD

X4 (side by side)X1 (after CISR)X1 (after CISE)

X1 (after CIST, before CIBI)X1 (after CIST)

X2 (side by side, after CISE)X1 (after CISE)X1 (after CISI)X1 (after CISG)

X1 (last board in chassis)

Total is 14 boards + Power PC = 15 slots!6 left

Safe Machine Parameters System 5 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

A VME chassis has 21 slots…

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

Safe Machine Parameters System 6 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

A VME chassis has 21 slots…

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

Safe Machine Parameters System 7 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Power PC:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

1 2 3 4

Pow

er P

CPow

er P

C

Safe Machine Parameters System 8 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

First receiver

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

1 2 3 4

Pow

er P

CPow

er P

C

5 6 7 8

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Safe Machine Parameters System 9 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Other receivers (x4)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

Safe Machine Parameters System 10 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Energy Down-Sampler

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

Safe Machine Parameters System 11 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

First Flag Generator

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A

Safe Machine Parameters System 12 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Second Flag Generator

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B

Safe Machine Parameters System 13 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Arbiter

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

Safe Machine Parameters System 14 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

BIC Interface

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

49 50 51 52

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

Safe Machine Parameters System 15 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Frame Transmitter

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

49 50 51 52

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

53 54 55 56 57 58 59 60SL

OT 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T

Safe Machine Parameters System 16 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Timing Receiver

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

49 50 51 52

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

53 54 55 56 57 58 59 60SL

OT 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T61 62 63 64

Tim

ing

Rec

eive

r –

CTR

VSL

OT 1

6

Safe Machine Parameters System 17 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Interface Timing to SMP (plus clocks??)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

49 50 51 52

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

53 54 55 56 57 58 59 60SL

OT 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T61 62 63 64

Tim

ing

Rec

eive

r –

CTR

VSL

OT 1

6

65 66 67 68

Tim

ing

Rec

eive

r In

terf

ace

& C

lock

s –

CIS

ISL

OT 1

7

Safe Machine Parameters System 18 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Cross-Checker

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

SLO

T 2

SLO

T 3

SLO

T 4

SLO

T 5

SLO

T 6

SLO

T 7

SLO

T 8

SLO

T 9

SLO

T 1

0

SLO

T 1

1

SLO

T 1

2

SLO

T 1

3

SLO

T 1

4

SLO

T 1

5

SLO

T 1

6

SLO

T 1

7

SLO

T 1

8

SLO

T 1

9

SLO

T 2

0

SLO

T 2

1

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

A B C D1 2 3 4

Pow

er P

CPo

wer

PC

21 22 23 24 25 26 27 28

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

29 30 31 32 33 34 35 36

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

A37 38 39 40 41 42 43 44

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

B45 46 47 48

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

49 50 51 52

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

53 54 55 56 57 58 59 60SL

OT 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T61 62 63 64

Tim

ing

Rec

eive

r –

CTR

VSL

OT 1

6

65 66 67 68

Tim

ing

Rec

eive

r In

terf

ace

& C

lock

s –

CIS

ISL

OT 1

7

69 70 71 72 73 74 75 76

SLO

T 1

8

SLO

T 1

9SM

P T

rans

mis

sion

Cro

ss-C

heck

er –

CIS

C

Safe Machine Parameters System 19 of 26 benjamin.todd@cern.ch

Proposed Chassis SMP

Debugger

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

Pow

er P

C

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

SLO

T 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T

Tim

ing

Rec

eive

r –

CTR

VSL

OT 1

6

Tim

ing

Rec

eive

r In

terf

ace

& C

lock

s –

CIS

ISL

OT 1

7

SLO

T 1

8

SLO

T 1

9SM

P T

rans

mis

sion

Cro

ss-C

heck

er –

CIS

C

SLO

T 2

0

SLO

T 2

1C

hass

is D

ebug

ger –

CIS

D

A BA B C D

Pow

er P

CSL

OT 1

Safe Machine Parameters System 20 of 26 benjamin.todd@cern.ch

Details

All boards classic 4/8TE wide (we’ve done these already!)

Intercommunications done through P2

Could be done using Panel and Extenders

(a la BIC)

If it is this way - each board could have 55 differential I/O through P2.

Panel could be tricky though… let’s take a look:

Safe Machine Parameters System 21 of 26 benjamin.todd@cern.ch

Chassis SMP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

SLO

T 1

Pow

er P

C

Fram

e R

ecei

ver –

CIS

RSL

OT 2

Fram

e R

ecei

ver –

CIS

RSL

OT 3

Fram

e R

ecei

ver –

CIS

RSL

OT 4

Fram

e R

ecei

ver –

CIS

RSL

OT 5

SLO

T 6

SLO

T 7

Ene

rgy

Dow

n-Sa

mpl

er –

CIS

E

SLO

T 8

SLO

T 9

Flag

Gen

erat

or –

CIS

G

SLO

T 1

0

SLO

T 1

1Fl

ag G

ener

ator

– C

ISG

Gen

erat

or A

rbiter

– C

ISA

SLO

T 1

2

SMP B

IC Int

erfa

ce –

CIS

BSL

OT 1

3

SLO

T 1

4

SLO

T 1

5Fr

ame

Tra

nsm

itte

r –

CIS

T

Tim

ing

Rec

eive

r –

CTR

VSL

OT 1

6

Tim

ing

Rec

eive

r In

terf

ace

& C

lock

s –

CIS

ISL

OT 1

7

SLO

T 1

8

SLO

T 1

9SM

P T

rans

mis

sion

Cro

ss-C

heck

er –

CIS

C

SLO

T 2

0

SLO

T 2

1C

hass

is D

ebug

ger –

CIS

D

A BA B C D

Pow

er P

CSL

OT 1

Safe Machine Parameters System 22 of 26 benjamin.todd@cern.ch

Chassis SMP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

CISR CISR CISR CISR CISE CISG CISG CISA CISB CIST CTRV CISI CISC CISD

Pow

er P

CPow

er P

C

Safe Machine Parameters System 23 of 26 benjamin.todd@cern.ch

Chassis SMP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

CISR CISR CISR CISR CISE CISG CISG CISA CISB CIST CTRV CISI CISC CISD

Pow

er P

CPow

er P

C

Add the 3 x 32 connectors to each board:

Safe Machine Parameters System 24 of 26 benjamin.todd@cern.ch

Chassis SMP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

CISR CISR CISR CISR CISE CISG CISG CISA CISB CIST CTRV CISI CISC CISD

Pow

er P

CPow

er P

C

Add some Burndy for CIBU!

Safe Machine Parameters System 25 of 26 benjamin.todd@cern.ch

Chassis SMP

We’ve done this before...

14 bundies could be used for many things:

Flag Arbiter Beam-1 FaultFlag Arbiter Beam-2 Fault

Safe Machine Parameters Beam-1 Cross-Check FaultSafe Machine Parameters Beam-2 Cross-Check fault

SPS Safe Injection Flag for LHC Beam-1SPS Safe Injection Flag for LHC Beam-2

etc

Safe Machine Parameters System 26 of 26 benjamin.todd@cern.ch

FIN