ARM Cortex

*ARM Cortex-M l mt nhm RISC ARM 32 bit,c cp php bi ARM Holdings,c s dng lm vi iu khin,gm c Cortex-M0,M0+,M1,M3,M4 v M7*ARM License-ARM Holdings khng phi nh sn xut cng khng bn cc thit b CPU da trn mu thit k ring ca mnh, nhng thay vo d ARM Hodings cung cp mt lot cc linh kin cp php.H cung cp mt m t integratable phn cng ca li ARM, cng nh hon thnh cng c pht trin phn mm*Silicon ty bin-Cc nh sn xut thit b tch hp (IDM) x l ARM IP nhu RTL synthesizable (vit bng Verilog). Trong hnh thc ny, h c kh nng thc hin ti u ha mc kin trc v phn m rng. iu ny cho php cc nh sn xut t oc mc tiu thit k ty chnh, chng hn nh ng h tc cao hn,tiu th in nng rt thp, m rng tp lnh, ti u ha cho kch thc, h tr g li,vv... xc nh cc thnh phn c a vo trong mt chip ARM CPU c th, tham kho datasheet nh sn xut v cc ti liu lin quan.-Mt s ty chn quan trng nht cho cc li Cortex-M l:+SysTick timer: Mt h thng timer 24-bit m rng cc chc nng ca c hai b vi x l v cc Nested vector Interrupt Controller (NVIC). Khi c mt, n cung cung cp thm cu hnh u tin SysTick ngt.Mc d cc b m thi gian SysTick l ty chn, him khi thy mt vi iu khin Cortex-M m khng c n.+Bit-banding: bn 1 t hon chnh ca b nh trong khu vc bit-band. V d, vit mt t b danh s thit lp hoc xa cc bit tng ng trong khu vc bit-band. iu ny cho php tt c cc bit ring l trong khu vc bit-band c th truy cp trc tip t mt a ch word-aligned,v cc bit ring l c bt t C / C ++ m khng thc hin mt chui c-chnh sa-ghi cc hng dn.+Memory Unit Protection (MPU): Cung cp h tr cho vic bo v cc khu vc ca b nh thng qua vic thc thi quyn v truy cp cc quy tc. N h tr ln n tm khu vc khc nhau...............................................Bng1.......................................+Luu : Hu ht Cortex-M3 v M4 c bit-banding v MPU. Cc ty chn bit-banding c th c thm vo Cortex-M0 / M0 +Tnh dn 26 thng 9 nam 2014, Cortex-M7 c th khng c bit-banding+Lu : Phn mm s xc nhn s tn ti ca mt tnh nang trc khi c gng s dng n*Ty chn silicon b sung:+Data Endianness:Khng ging nhu cc dng ARM, Cortex-M c c nh vnh vin trong silicon+Interrupts:1-32 (Cortex-M0 / M0 + / M1), 1-240 (Cortex-M3 / M4 / M7).+Wake-up interrupt controller: Ty chn.+Vector Table Offset Register: Ty chn+Hng dn ly width: 16-bit, hoc ch yu l 32-bit.+H tr ngi s dng / c quyn: Ty chn.+Thit lp li tt c cc thanh ghi: Ty chn.+Chu trnh n cng I / O: Ty chn.+Debug truy cp Port (DAP): Ty chn.+H tr debug Tm dng: Ty chn.+B so snh watchpoint: 0-2 (Cortex M0 / M0 + / M1), 0-4 (Cortex-M3 / M4 / M7)+B so snh breakpoint: 0-4 (Cortex M0 / M0 + / M1), 0-8 (Cortex-M3 / M4 / M7).*Instruction setsCortex-M0 / M0 + / M1 thc hin cc kin trc ARMv6-M,Cortex-M3 thc hin cc kin trc ARMv7-M,v Cortex-M4 / M7 thc hin cc kin trc ARMv7E-M.kin trc l cc hng dn nh phn tr ln tng thch t ARMv6-M n ARMv7-M n ARMv7E-M.Hng dn nh phn c sn cho Cortex-M0 / M0 + / M1 c th thc hin m khng cn sa i trn Cortex-M3 / M4 / M7.Hong dn nh phn c sn cho Cortex-M3 c th thc hin m khng cn sa i trn Cortex-M4 / M7.Tp hong dn Thumb v Thumb-2 uu c h tr trong kin trc Cortex-M , nhng vi tp lnh ca ARM 32bit khng c h tr.Tt c su li Cortex-M thc hin mt tp hp con chung hng dn c hu ht cc Thumb trong c mt kt qu 32-bit nhn. Cortex-M0 / M0 + / M1 c thit k to ra cc khun silicon nh nht, do c cc hng dn t nht trong gia dnh Cortex-M.Cortex-M0 / M0 + / M1 gm hng dn Thumb (tr hng dn mi (CBZ, CBNZ, IT) c b sung vo kin trc ARMv7-M ).Cortex-M0 / M0 + / M1 gm mt tp hp con nh ca hong dn Thumb-2 (BL, DMB, DSB, ISB, MRS, MSR).Cortex-M3 / M4 / M7 c tt c Thumb c s v hng dn Thumb-2. Cortex-M3 thm 3 hng dn Thumb gm tt c hng dn Thumb-2, chia phn cng, v lnh ton hc bo ha.Cortex-M4 thm hng dn DSP v single-precision floating-point (VFPv4-SP).Cortex-M7 thm mt ty chn double-precision FPU (VFPv5)..........................................................Bng2.....................Luu : Cc hng dn Thumb 16-bit ca Cortex-M0 / M0 + / M1 khng bao gm : CBZ, CBNZ, ITLuu : Cortex-M0 / M0 + / M1 ch bao gm cc Thumb-2 hng dn 32-bit:BL, DMB, DSB, ISB, MRS, MSRLuu : Cortex-M0 / M0 + / M1 ch c hng dn 32-bit nhn vi mt kt qu thp hn 32-bit (32bit 32bit = 32bit thp hn),vi Cortex-M3 / M4 / M7 bao gm thm 32-bit nhn vi kt qu 64-bit (32bit x 32bit = 64bit).Cortex-M4 / M7 cung bao gm hng dn cho DSP (16bit 16bit = 32bit), (32bit x 16bit = trn 32bit), (32bit 32bit = trn 32bit)Nu mt die silicon nh hn cn thit, Cortex-M0 / M0 + / M1 c mt ty chn c mt hng dn chm hn nhiu,mc d n him khi c thc hin trong M0 hoc M0 +.Luu : Cortex-M4 c mt la chn FPU silicon (VFPv4-SP) ca single-precision (SP),v c bit n nh mt Cortex-M4F.Cortex-M7 c cc ty chn FPU silicon (VFPv5) c?a single-precision (SP) hoc both single-precision (SP) v double-precision (DP)Nu Corex-M4 hoc M7 c mt FPU th c gi l Cortex-M4F hoc Cortex-M7F.Luu : 3 hng dn 16-bit Thumb cho ch ng ca cc dng Cortex-M bao gm : SEV, WFE, WFI............................................Bng 3..............................................Luu : Cc hng dn FPU single-precision (SP) hp l trong Cortex-M4 / M7 ch khi ty chn SP FPU tn ti trong silicon.Luu : Double-precision (DP) FPU l hp l trong Cortex-M7 ch khi ty chn DP FPU tn ti trong silicon.