View
9
Download
0
Category
Preview:
Citation preview
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
CH9 Multiplexers, Decoders, and CH9 Multiplexers, Decoders, and Programmable Logic DevicesProgrammable Logic Devices
Lecturer : 吳安宇Date : 2005.11.25
Graduate Institute of Electronics Engineering, NTU
pp. 2
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 3
Integrated Circuits (IC)Integrated Circuits (IC)
v Small-Scale Integrated Circuit (SSI):
vMedium-Scale IC (MSI)
v Large-Scale IC (LSI) : Arithmetic-Logic Unit (ALU)
v Very Large-Scale IC (VLSI)
NORNANDNOTXORMultiplexer
Decoder
Graduate Institute of Electronics Engineering, NTU
pp. 4
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 5
Multiplexers(1/2)Multiplexers(1/2)
A B Z0 0 I00 1 I11 0 I21 1 I3
I0I1I2I3
Z
A B
Graduate Institute of Electronics Engineering, NTU
pp. 6
Multiplexers(2/2)Multiplexers(2/2)Z = A’B’I0 + A’BI1 + AB’I2 + ABI3
= m0I0 + m1I1 + m2I2 + m3I3 ( mi : ith Minterm )
A B
I0
I1
I2
I3
z
AND-OR Network
Graduate Institute of Electronics Engineering, NTU
pp. 7
∑−
=
=12
0
n
kkkImz
2n-to-1Mux
Z
2n
DataLines
n control Inputs
General 2General 2nn--toto--1 Multiplexer1 Multiplexer
Graduate Institute of Electronics Engineering, NTU
pp. 8
Application: Quad MultiplexerApplication: Quad Multiplexer
sel
A B
C
A= ( a3a2a1a0 )B= ( b3b2b1b0 )
C= ( c3c2c1c0 )
sel 2-to-1
a3 b3
c3
2-to-1
a2 b2
c2
2-to-1
a1 b1
c1
2-to-1
a0 b0
c0
AB
01
CSel
(4-bit word selector): A=(a3 a2 a1 a0)
4 4
4
Graduate Institute of Electronics Engineering, NTU
pp. 9
)0'('''1)'(''''),,(⋅+⋅+⋅+⋅=
++=+=BACABCABBA
BBACBAACBACBAF
0 0 1 0 1 1 0 1
1C0C
I0I1
I3
I2Z=A’B’+AC
A B
1C0C
0 00 11 01 1
ZA B
Realize Combinational Logic FunctionRealize Combinational Logic Function
Graduate Institute of Electronics Engineering, NTU
pp. 10
Ex: Use 8Ex: Use 8--toto--1 Mux to Realize F(A, B, C)1 Mux to Realize F(A, B, C)
0110
1011
0001
1101
00 01 11 10AB
CD00011110
ABC = 001 ABC = 101
ABC = 000
0
1
Z
A B C
1D01D’
D’
DD’
I0
I5I6I7
I2I3I4
I1
8-to-1MUX
D10
I1=D
0
1D01
I6=D’
Graduate Institute of Electronics Engineering, NTU
pp. 11
Ex: use 8Ex: use 8--toto--1 Mux to Realize F(A,B,C,D)1 Mux to Realize F(A,B,C,D)
D’DD’D’
1 0 01 0 11 1 01 1 1
4567
1D01
0 0 00 0 10 1 00 1 1
0123
ZA B C
C’C10
1 0 01 0 11 1 01 1 1
4567
C’1CC
0 0 00 0 10 1 00 1 1
0123
ZA B D
F = A’B’C’ + B’CD + A’BC + A’BC + AC’D’(From K-map)
0110
1011
0001
110100 01 11 10
AB
CD00011110
I0=C’ I1=1I2=C I3=CI4=C’ I5=CI6=1 I7=0
Graduate Institute of Electronics Engineering, NTU
pp. 12
Ex. 4Ex. 4--toto--1 Mux to Realize 1 Mux to Realize F(A,B,C,D)F(A,B,C,D)
11 0
11 1
00 1
00 0
I1C D
01 0
11 1
00 1
10 0
I1C D
11 0
01 1
00 1
10 0
I1C D
0110
1011
0001
1101
00 01 11 10AB
00011110
CD
01 011 110 110 0I1C D
''''
')'(
3
2
1
0
DIDCCDDCI
CIDCCDI
=⊕=+=
=+==
I0I1I2I3
Z
A B
C
D’
C’DC’D
AB=00
AB=01 AB=10 AB=11
Graduate Institute of Electronics Engineering, NTU
pp. 13
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 14
ThreeThree--state Buffer(1/3)state Buffer(1/3)
F = C ó Buffer Gate
Gate Circuit with added Buffer
F C
Realization using Invert pairs
CF
Graduate Institute of Electronics Engineering, NTU
pp. 15
ThreeThree--state Buffer(2/3)state Buffer(2/3)
01 0
11 1
Z0 1
Z0 0
CB A
Z1 0
Z1 1
00 1
10 0
CB A
11 0
11 1
Z0 1
Z0 0
CB A
Z1 0
Z1 1
10 1
00 0
CB A
B = 1, C=A0, Open circuit
(High-impedance)
Operations of tri-state buffers
•Active High•Active Low
Graduate Institute of Electronics Engineering, NTU
pp. 16
ThreeThree--state Buffer(3/3)state Buffer(3/3)
x x x xx 0 x 0x x 1 1x 0 1 z
x01z
x 0 1 z Outputs of both Tri-state Buffers
(B,D are independent)
S1
S2
S2
S1
Graduate Institute of Electronics Engineering, NTU
pp. 17
Application of triApplication of tri--state bufferstate buffer
Bi-directional I/O pinBi-directional means that the same pin can be used as can input pin and as an output pin, but not both at the same time
{EnA, EnB, EnC, EnD} should be exclusive ( Only 1 active )
è Bus structure:Multiple I/O on a Busfor communication
4-bit adder with 4 sourcesfor one operand:
Graduate Institute of Electronics Engineering, NTU
pp. 18
Graduate Institute of Electronics Engineering, NTU
pp. 19
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 20
33--toto--8 Decoder8 Decoder
1 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
y0 y1 y2 y3 y4 y5 y6 y7a b c
Master
Decode 0Decode 1Decode 2Decode 3Decode 4Decode 5Decode 6Decode 7
Binary number(a2a1a0)
Graduate Institute of Electronics Engineering, NTU
pp. 21
Realization a DecoderRealization a Decoder
0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0 1 2 3 4 5 6 7 8 9A B C D
Decimal OutputBCD input
(a) Logic Diagram
(b) Block Diagram (with active-low output)
(c) Truth table
Graduate Institute of Electronics Engineering, NTU
pp. 22
An nAn n--toto--22nn decoder generate 2decoder generate 2n n mintermsminterms
)9,7,4(),,,()4,2,1(),,,(
9742
4211
mmmmdcbafmmmmdcbaf
∑=++=∑=++=
1
1
20,)'(
20,−
−
===
==n
iii
nii
toiMmytoimy
(Inverted outputs)
(non-Inverted outputs)
Ex:
)''''()''''(
9742
4211
mmmfmmmf⋅⋅=
⋅⋅= (NAND)
(NAND)
using MSI 7442(BCD input decoder)M > 10 is not allowed when
Graduate Institute of Electronics Engineering, NTU
pp. 23
Priority Encoders (8Priority Encoders (8--toto--3)3)
y0 y1 y2 y3 y4 y5 y6 y7 a b c d0 0 0 00 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0x 1 0 0 0 0 0 0x x 1 0 0 0 0 0x x x 1 0 0 0 0x x x x 1 0 0 0x x x x x 1 0 0
0 1 0 10 1 1 11 0 0 1
0 0 0 10 0 1 1
1 1 0 11 1 1 1
1 0 1 1
x x x x x x x 1x x x x x x 1 0
No signal
happen
Event detect with priority!è y7 > y6 > ….. > y0
Graduate Institute of Electronics Engineering, NTU
pp. 24
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 25
ReadRead--only Memory (ROM)only Memory (ROM)v An 8-word x 4-Bit ROM:
Each word is 4-bit, total 8 words in this ROM
1 0 1 01 0 1 00 1 1 10 1 0 11 1 0 00 0 0 11 1 1 10 1 0 1
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
F0 F1 F2 F3A B C
v Input (ABC)=23 input values (0~7 address)
v Output:(F0 F1 F2 F3 )=(word)
Typical datastored in ROM(2n words of 4 bits each)
Graduate Institute of Electronics Engineering, NTU
pp. 26
100…110010…111101…101110…010
001…011110…110011…000111…101
00…0000…0100…1000…11
11…0011…0111…1011…11
m-bit Output data
n-bit input address
Generalized Form ( Generalized Form ( nn--inputs/minputs/m--outputsoutputs ))
typical dataarray storedin ROM(2n words,
each m-bits)
Size = m x 2n (bits)
Graduate Institute of Electronics Engineering, NTU
pp. 27
Basic ROM Structure (A Decoder + Basic ROM Structure (A Decoder + Memory Array)(1/2)Memory Array)(1/2)
M output lines
Fig. 9-19Basic ROM Structure
2n entries
Graduate Institute of Electronics Engineering, NTU
pp. 28
ReadRead––only memoryonly memory
Types:
Mask-programmed ROM
Erasable Programmable ROM(EPROM)
Electrically Erasable Programmable ROM (EEPROM)
x0x1
xn-1
CS
A0A1
An-1
Device accessControl signal(chip select)
Addressinputs
AND array
Word 0
Word 1
Word 2n-1
y0y1
y2n
-1
n-to-2nAddressdecoder
OR Array
Product terms(minterms) O1 O2 O3
Data outputs(sum terms)
Graduate Institute of Electronics Engineering, NTU
pp. 29
Basic ROM Structure Basic ROM Structure (A Decoder + Memory Array)(2/2)(A Decoder + Memory Array)(2/2)
1 1 0 00 0 0 11 1 1 10 1 0 1
4567
1 0 1 01 0 1 00 1 1 10 1 0 1
0123
F0 F1 F2 F3
BACmFBCBAmFACBmFACBAmF
+=∑=+=∑=
+=∑=+=∑=
)7,6,5,3,2(''')6,2,1,0(')7,6,4,3,2(''')6,4,1,0(
3
2
1
0
Graduate Institute of Electronics Engineering, NTU
pp. 30
Contents of ROM specifies a Contents of ROM specifies a ““TRUTH TABLETRUTH TABLE””
0 1 1 0 0 0 00 1 1 0 0 0 10 1 1 0 0 1 00 1 1 1 0 00 1 1 0 1 0 10 1 1 0 1 1 00 1 1 0 1 1 10 1 1 1 0 0 00 1 1 1 0 0 11 0 0 0 0 0 11 0 0 0 0 1 01 0 0 0 0 1 11 0 0 0 1 0 01 0 0 0 1 0 11 0 0 0 1 1 0
0123456789ABCDEF
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
ASCII Code for Hex DigitA6 A5 A4 A3 A2 A1 A0
HexDigit
InputW X Y Z
Sameinvert
Graduate Institute of Electronics Engineering, NTU
pp. 31
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devices (PLD)v9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 32
N-by-m PLD
Programmable Logic Device (PLD)(1/3)
Graduate Institute of Electronics Engineering, NTU
pp. 33
1 0 1 01 1 0 00 1 0 10 0 1 00 0 0 1
0 0 -1 - 0- 1 -- 1 01 - 1
A’B’AC’BBC’AC
OutputsF0 F1 F2 F3
InputsA B C
Product Term.
ACBFBCBAF
BACFACBAF
+=+=
+=+=
3
2
1
0
''''
'''
Programmable Logic Device (PLD) (2/3)Programmable Logic Device (PLD) (2/3)v AND plane generates minterm (Product terms)v OR plane sums the product terms
Graduate Institute of Electronics Engineering, NTU
pp. 34
)15,14,13,9,8,7,6()15,14,11,10,7,6,5,3,2(
)15,13,11,10,9,8,7,5,3,2(
3
2
1
mfmfmf
∑=∑=∑= a’bd
abdab’c’b’ccbc
1 1 01 0 11 0 11 0 00 1 00 0 1
0 1 – 11 1 – 11 0 0 –– 0 1 –– – 1 –– 1 1 –
f1 f2 f3a b c d
Programmable Logic Device (PLD) (3/3)Programmable Logic Device (PLD) (3/3)
abdcabbcfbdacf
cbcababdbdaf
++=+=
+++=
'''
''''
3
2
1
Graduate Institute of Electronics Engineering, NTU
pp. 35
Programmable Array Logic (PAL)Programmable Array Logic (PAL)(1) Notation
(2) Fixed product terms
Graduate Institute of Electronics Engineering, NTU
pp. 36
PAL : PAL : Fixed OR arrayFixed OR array
Fixed Number of Minterms entering the OR Array(4 minterms in the figure)
Graduate Institute of Electronics Engineering, NTU
pp. 37
Implementation of Full Adder using PALImplementation of Full Adder using PAL
0 01 01 00 11 00 10 11 1
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Sum CoutX Y Cin
XYYCinXCinCoutXYCinCinXYYCinXCinYXSum
++=+++= ''''''
Graduate Institute of Electronics Engineering, NTU
pp. 38
Programmable Array Logic (PAL)Programmable Array Logic (PAL)
Programmable array logic (PAL) device (minterms = 3)
Standard PAL representation
Graduate Institute of Electronics Engineering, NTU
pp. 39
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devices
(skipped)v9.8 Field Programmable Gate Arrays
Graduate Institute of Electronics Engineering, NTU
pp. 40
Complex Programmable Logic Device Complex Programmable Logic Device (CPLD)(CPLD) (skipped)(skipped)
Tools will program for you
Architecture of Xilinx XCR3064XL CPLD
Graduate Institute of Electronics Engineering, NTU
pp. 41
CPLD Function Block and CPLD Function Block and MacrocellMacrocell(skipped)(skipped)
(a Simplified Version of XCR3064XL)
Graduate Institute of Electronics Engineering, NTU
pp. 42
OutlineOutlinev9.1 Introductionv9.2 Multiplexersv9.3 Three-State Buffersv9.4 Decoders and Encodersv9.5 Read-Only Memoriesv9.6 Programmable Logic Devicesv9.7 Complex Programmable Logic Devicesv9.8 Field Programmable Gate Arrays (FPGA)
Graduate Institute of Electronics Engineering, NTU
pp. 43
Field Programmable Gate Arrays Field Programmable Gate Arrays (FPGA)(FPGA)
Layout of a Typical FPGA
Graduate Institute of Electronics Engineering, NTU
pp. 44
Simplified Simplified Configurable Logic Block (CLB)
Graduate Institute of Electronics Engineering, NTU
pp. 45
Implementation of a Implementation of a Lookup Table (LUT)Lookup Table (LUT)
01
1
0 0 0 00 0 0 0
1 1 1 1
Fa b c d
StoredRAM
Graduate Institute of Electronics Engineering, NTU
pp. 46
Decomposition of Switching FunctionDecomposition of Switching Function
-- Purpose: Reduce input variablesf(a,b,c,d) = a’ f(0,b,c,d) + af(1,b,c,d) = af1+a’f0
Ex: f(a,b,c,d) = c’d’ + a’b’c + bcd + ac’= c’d’(a+a’) + a’b’c + bcd(a+a’) + ac’= a’(c’d’+b’c+bcd) + a(c’d’+bcd+c’)= a’(c’d’+b’c+cd) + a(c’+bd)= a’f0 + af1
Graduate Institute of Electronics Engineering, NTU
pp. 47
KK--map approachmap approach
a=0, f0 = c’d’+b’c+cda=1, f1 = c’+bd
0001
0111
1100
1111
00 01 11 10ab
cd00011110 0001
0111
1100
1111
00 01 11 10ab
cd00011110
F0 F1F
a=0 a=1
Graduate Institute of Electronics Engineering, NTU
pp. 48
Generalized expressionGeneralized expression
10
1121
1121
1121
'),,,1,,,,(
),,,0,,,,('),,,,,,,(
fxfxxxxxxfx
xxxxxfxxxxxxxf
ii
niii
niii
niii
+=
+=
+−
+−
+−
LL
LL
LL
Input variables Reduces from n to (n-1)
onefunction
twofunctions
Graduate Institute of Electronics Engineering, NTU
pp. 49
Ex: 5Ex: 5--variable functionvariable function
10'),,,,1(),,,,0('),,,,(
fafaedcbfaedcbfaedcbaf
⋅+⋅=⋅+⋅=
Two 4-variable functions+ 2-to-1 Mux(controlled by a)
Graduate Institute of Electronics Engineering, NTU
pp. 50
Ex: 6Ex: 6--variable functionvariable function
10'),,,,,1(),,,,,0('),,,,,(
GaGafedcbaffedcbfafedcbaG
⋅+⋅=+=
0100
0
'),,,,1,0(),,,,0,0('
GGbfedcbGfedcGbG
+=
+=1110
1
'),,,,1,1(),,,,0,1('
bGGbfedcbGfedcGbG
+=+=
11100100 '''' abGGabbGaGbaG +++= Four 4-variablefunctions+3 2-to-1 mux
Recommended