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Embedded Processor BasedEmbedded Processor BasedBuiltBuilt--In SelfIn Self--Test and DiagnosisTest and Diagnosis
of FPGA Core in FPSLIC of FPGA Core in FPSLIC John John SunwooSunwoo (Logic BIST)(Logic BIST)
SrinivasSrinivas GarimellaGarimella (RAM BIST)(RAM BIST)SudheerSudheer VemulaVemula (I/O Cell BIST)(I/O Cell BIST)
Chuck Stroud (Routing BIST)Chuck Stroud (Routing BIST)Jonathan Harris (original Logic and Routing BIST)Jonathan Harris (original Logic and Routing BIST)
1/19/09 Embedded Systems Lecture 2
Atmel AT94K FPSLIC ArchitectureAtmel AT94K FPSLIC ArchitectureField Programmable Gate ArrayField Programmable Gate Array
up to 48x48 array of Programmable up to 48x48 array of Programmable Logic Blocks (PLBs)Logic Blocks (PLBs)
RAM coresRAM cores32x4 bit RAMs distributed in FPGA32x4 bit RAMs distributed in FPGAProgram memory (up to 32 Kbyte)Program memory (up to 32 Kbyte)
Single port to processorSingle port to processorData RAM (up to 16 Kbyte)Data RAM (up to 16 Kbyte)
Dual port to FPGA & processorDual port to FPGA & processor
88--bit RISC processor corebit RISC processor coreVarious peripheralsVarious peripheralsProcessor can write (but not read) Processor can write (but not read) FPGA configuration memoryFPGA configuration memory
Dynamic partial reconfigurationDynamic partial reconfigurationPr
ogra
mPr
ogra
mM
emor
yM
emor
y
RISCRISCProcessorProcessor
FPGAFPGA
DataDataRAMRAM
ConfigConfigmemorymemory
PeripheralsPeripherals
1/19/09 Embedded Systems Lecture 3
FPGA Core ArrayFPGA Core Array
YYXX
YY
YY YYXX
XX XX
PLB local routingPLB local routing
PLBPLB PLBPLBPLBPLB
PLBPLB PLBPLBPLBPLB
PLBPLB PLBPLBPLBPLB
FPGA Core ArchitectureFPGA Core ArchitectureArranged in 4x4 arrays of PLBsArranged in 4x4 arrays of PLBsOne 32x4One 32x4--bit RAM per 4x4 arraybit RAM per 4x4 array
SingleSingle-- or Dualor Dual--Port operationPort operationSync or Sync or asyncasync operationoperation
Local routing to adjacent PLBsLocal routing to adjacent PLBs4 directs (4 directs (YY))4 diagonals (4 diagonals (XX))
Global routing Global routing –– 5 planes having:5 planes having:Two x8 lines/plane Two x8 lines/plane -- spans 8 PLBsspans 8 PLBsOne x4 line/plane One x4 line/plane -- spans 4 PLBsspans 4 PLBs
connects to/from PLBconnects to/from PLBRepeaters provide buffering and Repeaters provide buffering and interconnections between x8 & x4 linesinterconnections between x8 & x4 lines
Din
Dout
WaddRaddWEOE
5
4
32x432x4RAMRAM
5
4
Vertical Routing PlanesVertical Routing Planes
Hor
izon
tal R
outin
g Pl
anes
Hor
izon
tal R
outin
g Pl
anes
PLB global routingPLB global routing
PLBPLB
1/19/09 Embedded Systems Lecture 4
General FPGA Logic BIST ArchitectureGeneral FPGA Logic BIST ArchitectureColumns or rows of PLBs configured asColumns or rows of PLBs configured as
Test Pattern Generators (TPGs)Test Pattern Generators (TPGs)Counter or LFSR: pseudoCounter or LFSR: pseudo--exhaustive testexhaustive test
Blocks Under Test (BUTs)Blocks Under Test (BUTs)Configured in all modes of operationConfigured in all modes of operation2 test sessions to test all PLBs as BUTs2 test sessions to test all PLBs as BUTs
Output Response Analyzers (ORAs)Output Response Analyzers (ORAs)ComparisonComparison--based monitoring adjacent BUTsbased monitoring adjacent BUTs
Routing resource usage:Routing resource usage:Global routing for TPG signals to BUTsGlobal routing for TPG signals to BUTsLocal routing for BUT outputs to ORAsLocal routing for BUT outputs to ORAs
Architecture forms basis for diagnostic procedureArchitecture forms basis for diagnostic procedureMULTICELLO:MULTICELLO: MultiMultiple Faulty ple Faulty CelCell l LoLocatorcator
=TPG=TPG=BUT=BUT=ORA=ORA
Test Session 1Test Session 1Test Session 2Test Session 2Test Session 2Test Session 2Test Session 2Test Session 2
1/19/09 Embedded Systems Lecture 5
FPSLIC PLB ArchitectureFPSLIC PLB ArchitectureRelatively smallRelatively small
4 data inputs4 data inputsPlus Clock and Set/ResetPlus Clock and Set/Reset
Two 3Two 3--input LUTsinput LUTsOne D flipOne D flip--flopflop
AsyncAsync Set/ResetSet/Reset
Issues for BISTIssues for BISTORAs need 5 LUT inputsORAs need 5 LUT inputs
Compare 2 outputsCompare 2 outputsLatch any mismatchesLatch any mismatches
feedback to LUTsfeedback to LUTsShift out resultsShift out results
2 inputs to LUTs2 inputs to LUTs
Dynamic partial reconfiguration to create shift registerDynamic partial reconfiguration to create shift register
YYLUTLUT
XXLUTLUT
XX
WW
YY
ZZ
1100configurationconfiguration
memory bitmemory bit clockclockset/resetset/reset
LL to global to global routingrouting
YY
XX
to local to local routingrouting
to local to local routingrouting
OUTOUTiiOUTOUTjj ORA dataORA data
ShiftShift
ORAORAdata outdata out
OUTOUTiiOUTOUTjj ORA dataORA data
ShiftShift
ORAORAdata outdata out
1/19/09 Embedded Systems Lecture 6
Logic BISTLogic BISTColumnColumn--based BIST architecturebased BIST architecture
Logic blocks configured as TPGs, Logic blocks configured as TPGs, ORAs, and BUTsORAs, and BUTs
BUTs tested in all modesBUTs tested in all modes4 test configurations4 test configurations
BIST architecture flipped BIST architecture flipped vertically for 2vertically for 2ndnd test sessiontest sessionORA can only observe X from ORA can only observe X from one BUT & Y from other BUTone BUT & Y from other BUT
2 routing schemes needed to observe 2 routing schemes needed to observe both X and Y outputs of all BUTsboth X and Y outputs of all BUTs
= X direct= Y direct
=TPG=BUT=ORA
Routing Routing Scheme 1Scheme 1Routing Routing
Scheme 2Scheme 2
1/19/09 Embedded Systems Lecture 7
Pathological Case for Fault DetectionPathological Case for Fault Detection
X & Y have same position in both X & Y have same position in both TPGs in column 1TPGs in column 1W & Z have same position in both W & Z have same position in both TPGs in column 8TPGs in column 8X & Y have equivalent faultsX & Y have equivalent faultsW & Z have equivalent faultsW & Z have equivalent faultsX & Y cause TPGs in column 1 to X & Y cause TPGs in column 1 to skip patterns that detect W & Zskip patterns that detect W & ZW & Z cause TPGs in column 8 to W & Z cause TPGs in column 8 to skip patterns that detect X & Yskip patterns that detect X & Y
W
Z
X
Y
Rotating architecture by 90Rotating architecture by 90°° will detect these faults!will detect these faults!
W
Z
X
Y
W
Z
X
Y
To escape detection To escape detection allall of the following must be true:of the following must be true:
1/19/09 Embedded Systems Lecture 8
Conventional FPGA BISTConventional FPGA BISTTest Phase 1Test Phase 1 Test Phase 2Test Phase 2
FPGAFPGAResetReset
READREADORAORA
READREADORAORA
FPGAFPGAResetReset
External downloads consume major portion of testing timeExternal downloads consume major portion of testing timeMore test phases means more external storage is requiredMore test phases means more external storage is requiredTo find faulty blocks, ORA results are retrieved after each testTo find faulty blocks, ORA results are retrieved after each test phasephase
download of the next test phase causes FPGA core to be resetdownload of the next test phase causes FPGA core to be reset
External controller is neededExternal controller is neededBIST clocks from external pinBIST clocks from external pinORA results are retrieved outside through external pinORA results are retrieved outside through external pinEmbedded processor is not a main BIST componentEmbedded processor is not a main BIST component
Empty
TPG
ORA
BUT1
BUT2
Fault
1/19/09 Embedded Systems Lecture 9
Embedded Processor Based BISTEmbedded Processor Based BISTUse embedded processor core to Use embedded processor core to
Reconfigure FPGA for BISTReconfigure FPGA for BISTExecute BIST and retrieve BIST resultsExecute BIST and retrieve BIST resultsPerform diagnostic procedurePerform diagnostic procedurePerform fault injection emulationPerform fault injection emulation
Methodical verification of BIST configurationsMethodical verification of BIST configurationsProcessor must access configuration memoryProcessor must access configuration memory
Read access desirable for readRead access desirable for read--modifymodify--writewriteImplemented in Atmel AT94KImplemented in Atmel AT94K
88--bit AVR microcontrollerbit AVR microcontrollerConfiguration memory write access onlyConfiguration memory write access only
Currently implementing in VirtexCurrently implementing in Virtex--4&5 for NSA4&5 for NSAPowerPC (hard), PowerPC (hard), MicroBlazeMicroBlaze & & PicoBlazePicoBlaze (soft)(soft)Configuration memory write and read accessConfiguration memory write and read access
1/19/09 Embedded Systems Lecture 10
AVRAVR--generated FPGA BISTgenerated FPGA BISTTest Phase 1Test Phase 1 Test Phase 2Test Phase 2
No download to FPGA coreNo download to FPGA coreSingle AVR program contains algorithmic reconfiguration routinesSingle AVR program contains algorithmic reconfiguration routines for for configuring FPGA core for each test phaseconfiguring FPGA core for each test phase
TPG and ORA configurations are reusable for next phaseTPG and ORA configurations are reusable for next phaseUntil architecture flips to next test sessionUntil architecture flips to next test sessionAVR reconfigures AVR reconfigures BUTsBUTs for each test phasefor each test phase
ORA results can be retrieved after multiple phases ORA results can be retrieved after multiple phases FF values in ORAs remain throughout subsequent phasesFF values in ORAs remain throughout subsequent phases
ResetResetREADREADORAORA
ResetResetREADREADORAORA
Empty
TPG
ORA
BUT1
BUT2
Fault
1/19/09 Embedded Systems Lecture 11
Dynamic Reconfiguration SequenceDynamic Reconfiguration SequenceClear FPGA coreClear FPGA core
PLBs, repeaters, clk, FFs, freeRAMs, IOBsPLBs, repeaters, clk, FFs, freeRAMs, IOBsNo need for chip resetNo need for chip reset
Configure ORAsConfigure ORAsComparisonComparison--based ORAbased ORAReset ORA FFsReset ORA FFsRouting scheme 1 or 2Routing scheme 1 or 2
Configure BUTsConfigure BUTsChange BUT configurationsChange BUT configurationsWrite FF s from AVR (FF set/reset test)Write FF s from AVR (FF set/reset test)
Cannot be tested by external downloadCannot be tested by external download
Configure TPGsConfigure TPGsTwo 5Two 5--bit countersbit countersRoute TPG signals to BUTsRoute TPG signals to BUTs
Need care when configuring repeatersNeed care when configuring repeatersReset TPG FFsReset TPG FFs
=TPG=BUT=ORA
1/19/09 Embedded Systems Lecture 12
Route BIST clockRoute BIST clockBIST clock driven by AVRBIST clock driven by AVR
Configure AVRConfigure AVR--FPGA interfaces FPGA interfaces that cannot be called from MGLthat cannot be called from MGLRoute from FPGAIOWE to GCK4Route from FPGAIOWE to GCK4Route clock signal to all BUTs, Route clock signal to all BUTs, ORAs and TPGsORAs and TPGs
Run BIST clockRun BIST clockReconfigure ORAs to shift Reconfigure ORAs to shift regreg
Dynamic partial reconfiguration of Dynamic partial reconfiguration of ORAs to shift register without ORAs to shift register without destroying ORA FF contentsdestroying ORA FF contents
Route scan out pathRoute scan out pathshift shift regreg output to 1 of 8output to 1 of 8--bit bus bit bus between AVR and FPGAbetween AVR and FPGA
AVR Data In (ADIN)AVR Data In (ADIN)Retrieve ORA resultsRetrieve ORA results
OnOn--chip diagnosis by AVRchip diagnosis by AVR
Dynamic Reconfiguration SequenceDynamic Reconfiguration Sequence
FIGAROFIGARO
1/19/09 Embedded Systems Lecture 13
97,37097,37024,87924,8794545402402Route scan outRoute scan out
24,79124,7916,3716,3718080282282ORA/shift registerORA/shift register
594,427594,427157,957157,9574,0004,0004,6764,676TotalTotalN/AN/AN/AN/A2,6592,659388388MiscellaneousMiscellaneous
75,85975,85919,33919,3393535306306Retrieve resultsRetrieve results
456456456456663232Generate clocksGenerate clocks
4,9114,9111,9231,9234040234234Route BIST clockRoute BIST clock14,86614,8664,6524,6526006001,4861,486Instantiate TPGInstantiate TPG60,68660,68614,84414,8447070220220Instantiate ORAInstantiate ORA100,360100,36025,82925,829300300834834Instantiate BUTInstantiate BUT215,128215,12859,66459,664150150492492Clear FPGAClear FPGA
K40K40K10K10
Processor Execution Processor Execution CyclesCycles
Number of Lines Number of Lines of C Code of C Code (Approx.)(Approx.)
Program Program MemoryMemory
Size (Bytes)Size (Bytes)
BISTBISTReconfigurationReconfiguration
SubroutinesSubroutines
Largest subroutine (program memory & lines of code) is for confiLargest subroutine (program memory & lines of code) is for configuring guring TPGsTPGsDue to irregular structuresDue to irregular structures
Clearing FPGA and configuring BUTs/ORAs need less program memoryClearing FPGA and configuring BUTs/ORAs need less program memory sizesizeDue to regular structure of BIST architectureDue to regular structure of BIST architecture
Configuration Routines for logic BISTConfiguration Routines for logic BIST
1/19/09 Embedded Systems Lecture 14
OnOn--Chip BIST and DiagnosisChip BIST and DiagnosisAtmel SoCs contain:Atmel SoCs contain:
Program & Data RAMsProgram & Data RAMsProcessor coreProcessor coreFPGA coreFPGA core
Use processor to:Use processor to:Configure FPGA for BISTConfigure FPGA for BISTRun BISTRun BISTGet BIST resultsGet BIST resultsPerform diagnosisPerform diagnosis
Reduces test and diagnosis time by a factor of 36.9Reduces test and diagnosis time by a factor of 36.9Store only one BIST and diagnostic program onStore only one BIST and diagnostic program on--chipchip
1/19/09 Embedded Systems Lecture 15
110000110044000011110055
BB55
11
111100
OO5656 BB66
11
000000
OO1212 BB22
00
000000
OO2323 BB33
00
110011
OO3434
1166
113311220011
OO4545BB44BB11rowrowDiagnosis Based on BIST ResultsDiagnosis Based on BIST Results
Step 1:Step 1: Record ORA resultsRecord ORA resultsStep 2:Step 2: Mark BUTs good Mark BUTs good
between consecutive between consecutive ORAs with 0sORAs with 0s
Step 3:Step 3: Mark BUTs good for Mark BUTs good for every two adjacent 0s every two adjacent 0s followed by empty cellfollowed by empty cell
Step 4:Step 4: Mark BUTs bad for Mark BUTs bad for every consecutive 0 and 1 every consecutive 0 and 1 followed by empty cellfollowed by empty cell
Step 5:Step 5: Inconsistencies mean Inconsistencies mean fault in ORA or in routing fault in ORA or in routing resources from resources from BUTsBUTs
Step 6:Step 6: Unique diagnosis if all Unique diagnosis if all BUTs marked faulty or BUTs marked faulty or faultfault--freefree
1100000011004400000011110055
00BB55
11
111100
OO5656 BB66
11
000000
OO1212
000000BB22
00
000000
OO2323
00
00
BB33
00
110011
OO3434
1166
113311220011
OO4545BB44BB11rowrow
110000000000110044000000000011110055
00BB55
11
111100
OO5656
00BB66
11
000000
OO1212
00
000000BB22
00
000000
OO2323
00
000000BB33
00
110011
OO3434
110066
1100331100002200000011
OO4545BB44BB11rowrow
11110000000000111100114400000000001111110055
11
1100BB55
11
111100
OO5656
00BB66
11
000000
OO1212
00
000000BB22
00
000000
OO2323
00
000000BB33
00
110011
OO3434
11001166
111100331100002200000011
OO4545BB44BB11rowrow
Ambiguities:Ambiguities:Row 2:Row 2: BUT 6 may be faulty or faultBUT 6 may be faulty or fault--freefreeRow 6:Row 6: BUT 6 may be faulty or faultBUT 6 may be faulty or fault--freefreeRow 3:Row 3: BUT 5 and/or BUT 6 is faultyBUT 5 and/or BUT 6 is faultyRow 5:Row 5: BUTs 1 & 2 may be faultBUTs 1 & 2 may be fault--free orfree or
faulty (with equivalent faults)faulty (with equivalent faults)rotate BIST 90rotate BIST 90°° to remove ambiguitiesto remove ambiguities
11
11110000000000111100114400000000001111110055
11
1100BB55
11
111100
OO5656
00BB66
11
000000
OO1212
00
000000BB22
00
000000
OO2323
00
000000BB33
00
110011
OO3434
11001166
111100331100002200000011
OO4545BB44BB11rowrow
Note:Note:Row 4:Row 4: BUTs 1 & 2 have equivalent faultsBUTs 1 & 2 have equivalent faults
=Core Under Test=Core Under Test=ORA PLBs=ORA PLBs =Processor Core=Processor Core
=TPG PLBs=TPG PLBs
1/19/09 Embedded Systems Lecture 16
Implementation of DiagnosticsImplementation of Diagnostics
7207201,3301,330110,000110,0004848××48481801801,3301,33032,00032,0002424××2424
PLBsPLBs
73731,1301,1309,7009,7001212××121220201,1301,1302,4002,40066××66
RAMsRAMs
DataDataMemoryMemory(bytes)(bytes)
ProgramProgramMemoryMemory(bytes)(bytes)
Execution Execution ClockClockCyclesCycles
ArrayArraySizeSize
LogicLogicResourceResource
Diagnostic program is independent of array sizeDiagnostic program is independent of array sizeExtra 200 bytes for ORA/BUT translationExtra 200 bytes for ORA/BUT translation
Data memory requirement and execution time Data memory requirement and execution time are a function of array sizeare a function of array size
OO((NN22) where ) where NN is array size in one dimensionis array size in one dimension
1/19/09 Embedded Systems Lecture 17
BIST and Diagnostic ProgramsBIST and Diagnostic Programs
9309306,5706,5701,506,6601,506,660TotalTotal7207201,3301,330110,000110,000DiagnosticsDiagnostics1381383,3803,380998,560998,560Logic BISTLogic BIST73731,8601,860398,100398,100RAM BISTRAM BIST
DataDataMemoryMemory(bytes)(bytes)
ProgramProgramMemoryMemory(bytes)(bytes)
ExecutionExecutionClockClockCyclesCycles
TestTestFunctionFunction
BIST and diagnostic programs easily fit in AT94KBIST and diagnostic programs easily fit in AT94K≈≈ 20% of 20% of 32Kbyte Program Memory32Kbyte Program Memory≈≈ 20% 20% of 4Kbyte Data RAMof 4Kbyte Data RAM
Same diagnostic program used for PLBs & RAMsSame diagnostic program used for PLBs & RAMsPLB diagnosis dictates memory requirementsPLB diagnosis dictates memory requirements
1/19/09 Embedded Systems Lecture 18
local routing resources
ParC1C0 ORA ORA
Global ×4 lines
Routing BISTRouting BIST
Modified parityModified parity--based routing BISTbased routing BIST33--bit TPG = 2bit TPG = 2--bit counter + paritybit counter + parity
Drive all five x4 global busesDrive all five x4 global buses
Detects allDetects allstuckstuck--at faults, bridging faults and opens at faults, bridging faults and opens in wire segments in wire segments stuckstuck--on/off faults in repeaterson/off faults in repeaters
ParC1C0 ORA ORA
repe
ater
s
repe
ater
s
Count-up/even parity Count-down/odd parity
110000001111001100110011000011111100111111000000
PoPoC1C1C0C0PePeC1C1C0C0CountCount--downdownCountCount--upup
1/19/09 Embedded Systems Lecture 19
Configuration Routines for Routing BISTConfiguration Routines for Routing BIST
Routing BIST generation and Routing BIST generation and reconfiguration program are similar to logic reconfiguration program are similar to logic BIST shown previouslyBIST shown previouslySingle AVR program generates all 56 Single AVR program generates all 56 routing BIST configurationsrouting BIST configurations
8,578,7188,578,7181,1551,1557,8547,8545656TotalTotal6,671,9736,671,9736366364,4124,4124040RepeatersRepeaters1,906,7451,906,7455195193,4423,4421616CrossCross--pointspoints
Processor Processor Cycles K40Cycles K40
Lines of Lines of C CodeC Code
MemoryMemory(bytes)(bytes)
# # ConfigsConfigs
BISTBISTSubroutineSubroutine
1/19/09 Embedded Systems Lecture 20
Results: Results: SpeedSpeed--upup
182.4182.40.110 sec0.110 sec20.064 sec20.064 secDownloadDownload0.0750.0750.343 sec0.343 sec0.026 sec0.026 secExecutionExecution
76.076.00.101 sec0.101 sec7.680 sec7.680 secDownloadDownload0.20.20.085 sec0.085 sec0.016 sec0.016 secExecutionExecution
43.543.50.639 sec0.639 sec27.786 sec27.786 secTotal Test TimeTotal Test Time20.090 sec20.090 sec
7.696 sec7.696 sec
DownloadDownload
0.453 sec0.453 sec
0.186 sec0.186 sec
ProcessorProcessor
44.344.3Total timeTotal timeRouting BISTRouting BIST
41.441.4Total timeTotal timeLogic BISTLogic BIST
SpeedSpeed--upupFunctionFunctionResourceResource
Configuration download time dominates total test Configuration download time dominates total test time for conventional download approachtime for conventional download approachLonger execution time on processorLonger execution time on processor--generated generated BIST approach than download approachBIST approach than download approach
1/19/09 Embedded Systems Lecture 21
Results: Results: MemoryMemory ReductionReduction
Download approach needs 60 configuration Download approach needs 60 configuration downloads to the chipdownloads to the chipProcessorProcessor--generated BIST approach requires generated BIST approach requires only one (relatively small) download to the only one (relatively small) download to the program memory of AVR processorprogram memory of AVR processor
1581581122 Kbyte22 Kbyte606058 Kbyte58 KbyteCombinedCombined1791791114 Kbyte14 Kbyte444457 Kbyte57 KbyteRoutingRouting80801112 Kbyte12 Kbyte161660 Kbyte60 KbyteLogicLogic
# # FilesFilesFile SizeFile Size# #
FilesFilesAverageAverageFile SizeFile Size
Memory Memory Reduction Reduction
FactorFactor
ProcessorProcessorDownloadDownloadResourceResource
TestedTested
1/19/09 Embedded Systems Lecture 22
110111010000100010110101BIST BIST configconfig
FPGAFPGA
Physical Fault InjectionPhysical Fault InjectionFaulty FPGA are difficult to findFaulty FPGA are difficult to find
1 ORCA with faulty PLB & 2 1 ORCA with faulty PLB & 2 ORCAsORCAs with faulty routingwith faulty routingPhysical fault insertionPhysical fault insertion
Etch package and Etch package and ““zapzap”” with laserwith laserFault Injection EmulationFault Injection Emulation
Modify configuration bitsModify configuration bitsPrior to download, orPrior to download, orReadRead--modifymodify--write of configuration memorywrite of configuration memory
External or internal embedded processor External or internal embedded processor Fault Emulator can create single & multiple faults in:Fault Emulator can create single & multiple faults in:
PLBsPLBs: : LUTsLUTs, flip, flip--flops, etc.flops, etc.Interconnect: Interconnect: PIPsPIPs stuckstuck--on & stuckon & stuck--offoff
011001101110011001000000StuckStuck--at valuesat values
000010000100000010000100Fault maskFault mask
110111011100100010000101Download fileDownload file 1101 1101
1100100100000101faultsfaults
1/19/09 Embedded Systems Lecture 23
Automated Fault Injection AnalysisAutomated Fault Injection AnalysisFault injection emulation used for debugging, analysis & Fault injection emulation used for debugging, analysis & verification of BIST configurations & diagnosisverification of BIST configurations & diagnosis
Embedded processor based fault injection gives faster and more Embedded processor based fault injection gives faster and more thorough analysisthorough analysis
14 seconds13 minutes84Free RAMFree RAM3 min 40 sec3 hrs 36 min13065Horizontal RepeatersHorizontal Repeaters4 min 1 sec3 hrs 55 min14271Vertical RepeatersVertical Repeaters
4 min 34 sec4 hrs 29 min16281PLB with flipPLB with flip--flopsflops
ProcessorProcessorRun TimeRun Time
DownloadDownloadRun TimeRun Time
TotalTotalFaultsFaults
ConfigConfigBitsBits
ProgrammableProgrammableResourceResource
0
1
2
3
4
5
6
7
X3Y3Z
0B0S
0
X3Y3Z
0B2S
0
X3Y3Z
0B4S
0
X3Y3Z
0B6S
0
X3Y3Z
1B1S
0
X3Y3Z
1B3S
0
X3Y3Z
1B5S
0
X3Y3Z
2B1S
0
X3Y3Z
2B3S
0
X3Y3Z
2B5S
0
X3Y3Z
3B0S
0
X3Y3Z
3B2S
0
X3Y3Z
3B4S
0
X3Y3Z
4B0S
0
X3Y3Z
4B2S
0
X3Y3Z
4B4S
0
X3Y3Z
4B6S
0
X3Y3Z
5B1S
0
X3Y3Z
5B3S
0
X3Y3Z
5B5S
0
X3Y3Z
6B1S
0
X3Y3Z
6B3S
0
X3Y3Z
6B5S
0
X3Y3Z
7B0S
0
X3Y3Z
7B2S
0
X3Y3Z
7B4S
0
X3Y3Z
8B0S
0
X3Y3Z
8B2S
0
X3Y3Z
8B4S
0
X3Y3Z
8B6S
0
X3Y3Z
9B1S
0
X3Y3Z
9B3S
0
X3Y3Z
9B5S
0
Horizontal Ebus Repeater Faults
# C
onfig
s D
etec
ting
Faul
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
X3Y3
Z0B0
S0
X3Y3
Z0B2
S0
X3Y3
Z0B4
S0
X3Y3
Z0B6
S0
X3Y3
Z1B1
S0
X3Y3
Z1B3
S0
X3Y3
Z1B5
S0
X3Y3
Z2B1
S0
X3Y3
Z2B3
S0
X3Y3
Z2B5
S0
X3Y3
Z3B0
S0
X3Y3
Z3B2
S0
X3Y3
Z3B4
S0
X3Y3
Z4B0
S0
X3Y3
Z4B2
S0
X3Y3
Z4B4
S0
X3Y3
Z4B6
S0
X3Y3
Z5B1
S0
X3Y3
Z5B3
S0
X3Y3
Z5B5
S0
X3Y3
Z6B1
S0
X3Y3
Z6B3
S0
X3Y3
Z6B5
S0
X3Y3
Z7B0
S0
X3Y3
Z7B2
S0
X3Y3
Z7B4
S0
X3Y3
Z8B0
S0
X3Y3
Z8B2
S0
X3Y3
Z8B4
S0
X3Y3
Z8B6
S0
X3Y3
Z9B1
S0
X3Y3
Z9B3
S0
X3Y3
Z9B5
S0
Horizontal Ebus Repeater Faults
# Con
figs
Det
ectin
g Fa
ult
Read-modify-write of config memory bits makes analysis more efficient!
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