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System Design with ForSyDe
Ingo Sander
Royal Institute of TechnologyStockholm, Sweden
ingo@kth.se
October 9, 2009
Ingo Sander (KTH) ForSyDe October 9, 2009 1 / 83
Outline1 Background
2 Haskell
3 ForSyDe Modeling Concepts
4 Design Transformation
5 Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
6 Modeling of Adaptive Systems
7 Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
8 The SYSMODEL Project
9 Conclusion and Future Work
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Background
Observations• The design productivity gap is still increasing• Share of the verication costs of the total design costs is
increasing• Industry aims for more abstract design languages, but
• SystemC and Verilog are further development of old languageparadigms
• Simulation is still the predominant verication technique• Difficult to apply formal methods since today’s design languages
do not offer a sufficient formal basis
Formal and systematic approach is needed!
Ingo Sander (KTH) ForSyDe October 9, 2009 4 / 83Background
What is ForSyDe?ForSyDe (Formal System Design) is a design methodology forsystems-on-chip that has been developed with the followingobjectives.
• System design must start at a high level of abstraction
• Designer shall focus on functionality• Low-level implementation details shall not be an issue at this
stage• Design methodology must give a solid base for the incorporation
of formal methods• Verication must be a rst class citizen from the start
• Abstraction gap between specication and implementation mustbe bridged by formal renement technique
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Background
Designing at Different Levels of Abstraction
Specication Model
Design Space
Abstraction Level
Implementation
Renement Steps
A b s t r a c t i o n
G a p
• ForSyDe allows to describe heterogeneous models at differentabstraction levels.
• The idea is to ’map’ a rened ForSyDe model to animplementation language such as VHDL or C.
Ingo Sander (KTH) ForSyDe October 9, 2009 6 / 83Background
ForSyDe Design Flow
SpecicationModel
TransformationalDesign
Renement
ImplementationModel
CommunicationImplementation
HardwareImplementation
SoftwareImplementation
Verication TransformationLibrary
MappingImplementation Architecture
Model
FunctionalDomain
ImplementationDomain
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Background
Current Status of ForSyDe• ForSyDe is implemented as domain specic language in Haskell.• Several libraries for different models of computation exist and
can be simulated as integrated model.• ForSyDe processes are formally dened.• ForSyDe supports modeling at different levels of abstraction.• There exists a back-end for hardware design and synthesis
(VHDL).• High-level and synthesizable models can be co-simulated giving
access to powerful test benches.
Ingo Sander (KTH) ForSyDe October 9, 2009 8 / 83Haskell
The Functional Language Haskell• A functional program is a function that receives the program’s
input as argument and delivers the program’s output as result.• Haskell is apure and lazy functional language
Pure Haskell is free from side-effects, i.e. there is no
global stateLazy Haskell is a lazy languages, which means that thearguments will rst be evaluated, when they areneeded
• A functional program is a function that consists of otherfunctions.
• A functional program containsimplicit parallelism.
r (x , y ) = h(f (x ), g ( y ))
Here there are no data dependencies betweenf (x ) and g ( y ).Thus they can be executed in any order or in parallel.
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Haskell
Length of a ListThe length of the list can be dened recursively.
There are two cases:
1 The list is empty2 The list has at least one element
This can be directly modelled in Haskell:len [] = 0 -- (1) List is emptylen ( hd :tl ) = 1 + len tl -- (2) List is non - emp ty
Execution in the Haskell interpreter, hereghci , gives*Haskel l In t ro > l en [7 ,2 ,5 ,4 ,9 ,3 ,2 ]7*Haskel l In t ro > l en [ ’ a ’ , ’b ’ , ’c ’ ]3
Ingo Sander (KTH) ForSyDe October 9, 2009 11 / 83Haskell
Program ExecutionThe programlen [] = 0 -- (1) List is emptylen ( hd :tl ) = 1 + len tl -- (2) List is non - emp ty
is executed in the following steps:l en [ ’ a ’, ’ b ’, ’ c ’]
= len ( ’a ’ : [ ’b ’, ’c ’]) -- P att er n 2 m at ch es= 1 + len [ ’b ’, ’c ’]= 1 + len ( ’b ’: [ ’c ’]) -- P att er n 2 m at ch es= 2 + l e n [ ’ c ’ ]= 2 + len ( ’c ’ : []) -- P att er n 2 m at ch es
= 3 + len [] -- P att er n 1 m at ch es= 3 + 0= 3
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Haskell
QuicksortComplex algorithms can be formulated very concise and clearly!quicksor t [] = []q ui c ks or t ( x : xs )
= quicksort [y | y <- xs , y <= x ]++ [ x]++ quicksort [y | y <- xs , y > x ]
*Haskel l In t ro > qu icksort [7 ,2 ,5 ,4 ,9 ,3 ,2 ][2 ,2 ,3 ,4 ,5 ,7 ,9]
Ingo Sander (KTH) ForSyDe October 9, 2009 13 / 83Haskell
Higher-order function: mapA higher-order function is a function that takes functions asargument and/or produces a function as output. map f [] = [] -- em pt y l is t m a p f ( x : x s ) = f x : m a p f x s -- all oth er l i sts
The higher-order function map can be used with different data types.* Haskel l Int ro > in t l i st[7 ,2 ,5 ,4 ,9 ,3 ,2]* H a sk el lI nt ro > m ap e ve n i nt li st[Fal se ,True ,Fal se ,True ,Fal se ,Fal se ,True ]* H a sk el lI nt ro > m ap ( *3 ) i nt li st
[21 ,6 ,15 ,12 ,27 ,9 ,6]
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Haskell
Haskell is strong-typed!
map f [] = [] -- em pt y l is t m a p f ( x : x s ) = f x : m a p f x s -- all oth er l i sts
The Haskell type system caninfer the data type of a function.*Haskel l In t ro > : i map map :: ( a -> b) -> [ a ] -> [b ]
This means that the function map takes a function that takes twoarguments
1 a function that takes a data type a and returns a data type b
2 a list of data type aThe function map returns a list of data type b.
Ingo Sander (KTH) ForSyDe October 9, 2009 15 / 83Haskell
Wrong types are rejected
map f [] = [] -- em pt y l is t m a p f ( x : x s ) = f x : m a p f x s -- all oth er l i sts
Since Haskell expects a list as its second argumentmap even ’c’ isrejected!* H a sk el lI nt ro > m ap e ve n ’c ’
<interactive >:1:9:Cou ldn ’ t m at ch e xp ec te d t yp e ‘[ a ]’ a ga in sti nf er re d t yp e ‘ Char ’In the s eco nd a rg um en t of ‘ map ’ , na mel y ’c ’
In the e xp re ss io n : map even ’c ’In the def ini t ion of ‘ it ’ : it = map even ’c ’
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Haskell
Function CompositionThe operator ◦ allows founction composition.Function Composition
(f ◦ g )x = f (g (x ))In Haskell ’.’ is used instead for◦ .inc x = x + 1n ew Fu nc ti on = even . inc
* H a sk el lI nt ro > m ap e ve n [1 , 2 , 3 , 4][Fa l se ,True ,Fa l se ,True ]*Haskel l In t ro > map newFunc tion [1 ,2 ,3 ,4][True ,Fa l se ,True ,Fa l se ]
Ingo Sander (KTH) ForSyDe October 9, 2009 17 / 83Haskell
Function Application OperatorThe operator $ is used for function application.
Function Application Operator
($) :: (a -> b ) -> a -> b
f $ x = f x
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ForSyDe Modeling Concepts
ForSyDe System Model• A system is modelled as hierarchical concurrent process model• Processes of different models of computation communicate via
domain interfaces• Supported MoCs: Synchronous, Untimed (Synchronous Data
Flow), Continuous Time
AB
AB
P 1
P 3
P 2 P 4
P 5
MoC B
MoC A
Ingo Sander (KTH) ForSyDe October 9, 2009 20 / 83ForSyDe Modeling Concepts
ForSyDe ProcessA process takes m input signals as argument and producesn outputsignals. ForSyDe processes are deterministic.
• A process is always designed by means of aprocess constructor• The process constructor denes the communication interface of
the process• The process constructor takes side-effect freefunctions and
variables as arguments and returns a process
f g
v
mooreSY
=
Process
v
Variables
+
Functions
+
Process Constructor
f g
mooreSY
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ForSyDe Modeling Concepts
Process Constructor Types
There are three main categories of processconstructorCombinational Process has no internal state
Delay Process delays inputSequential Processes have an internal state
and contain a delay process
These categories exist in all models of com-putation
f g
v
mooreSY
vdelaySY
f
mapSY
Ingo Sander (KTH) ForSyDe October 9, 2009 22 / 83ForSyDe Modeling Concepts
Synchronous Process
4
2
5
⊥
6
3
7
6
Communication and Synchronization
4
3
5
⊥
6
4
7
7inc⊥
mapSY
ProcessEventTag
Value ”Absent” Value
Computation
Signal
Synchronous AssumptionThe outputs of a system (process) are synchronized with the inputs. The reactionof the system is instantaneous and takes no observable time!
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ForSyDe Modeling Concepts
Process Constructor - BenetsThe concept of process constructor
• separates communication from computation• process constructor: communication and interface• function: computation
• forces the designer to develop a structured formal model thatallows for formal analysis
• transformational renement• implementation mapping• formal verication
Ingo Sander (KTH) ForSyDe October 9, 2009 24 / 83Design Transformation
Semantic-Preserving Design Transformations
P 1 mapSY (f ) P 2mapSY (g )
Subsystem 2Subsystem 1 PN
T (PN , MapMerge )
P 1 P 2
PN
mapSY (f ◦ g )
Semantic-Preserving TransformationmapSY (+2) ◦ mapSY (+5) can be transformed into mapSY (+7)Possible in the synchronous model, since computation takes no time(not even a delta delay)!
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Design Transformation
Non-Semantic-Preserving Design Transformations
r
i
(Buffer = ∞ )FIFO i
o
FIFO (Buffer = n )r
o
RestrictFIFOBuffer (n)
• Also non-semantic preserving design transformations are neededin order to arrive at an efficient implementation
• requires verication, since semantics are changed
Concepts and verication method have been developed inside theForSyDe project
Ingo Sander (KTH) ForSyDe October 9, 2009 27 / 83Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modelling Heterogeneous SystemsThe Shallow Embedded Implementation of ForSyDe
ForSyDe has initially been mainly developed for the modellingpurpose.
• Signals have been modelled as streams of data.data Signal a = NullS | Signal a
• Pros• Rapid modelling of heterogeneous systems• No need for advanced or non-standard features of Haskell• Easy to include new models of computation
• Cons• Restriction to simulation only, since there is no access to the
abstract syntax tree
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Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modeling combinational processes
mapSY (f )
i o
The process constructor mapSY
mapSY :: (a -> b ) -> Signal a -> Signal b map SY _ N ull S = Nu ll S mapSY f (x : - xs ) = f x : - ( mapSY f xs )
Exampleinverter = mapSY not
* H a sk el lI nt ro > i nv e rt er ( s i gn al [ True , F al se ] ){Fa l se ,True}
Ingo Sander (KTH) ForSyDe October 9, 2009 30 / 83Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modeling combinational processes
zipWithSY m(f )
o i m
i 1
The process constructor zipWithSYzipWithSY :: (a -> b -> c ) -> Signal a
-> Signal b -> Signal czipWithS Y _ NullS _ = NullSzipWithS Y _ _ NullS = NullSz ip Wi th SY f ( x :- xs ) ( y :- ys )
= f x y : - ( zipWithSY f xs ys )
Exampleadder = zipWithSY (+)
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Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modeling sequential processes
delaySY k (s 0)
i o
The process constructor delaySY
delaySY :: a -> Signal a -> Signal adelaySY e es = e :- es
Exampleregister = delaySY 0
Ingo Sander (KTH) ForSyDe October 9, 2009 32 / 83Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modeling sequential processes
o
scanldSY m (f , s 0)
(s 0)s delaySY 1
(f )zipWithSY m +1
i 1i m
The process constructor scanldSY
scanldSY :: ( a -> b -> a) -> a-> Signal b -> Signal a
scanldSY f mem xs = s ’where s ’ = delaySY mem ( z ipWit hSY f s ’ xs )
Examplecounter = scanldSY (+) 0
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Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Modeling sequential processes
o i 1
i m (g )
mooreSY m (f , g , s 0)
(f , s 0)
s scanldSY m mapSY
The process constructor mooreSY
mooreSY :: (a -> b -> a ) -> (a -> c )-> a -> Signal b -> Signal c
mooreSY nex tS ta te ou tpu t in it i al= m ap SY o ut pu t
. ( s c an ld SY n ex tS ta te i ni ti al )
Ingo Sander (KTH) ForSyDe October 9, 2009 34 / 83Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Tutorial Example
ControllerEncr/DecrAdaptive
D2AConverter
adaptGain
12
3
4
5 6 7
decode ASKReceiver
A2DConverter
WaveSine
generate
multCT
modulate ASK
serializeBitVector
encode ASK
SenderTransceiver
PowerController
Adaptive
Noiseadd
GeneratorNoise
Gaussian
Transceiver System
NoiseNoisyASK
ASKreceivedBitVector
encodedBitVector
ControlInputGainParameter
Controller
Key
BitVector
IntegerTo
IntegerTo
BitVector
decodedBitVector
IntegerInput
IntegerOutput
BitVector
Continuous Time Untimed (SDF) Synchronous
Decoder
Encoder
Bit ErrorsDetect
detectBits packBits
Bit Error Rate
Encryption/Decryption
Key
in Hardware
0.0001Attenuation
Implementation
(Simplied DES)
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Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Simulating a Heterogeneous System
1 Synchronous Input Signal
in = {0,1,2,3,4,5 }
4 Gaussian Noise
-0.0004
-0.0003
-0.0002
-0.0001
0
0.0001
0.0002
0.0003
0.0004
0.0005
0 0.001 0.002 0.003 0.004 0.005 0.006
seconds
Noise
7 Synchronous Output Signal
out = {0,1,10,3,4,5 }
3 Transceiver Output
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 0.001 0.002 0.003 0.004 0.005 0.006
seconds
ASK
5 Noisy Transceiver Input
-0.0008
-0.0006
-0.0004
-0.0002
0
0.0002
0.0004
0.0006
0.0008
0.001
0 0.001 0.002 0.003 0.004 0.005 0.006seconds
NoisyASK
Ingo Sander (KTH) ForSyDe October 9, 2009 36 / 83Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Simplied DES Algorithm• Both the encryption and decryption units are implemented with
the simplied DES algorithm• The simplied DES algorithm has similar properties and
structure as DES, but is developed for educational purposes.
Simplied DES Algorithmciphertext = ( IP − 1 ◦ f K 2 ◦ SW ◦ f K 1 ◦ IP ) plaintext
plaintext = ( IP − 1 ◦ f K 1 ◦ SW ◦ f K 2 ◦ IP ) ciphertext
IP initial permutationIP − 1 inverse of initial permutation
SW switches halves of dataf K i permutation and substitution of data using the subkey i .
Two 8-bit subkeys are generated from an initial 10-bitkey.
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Shallow Embedded ForSyDe - Modelling Heterogeneous Systems
Simplied DES - The f K FunctionalityProcess networks aremodelled as set of equations.
S0 S1
XOR
P4
Expand/Permute
XOR
IP
K 1
8
4 4
8
8
22
4
4
SW
F
44
f K
connected to f K 2
plaintext
subkey
...import Data.Param.FSVecimport qualified Data.Param.FSVec as FS
f :: FSVec D8 Bit -> FSVec D4 Bit -> FSVec D4 Bitf subkey nibble
= p4 (out_S0 FS.++ out_S1)where out_S0 = s0matrix out_xor
out_S1 = s1matrix out_xorout_xor = zipxor subkey out_epout_ep = exp_perm nibble
f_k :: FSVec D8 Bit -> FSVec D8 Bit-> FSVec D8 Bit
f_k subkey input= outLeft FS.++ outRight
whereoutLeft = FS.zipWith xor inpLeft fOutoutRight = inpRightfOut = f subkey inpRightinpLeft = FS.take d4 inputinpRight = FS.drop d4 input
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Fixed-Sized VectorsFor hardware design vectors of xed size are of crucial importance forboth modelling and an efficient design implementation. ForSyDeoffers the data type FSVec 1 that allows to specify vectors of constantsize, which can also be synthesized to hardware.
...import Data.Param.FSVecimport qualified Data.Param.FSVec as FS
splitBlock :: FSVec D8 Bit -> (FSVec D4 Bit, FSVec D4 Bit)splitBlock block = (FS.take d4 block, FS.drop d4 block)
Fixed Size Vectors are heavily used during the tutorial example.
1The implementation was done by Alfonso AcostaIngo Sander (KTH) ForSyDe October 9, 2009 39 / 83
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Modeling of Adaptive Systems
Adaptive Processes• Basic Idea
• Functions can be used as signal values• Adaptive process executes function that is provided at time
instance for execution
ProcessAdaptive
s a = < 2, 4, 6, 8, · · · >
s b = < 1, 2, 3, 4, · · · >s o = < 3, 8, 9, 32, · · · >
s f = < (+) , (x ), (+) , (x ), · · · >
P F
Functionality is provided from the outside and ”loaded” into the adap-tive process.
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Adaptivity in HaskellSince functions are rst-class citizens, adaptivity can be easilyimplemented in Haskell.Implementaton of Function AdaptivityfuncAdaptSY = zipWithSY ($)
funcAdapt2SY = zipWith3SY ($)
s_f = signal ([(+),(*),(+),(*)])
* Haskel l Int ro > s_a{2,4 ,6 ,8}* Haskel l Int ro > s_b
{1,2 ,3 ,4}* H a sk el lI nt ro > f u nc A da p t2 S Y s _f s _a s _b{3,8 ,9 ,32}
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Modeling of Adaptive Systems
An illustrative example
EncodingFunction
Signal Encoded Signal Decoded Signal
generateEncoder
Encoder Decoder
generateDecoder
Key
DecodingFunction< f (x ) = x + 1 , f (x ) = x + 2 , · · · >
< 2, 4, · · · > < 2, 4, · · · >< 3, 6, · · · >
< 1, 2, · · · >
< f (x ) = x − 1, f (x ) = x − 2, · · · >
Adaptive Processes
Ingo Sander (KTH) ForSyDe October 9, 2009 43 / 83Modeling of Adaptive Systems
Different levels of adaptivityAdaptive processes can be of different complexity
Parameter Adaptive process contains a parameter that can bechanged from the outside
Mode Adaptive process contains several functions that can beselected from the outside
Function Adaptive process changes its functionality depending onthe function that is supplied from the outside
Interface Adaptive process changes its functionality and interfacedepending on the process that is supplied from theoutside
• Number of inputs and outputs can change• MoC can change• Functionality can change
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Modeling of Adaptive Systems
Parameter AdaptivityFunctionality is part of the process, but is modied by a parameterthat is provided from the outside.
s o = < 3, 8, 10, 3, · · · >
Parameter Adaptive Process
P P s a = < 3, 4, 5, 3, · · · >
s p = < 1, 2, 2, 1, · · · >
Functionality of P P
s o (i ) = s a (i ) · s p (i )
Ingo Sander (KTH) ForSyDe October 9, 2009 45 / 83Modeling of Adaptive Systems
Mode AdaptivityFunctionality is part of process and controlled from the outside
s a = < 2, 4, 6, 8, · · · >
s b = < 1, 2, 3, 4, · · · >s o = < 3, 8, 9, 32, · · · >
Mode Adaptive Process
P M
s m = < ADD , MUL, ADD , MUL, · · · >
Functionality of P M
s o (i ) = s a (i ) + s b (i ) | s m (i ) = ADD s a (i ) · s b (i ) | s m (i ) = MUL
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Modeling of Adaptive Systems
Function AdaptivityFunctionality is provided from the outside and ”loaded” into theadaptive process.
s a = < 2, 4, 6, 8, · · · >
s b = < 1, 2, 3, 4, · · · >s o = < 3, 8, 9, 32, · · · >
Function Adaptive Process
P F
s f = < (+) , (x ), (+) , (x ), · · · >
Functionality of P F
s o (i ) = s f (i )(s a (i ), s b (i ))
Ingo Sander (KTH) ForSyDe October 9, 2009 47 / 83Modeling of Adaptive Systems
Interface AdaptivityAdaptive process changes its functionality and interface depending onthe ”loaded” process
i 1
i m
o 1
o n
Interface Adaptive Process
s i = < P SY , 1(i 1 , i 2), P SDF , 1(i m ), P SY , 2(i 2), · · · >
i 2 o 2P I
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Modeling of Adaptive Systems
Interface AdaptivityAdaptive process changes its functionality and interface depending onthe ”loaded” process
i 1
i m
o 1
o n
Interface Adaptive Process
i 2 o 2
s i = < P SDF , 1(i m ), P SY , 2(i 2), · · · >
P SY , 1
Ingo Sander (KTH) ForSyDe October 9, 2009 49 / 83Modeling of Adaptive Systems
Interface AdaptivityAdaptive process changes its functionality and interface depending onthe ”loaded” process
i 1
i m
o 1
o n
Interface Adaptive Process
i 2 o 2
s i = < P SY , 2(i 2), · · · >
P SDF , 1
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Modeling of Adaptive Systems
Interface Adaptivity
i 1
i m
o 1
o n
Interface Adaptive Process
s i = < P SY , 1(i 1 , i 2), P SDF , 1(i m ), P SY , 2(i 2), · · · >
i 2 o 2
P I
• Interface Adaptive Processes are inherently complex• many open questions!
• However, they have their counterpart in the implementationdomain
• Any function can be loaded on the y onto a partiallyrecongurable FPGA (e.g. Xilinx Virtex IV-family)
Ingo Sander (KTH) ForSyDe October 9, 2009 51 / 83Modeling of Adaptive Systems
Partially recongurable FPGAs
Configuration 1
Configuration 2
Configuration n
Non−reconfigurable Area
Configuration
Reconfigurable Area Co nfiguration Memory C o n g u r a t i o n
C o n t r o l l e r
Slot
Just-In-Time Adaptivity• Adaptive processes can be implemented using a run-time
recongurable FPGA• Conguration (process/function) is loaded from conguration
memory into conguration slot on FPGA• Non-recongurable area performs its function even during
reconguration!Ingo Sander (KTH) ForSyDe October 9, 2009 52 / 83
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Modeling of Adaptive Systems
Design Renement• An efficient design ow starts at high abstraction level
• functionality shall be analyzed• implementation details are not necessary at this stage
EncodingFunction
Signal Encoded Signal Decoded Signal
generateEncoder
Encoder Decoder
generateDecoder
Key
DecodingFunction< f (x ) = x + 1 , f (x ) = x + 2 , · · · >
< 2, 4, · · · > < 2, 4, · · · >< 3, 6, · · · >
< 1, 2, · · · >
< f (x ) = x − 1, f (x ) = x − 2, · · · >
Adaptive Processes
Adaptation is assumed to be instantaneous
Ingo Sander (KTH) ForSyDe October 9, 2009 53 / 83Modeling of Adaptive Systems
Design Renement• During the design process implementation details are added
• Adaptation is no longer instantaneous ⇒ Buffers have to beintroduced
EncodingFunction
Buffer
DecodingFunction
BufferSignal DecodedEnc
Signal
Encoder Decoder
generateEncoder
generateDecoder
congEncoder
congDecoder
SignalDecoderAdaptive
EncoderAdaptive
Introduction of Buffers
Key
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Modeling of Adaptive Systems
Design Renement• Design process for adaptive systems imposes hard requirements
on correctness• System must work correctly during course of adaptation, which
can comprise several stages• Performance data is required Difficult to ensure correctness byad hoc renement
Formal approach is needed!
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Deep-Embedded ForSyDeIn order to allow to give structural information to a ForSyDe model,recently a deep-embedded version of ForSyDe has been developed.The main objectives have been
• to allow for efficient hardware synthesis of synchronous ForSyDe
models• to be able to simulate synchronous ForSyDe models• to be able to integrate further back-ends for analysis and
transformation• to be able to combine and co-simulate shallow-embedded and
deep-embedded ForSyDe models
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
Why an Embedded Compiler?• Feasibility. Does require less time than development of
traditional compiler• Saves unnecessary effort. The goal is to translate the system
structure, not any arbitrary Haskell program• Previous success. Successful embedded compiler has been
developed for Lava• Maintainable. The compiler is packed with ForSyDe’s Library• Independent of third-party tools. No risk of getting outdated
due to external design changes
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Process Function• ForSyDe uses Template Haskell to be able to extract the
Abstract Syntax Tree.• Each function that is argument to a process constructor needs to
be declared using Template Haskell.p4Fun :: ProcFun (FSVec D2 Bit -> FSVec D2 Bit -> FSVec D4 Bit)p4Fun = $(newProcFun
[d| p4 :: FSVec D2 Bit -> FSVec D2 Bit -> FSVec D4 Bitp4 outS0 outS1 = outS0!d1 +> outS1!d1 +>
outS1!d0 +> outS0!d0 +> empty |])
Use of Template Haskell
• The declaration [d| ... |] is used to give a denition of a functionso that its abstract syntax tree is accessible at compile-time.
• $(..) means ”evaluate at compile time”. Here a newProcFun usingthe declaration in [d| ... |] is evaluated at compile-time andgives access to the abstract syntax tree.
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
System Function and DenitionProcesses are created using process constructors and process functions asarguments. An additional argument is the process identier that can beused by the compiler back-end.
p4Proc :: Signal (FSVec D2 Bit) -> Signal (FSVec D2 Bit)-> Signal (FSVec D4 Bit)
p4Proc = zipWithSY "p4Proc" p4Fun
A system function describes a system. Additional parameters are systemidentier and input and output ports.
p4Sys :: SysDef (Signal (FSVec D2 Bit) -> Signal (FSVec D2 Bit)
-> Signal (FSVec D4 Bit))p4Sys = newSysDef p4Proc "p4" ["S0", "S1"] ["out"]
Ingo Sander (KTH) ForSyDe October 9, 2009 60 / 83Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
Composing a Larger SystemSystems can be used as components to create larger systems.
fProc :: Signal (FSVec D4 Bit) -> Signal (FSVec D8 Bit)-> Signal (FSVec D4 Bit)
fProc nibble subkey = outwhere
out = (instantiate "p4Sys" p4Sys) s0 s1s0 = (instantiate "outputS0Sys" outputS0Sys) rS0 cS0s1 = (instantiate "outputS1Sys" outputS1Sys) rS1 cS1rS0 = (instantiate "rowS0" rowS0Sys) xorsubkeyrS1 = (instantiate "rowS1" rowS1Sys) xorsubkeycS0 = (instantiate "colS0" colS0Sys) xorsubkeycS1 = (instantiate "colS1" colS1Sys) xorsubkeyxorsubkey = (instantiate "xorsubkeySys" xorSubkeySys) subkey exppermexpperm = (instantiate "expPermSys" expPermSys) nibble
fSys :: SysDef (Signal (FSVec D4 Bit) -> Signal (FSVec D8 Bit)-> Signal (FSVec D4 Bit))
fSys = newSysDef fProc "fSys" ["nibble", "subkey"] ["out"]
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
SimulationDeep-embedded models can be simulated using the command simulate .The system process encryptSys encrypts a plain text and decryptSys isthe corresponding decryption.
key1 = [H +> L +> H +> L +> L +> L +> L +> L +> H +> L +> empty]subkey_1 = fst $ simulate subkeysSys key1subkey_2 = snd $ simulate subkeysSys key1enc = simulate encryptSys subkey_1 subkey_2 plaindec = simulate decryptSys subkey_1 subkey_2 enc
> plain[<L,L,H,L,L,H,L,L>]> enc[<H,H,H,L,L,L,H,H>]> dec[<L,L,H,L,L,H,L,L>]
Deep-embedded and shallow-embedded models can be co-simulatedin the ’shallow-embedded world’.combSim shallowSig = (shallowProcess . signal . simulate DeepSys
. fromSignal) shallowSig
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Graphical OutputIt is possible to obtain a graphical representation using ForSyDe’s GraphMLback-end.
> writeGraphMLOps defaultGraphMLOps{yFilesMarkup=True} fSys
The diagram can then be viewed using the editor yEd from yWorks:
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
Hardware Synthesis - ProcessesThe main ideas for hardware synthesis are summarized in this and thefollowing slide:
• Each process constructor has a corresponding VHDL-template
• ForSyDe functions and data types are translated to VHDL
f g
v
mooreSY
v
delaySY
f
mapSYf HW
Register
CLK
f HWRegister
CLKgHW
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Hardware Synthesis - Process Networks
ForSyDe process networks aremapped to networks of compo-nents
• ForSyDe signals aremapped to VHDL signals
• ForSyDe processes aremapped to VHDLcomponents
P 1
P 2
P 3
C 2
C 3
C 1
C o m p o n e n t M a p
p i n g
S i g n a l M a p p i n g
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
VHDL Synthesis
ForSyDe’s embedded compileris able to translate system de-
nitions to VHDL. This is donethrough the writeVHDL func-tion.
> writeVHDL fSys
The function generates a treestructure containing the VHDLcode of all included subsystems.
f orsyde_l i b.vhd
VHDL
wor k
l i b
fSys_lib.vhd
fSys_lib
fSys.vhd
fSys
colS0.vhdcolS1.vhdexpperm.vhdoutputS0.vhdoutputS1.vhdp4.vhdrowS0.vhdrowS1.vhdxorSubKey.vhd
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FPGA Synthesis using Altera QuartusForSyDe allows to directly create a downloadable le for a specic Altera FPGAcircuit, given that the Altera tools are installed.
Synthesis of encryptSys
compileQuartus_encryptSys :: IO ()
compileQuartus_encryptSys = writeVHDLOps vhdlOps encryptSyswhere vhdlOps = defaultVHDLOps{execQuartus=Just quartusOps}
quartusOps = QuartusOps{action=FullCompilation,fMax=Just 50, -- in MHzfpgaFamiliyDevice=Just ("CycloneII",
Just "EP2C35F672C6"),-- Possibility for Pin AssignmentspinAssigs=[]
}
Quartus generates then reports, which inform about size and speed of the design(encryptSys needs 36 logic elements, 32 pins, and the worst case delay is18.836 ns)
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Deep Embedded ForSyDe - Hardware Synthesis, Graphical Output
FPGA Synthesis Using Altera QuartusOutput from RTL Viewer
• Implementation of encryptSys
• Implementation of fkSys
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FPGA Synthesis Using Altera QuartusOutput from RTL Viewer
• Implementation of fSys
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The SYSMODEL Project
The SYSMODEL project• The Artemis project ’SYSMODEL’ (System Level Modeling
Environment for SMEs) addresses the design process of heterogeneous embedded systems.
•Industrial Partners: Technoconsult, SIB Development(Denmark), Sting Networks, Catena, Solidux (Sweden),DA-Design, Finnelpro (Finland), Novelda (Norway)
• Academic Partners: Technical University of Denmark, RoyalInstitute of Technology (Sweden), Tampere University of Technology (Finland)
• The projected has started in January 2009 and has a durationof three years.
Ingo Sander (KTH) ForSyDe October 9, 2009 71 / 83The SYSMODEL Project
SYSMODEL: ObjectivesThe SYSMODEL project follows the platform-based design approach.There are the following main objectives:
• Development of modeling and simulation framework for analysisand design of embedded systems and systems-on-chip.
• System Functionality Framework• Platform Architecture Framework• Design Space Exploration: Analysis, Mapping and Testability• Verication of models
The results of the project shall increase productivity in industry.
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The SYSMODEL Project
Models and Languages• To provide a base for formal methods, the system functionality
framework is based on theForSyDe modeling framework.• To allow for industrial exploitationSystemC is used as the main
modeling language both for the system functionality frameworkand the platform architecture framework.
• Already today several dialects for different models of computation exist. However, they often lack a formal semantics.
• Other languages, such as VHDL for hardware models orC/C++ for algorithms shall be integrated in the framework.
• An industrial ’renement-by-replacement’ approach shall besupported. Parts of the system functionality models shall bereplaced by executable platform models and then co-simulatedwith the system functionality models.
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ForSyDe System Model• A system is modeled as hierarchical concurrent process model• Processes of different models of computation communicate via
domain interfaces• Supported MoCs: Synchronous, Untimed (Synchronous Data
Flow), Continuous Time
AB
AB
P 1
P 3
P 2 P 4
P 5
MoC B
MoC A
Systems containing analog, digital and software parts can be modeledat different levels of abstraction!
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The SYSMODEL Project
SystemC• SystemC is a class library built on top of the C++ language.• SystemC adds concurrency and notion of time to C++ to allow
to model systems.• The semantics of SystemC is very different from C++.• Systems in SystemC are modeled network of communicating
processes. Computational processes are encapsulated inmodules, while the communication among them is performedthrough channels.
Module
ProcessesPort
Interface Channel
Module
ProcessesPort
Interface
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SYSMODEL: ForSyDe is implemented in SystemC
MoC A
ChannelMoC A - MoC A
Port
MoC A - MoC BChannel
ModuleSystemC
MoC B
P 2
P 1
P 3 P 5
P 4
SYSMODEL: Modeling rules will be developed in order to write Sys-
temC models to comply to the ForSyDe semantics!
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The SYSMODEL Project
SYSMODEL: System Functionality Framework
Continuous Time Model (CT) Synchronous Model (SY)Synchronous Data Flow Model (SDF)
SystemCCT
SystemCSY
ChannelCT - SY
VHDLSY
SystemCSY
LegacyC-Code
SDF
ChannelSY-SDFSY-SY
Channel
SystemC WrapperSystemC Wrapper
The System Functionality Model is modeled in SystemC. Other languages can beimported by means of SystemC-wrappers. The whole model can be co-simulated.
Ingo Sander (KTH) ForSyDe October 9, 2009 77 / 83The SYSMODEL Project
SYSMODEL: Replacement by Renement
Continuous Time Model (CT) Synchronous Model (SY)
SystemCCT
SystemCSY
ChannelCT - SY
VHDLSY
LegacyC-Code
SDF
ChannelSY-SDFSY-SY
Channel
C-Code
ISS
SystemC WrapperSystemC WrapperSystemC Wrapper
Synchronous Data Flow Model (SDF)
Replaced by platform component
A SystemC block has been rened and replaced by C-code that runs on aninstruction set simulator, which belongs to the platform architecture framework.The whole model can be co-simulated.
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The SYSMODEL Project
The ANDRES projectForSyDe has been used as formal framework in the FP6 ANDRES project:(Analysis and Design of run-time Recongurable, heterogeneous Systems). TheANDRES project used SystemC as design language. As part of the project
• a specication methodology
• a performance analysis method
for recongurable systems has been developed.
Facts on ANDRES
• Industrial Partners: Thales Communications (France), DS2 (Spain)
• Academic Partners: OFFIS (Germany), Royal Institute of Technology (Sweden),Technical University Vienna (Austria), University of Cantabria (Spain)
• The projected has started in June 2006 and will nish in September 2009.
Ingo Sander (KTH) ForSyDe October 9, 2009 79 / 83Conclusion and Future Work
Conclusion• Complex adaptive heterogeneous systems can be modelled and
simulated in ForSyDe• Deep-embedded ForSyDe implementation allows to extract
structural information of a ForSyDe model
• used for hardware synthesis• Connection to Altera Quartus (FPGA-Synthesis)• Connection to Modelsim (VHDL-Simulator)
• used for graphical output (GraphML)• So far deep-embedded presentation is only possible for
synchronous models• Not all desired constructs can yet be synthesized• Template Haskell allows to extract the structural information,
but implies a less intuitive syntax
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Conclusion and Future Work
Future Work• Extension of VHDL-backend
• More synthesizable constructs• At present only Int8 , Int16 , and Int32 are supported• Higher-order functions on xed-sized vectors cannot be
synthesized, such as FS.zipWith.xor s1 s2 .• Better support for pattern matching• Introduce optimization capabilities into VHDL-backend
• So far compiler does only map ForSyDe-model to VHDL• Extension of deep-embedded implementation to additional
models of computation• So far only synchronous model is supported
• Adaptation to new problem areas• Software synthesis• Formal verication• Performance analysis• Design transformation
Ingo Sander (KTH) ForSyDe October 9, 2009 82 / 83Conclusion and Future Work
Thanks for your attention!
More information on Haskellhttp://www.haskell.org/
More information on ForSyDehttp://www.ict.kth.se/forsyde/
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