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8/10/2019 Lecture2 Algo
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12/16/2014
1
VLSI Physical Design Automation
Prof. David Pan
dpan@ece.utexas.edu
Office: ACES 5.434
Lecture 2. Review of Device/VLSI/Algorithm
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Objective of this Lecture
To review the materials used in fabrication of VLSI
devices.
To review the structure of devices and process
involved in fabricating different types of VLSI circuits
To review the basic algorithm concepts
To level-set everyone so that we can get into serious
Physical Design topics in the next lecture
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Wafer, Die and Package
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Fabrication Materials
copper
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Electron and Holes
Holes travel as do electrons
Material can be enriched in holes or electrons by introducing impurities
Holes in crystals can be enriched by embedding some boron atoms
Electrons in crystals can be enriched by embedding phosphorus atoms
Recent breakthroughs: strained silicon (IBM) to stretch silicon such that
electrons experience less resistance and flow up to 70% faster
Free
Electron
Silicon
atom
+Ion
Holehttp://researchweb.watson.ibm.com/resources/press/strainedsilicon/
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The Three Regions in a n-p Junction
A mask is a specification of geometric shapes that need tobe created on a certain layer. Masks are used to create a
specific patterns of each material in a sequential manner
and create a complex pattern of several layers
Electron
richInterface Hole rich
Carrier-depletion
zone
MaskSilicon dioxideinsulator
Phosphorous
Depletionzone
Substrate( a ) ( b ) ( c )
Formation of a Diffused Junction
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A nMOS Transistor
Enhancement Mode
Source Gate Drain Channel
Gate
Source Drain
Vg<Vt Vg Vt
Vs Vs Vd Vd
( c )
( a ) ( b )
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Fabrication of VLSI Circuits
1. Create
2. Define
3. Etch
Material formation by deposition,diffusion or implantation
Pattern definition by
photolithography
Etch
8 to 10 iterations
Silicon wafers
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Details of Fabrication Processes
Crystal growth & wafer preparation
Epitaxy
Dielectric & polysilicon film deposition
Oxidation
Diffusion
Ion implantation
Lithography
Etching
Packaging
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Basic Design Rules
1. Size Rules2. Separation Rules
3. Overlap Rules
Basic nMOS Design Rules
Diffusion Region WidthPolysilicon Region WidthDiffusion-Diffusion SpacingPoly-Poly Spacing
Polysilicon Gate ExtensionContact ExtensionMetal Width
2
2
3
2
2
3
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Size and Separation Rules
Incorrectly and Correctly Formed Channels
Diffusion
Short
Poly
Incorrectly formed
Channel
Correctly formed
Metal
Diffusion Poly
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Overlap Rules for Contact cuts
( a ) ( b )
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Layout of Basic Devices
nMOS Inverter
CMOS Inverter
nMOS NAND Gate
CMOS NAND Gate
nMOS NOR Gate
CMOS NOR Gate
Complicated devices are constructed by using basic devices
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A CMOS Inverter
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A CMOS NAND Gate
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A CMOS NOR Gate
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Additional Fabrication Factors
Scaling
Parasitic Effects
Yield Statistics and Fabrication Costs
Delay Computation
Noise and Crosstalk
Power Dissipation
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Mini Summary
The three types of materials are insulators, conductors andsemiconductors
A VLSI chip consists of several layers of different materials on
a silicon wafer.
Each layer is defined by a mask
VLSI fabrication process patterns each layer using a mask
Complex VLSI circuits can be developed using basic VLSI
devices
Design rules must be followed to allow proper fabrication
Several factors such as scaling, parasitic effects, yieldstatistics and fabrication costs, delay computation, noise and
crosstalk and power dissipation play a key role in fabrication
of VLSI chips
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Complexity of
VLSI circuits
Full custom
Performance Size Cost Market time
Standard Cell Gate Array FPGA
Different design styles
Cost, Flexibility, Performance
Design Styles
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Full Custom Design Style
Pad Metal Via Metal 2
I/OData Path
ROM/RAM
PLA
A/D ConverterRandom logic
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Standard Cell Design Style
VDD
Metal 1Cell
Metal 2Feedthrough GND
D C C B
A C C
D C D B
C C C B
Cell A
Cell C
Cell B
Cell DFeedthrough cell
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Gate Array Design Style
A
B
C
A
B
C
VDD Metal1 Metal2
Structured ASICs (hot topics nowadays) are essentially gate array
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FPGA Design Style
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Programmable logic
Programmable interconnects
Programmable inputs/outputs
Field-Programmable Gate-Arrays (FPGAs)
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Comparisons of Design Styles
full-custom standard cell gate array FPGA
cell size variable fixed height * fixed fixed
cell type variable variable fixed programmable
cell placement variable in row fixed fixed
interconnections variable variable variable programmable
* uneven height cells are also used
style
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Area
Performance
Fabrication
layers
style
full-custom standard cell gate array FPGA
compact
high
compact
to moderatemoderate large
high
to moderatemoderate low
ALL ALLrouting
layers none
Comparisons of Design Styles
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Printed Circuit Board
PCB
Multi-Chip Module
MCM
Wafer Scale Integration
WSI (SOC)
Packaging
Area
Performance, cost
The increasing complexity and density of the semiconductor devices
are driving the development of more advanced VLSI packaging and
interconnection approaches.
Packaging Styles
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History of VLSI Layout Tools
Year Design Tools
1950 - 1965
1965 - 1975
1975 - 1985
1985 – 1995
1995 – 2002
2002 - present
Manual Design
Layout editorsAutomatic routers( for PCB)Efficient partitioning algorithm
Automatic placement toolsWell Defined phases of design of circuitsSignificant theoretical development in all phases
Performance driven placement and routing toolsParallel algorithms for physical designSignificant development in underlying graph theoryCombinatorial optimization problems for layout
Interconnect layout optimization, Interconnect-
centric design, physical-logical codesign
Physical synthesis with more vertical integrationfor design closure (timing, noise, power, P/G/clock,manufacturability)
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Now You Need Algorithms
• To put devices/interconnects together into VLSI chips
• Fundamental questions: How do you do it smartly?
• Definition of algorithm in a board sense: A step-by-step procedure for solving a problem. Examples: – Cooking a dish
– Making a phone call
– Sorting a hand of cards
• Definition for computational problem: A well-defined
computational procedure that takes some value asinput and produces some value as output
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• Input: An array of n numbers D[1]…D[n].
• Output: An array of n numbers E[1]…E[n] such that
E[1] E[2] … E[n].
• Algorithm:1. For i from 1 to n do
2. Select the largest remaining no. from D[1..n].
3. Put that number into E[i].
Example: Selection Sort
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Some Algorithm Design Techniques
• Greedy
• Divide and Conquer
• Dynamic Programming
• Network Flow
• Mathematical Programming (e.g., linear programming,integer linear programming)
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Reduction
• Idea: If I can solve problem A, and if problem B can betransformed into an instance of problem A, then I cansolve problem B by reducing problem B to problem Aand then solve the corresponding problem A.
• Example: – Problem A: Sorting
– Problem B: Given n numbers, find the i-th largest numbers.
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Analysis of Algorithm
• There can be many different algorithms to solve thesame problem.
• Need some way to compare 2 algorithms.
• Usually run time is the most important criterion used – Space (memory) usage is of less concern now
• However, difficult to compare since algorithms may beimplemented in different machines, use differentlanguages, etc.
• Also, run time is input-dependent. Which input to use?
• Big-O notation is widely used for asymptotic analysis
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Big-O Notation
• Consider run time for the worst input=> upper bound on run time.
• Express run time as a function input size n.• Interested in the run time for large inputs.
• Therefore, interested in the growth rate.• Ignore multiplicative constant.• Ignore lower order terms.
• 3n2+6n+2.7 is O(n2).
• n1.1+10000000000n is O(n1.1).• n1.1 is also O(n2), but to be more precise, it is O(n1.1)
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Effect of Multiplicative Constant
0
100
200
300
400500
600
700
800
0 10 20 n
R u n t i m
e
n2
10n
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Growth Rates of some Functions
n
nnn
nn
ncc
nOnO
OOO
OnO
cOnO
nOnO
nOnOnnOnnO
nOnOnOnO
!
432
2
constantanyfor2
loglog
loglog
2loglog
log
43
25.12
2
E x p on en t i al
F u
n c t i on s
P ol y n omi al
F un c t i on
s
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Problem of Exponential Function
• Consider 2n
, value doubled when n is increased by 1.
• If you borrow $10 from a credit card with APR 18%, after40 yrs, you will own $12700!
n 2n 1ms x 2n
10 103 0.001 s
20 106 1 s
30 109 16.7 mins
40 1012 11.6 days
50 1015 31.7 years
60 1018 31710 years
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NP-Complete
• The class NP-Complete is the set of problems whichwe believe there is no polynomial time algorithms.
• Therefore, it is a class of hard problems.
• NP-Hard is another class of problems containing the
class NP-Complete.
• If we know a problem is in NP-Complete or NP-Hard,there is no hope to solve it efficiently.
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NP-Complete
• I can't find an efficientalgorithm, I guess I'm just toodumb.
• I can't find an efficientalgorithm, but neither can allthese famous people.
• I can't find an efficientalgorithm, because no suchalgorithm is possible.
Source: Computers and Intractibility by Garey and Johnson
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Solution Type of Algorithms
• Polynomial time algorithms
• Exponential time algorithms
• Special case algorithms
• Approximate algorithms
• Heuristic algorithms
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Before Next Class
• Refresh your Algorithms: – C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of
Algorithms for Physical Design Automation, AuerbachPublications, 2008
– T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. SteinIntroduction to Algorithms, MIT Press, 2009 (3rd edition)
• Circuit partitioning in the next class
Recommended