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Page 198學年度(上)
Final Project
• You can choose either
(1) 16-channel16-channel gate driver circuit gate driver circuit or
(2) 2-bit 6-channel2-bit 6-channel source driver source driver
as your final project
評分標準 : (1)gate driver :70~90
(2)source driver:80~100
Page 298學年度(上)
Flat Panel Display : Principle and Driving Flat Panel Display : Principle and Driving Circuit DesignCircuit Design
Final Project (1) – 16-channel16-channel gate driver circuitgate driver circuit
Design a 16-channel gate driver circuit for TFT-LCD
Please use the level shifter shown in next page.
Use H-SPICE with 0.35um model ‘l35uhv12v’
Use a 5-level RC load (R=2KΩ, C=25pF)
You must finish a final report in power point or Word form
before 99/1/14 (17:00) and mail to the teacher.
Page 398學年度(上)
Level Shifter
• Vin=0~Vcc
– Vcc=3.0V
• Vout=0~AVdd
– AVdd=12VVcc
GND
Vout
N2
P2
Vcc
GND
N1
P1
Vin
N3
P3
Vcc
AVdd
P4
AVdd
VccN4
Page 498學年度(上)
Function block of gate driver
• Function block of gate driver circuit
16-bitShift register
Level ShifterBuffer
(Inverter)
Load
CLK
STP
Reset
Vout
Page 598學年度(上)
Load
• 5-level RC load
2K 2K 2K 2K 2K
25pF 25pF 25pF 25pF 25pF
Vout1
1-channelGate DriverCircuit
Vout2
Page 698學年度(上)
Flat Panel Display : Principle and Driving Flat Panel Display : Principle and Driving Circuit DesignCircuit Design
The project must include:
Schematics (gate level) of all block
SPICE netlist file
Timing diagram
Vout1, Vout2 & All Control Signals
Rising/falling times
Find current consumption – i(Vcc) & i(Vdda) and Iave(Vcc) & Iave(Vdda)
for digital and analog circuits, respectively.
Find total power consumption (instaneous and average).
Discussions ( and what you have learned )
References
Page 798學年度(上)
Notice
• If you have any problem, please e-mail
to me or call 0935-761741.
Page 898學年度(上)
Flat Panel Display : Principle and Driving Flat Panel Display : Principle and Driving Circuit DesignCircuit Design
Final Project (2) – 2-bit 6-channel2-bit 6-channel source driversource driver1 persons in a group
Design a 2-bit 6-channel source driver for TFT-LCD
Source driver circuits are based on your homework 1~3
Use Nanosim/Powermill or H-SPICE with 0.35um model
‘l35uhv12v’
Use a 5-level RC load (R=2KΩ, C=25pF)
You must finish a final report in power point or Word form
before 99/1/14 (17:00) and mail to the teacher.
Page 998學年度(上)
Flat Panel Display : Principle and Driving Flat Panel Display : Principle and Driving Circuit DesignCircuit Design
The project must include:Schematics (gate level) of all block (see next page)SPICE fileTiming diagram
Vin & All Control Signals & Vout ： Vin ： 2-bit for each R 、 G 、B (see page 4~5)
Rising/falling/settling(rise & fall) times Offset voltages for each level
Find current consumption – i(Vcc) & i(Vdda) and Iave(Vcc) &
Iave(Vdda) for digital and analog circuits, respectively.
Find total power consumption (instaneous and average).Discussions ( and what you have learned )References
Page 1098學年度(上)
Block Diagram of Source Driver IC
OUT[1]
DIO1 DIO2
VGAMMA[1-4]
R[1-2]G[1-2]B[1-2]
CLK
(SHL)POLCLK1(EQC)
An
alog
(LS
, DA
C, B
uffer)
Vcc/gnd
OUT[2]
OUT[3]
OUT[4]
OUT[5]
OUT[6]
Vdda/Agnd
6 bit
Dig
ital (SR
, Latch
1&2)
Page 1198學年度(上)
Input Data
• 2-bit x R 、 G 、 B data input (6-bit)
– Red : level 0123…
– Green : level 1230…
– Blue : level 2301…
• Please run at least 6 clock cycles
• Clock frequency = 100 KHz
• Please use “dot inversion”
Page 1298學年度(上)
Timing of Input Data
Data
CLK
DIO1
6 CLKs
Invalid Valid
DIO2
6 Outputsfor 1~2 Pixel
P1 P2 P3 P4 P5 P6
Page 1398學年度(上)
Digital Circuit Block
• Shift Register and Latch
SR-1 SR-2DIO1 DIO2
Latch 1 (6x2 bit)
Latch 2 (6x2 bit)
Vdata
Ctrl
‘Ctrl’ is generated from ‘CLK1’
6 bit
CLK
CLK
Page 1498學年度(上)
Analog Circuit Block
ACELL
SW-P
SW-N
SW-N
LVSH
LVSH
LVSH
LVSH
(EQC)POLVpos,ref[1-2]
D1[0:1]
D2[0:1]
D3[0:1]
D4[0:1]
OUT1
OUT2
OUT3
OUT4
Vneg,ref[1-2] CLK1
OP
OP
OP
OP
SW-P
SW-N
LVSH
LVSH
D5[0:1]
D6[0:1]
OUT5
OUT6
OP
OP
SW-P
Page 1598學年度(上)
Level Shifter
• Vin=0~3V
– Vcc=3V
• Vout=0~12V
– AVdd=12V
Vcc
GND
Vout
N2
P2
Vcc
GND
N1
P1
Vin
N3
P3
Vcc
AVdd
P4
AVdd
VccN4
Page 1698學年度(上)
Load
2K 2K 2K 2K 2K
25pF 25pF 25pF 25pF 25pF
Vout1
Source DriverCircuit
Vout2
Page 1798學年度(上)
VGamma for DAC
• For negative polarity ：
Vgamma[1]=0.5V ，Vgamma[2]=5.0V ；
negative polarity is from 0.5 to 5V, 4 level,
step 1.5V ； • For positive polarity ：
Vgamma[3]=7V ，Vgamma[4]=11.5V ；
positive polarity is from 7 to 11.5V, 4 level,
step 1.5V ；
Page 1898學年度(上)
Timing Diagram of Output
Tst
P O L
O dd outputs
E ven outpu ts N egative
P ositive
Tst
V com
O utput
Output load condition :
LD
1K
15P
1K
15P
1K
15P
1K
15P
1K
15P
H igh -Z H igh -Z
H igh -Z
LD is generated from CLK1
Page 1998學年度(上)
Notice
• If you have any problem, please e-mail
to me or call 0935-761741.
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