Synopsys Synthesis Overview -...

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SynopsysSynopsys Synthesis OverviewSynthesis Overview

Ben2006.02.16

Graduate Institute of Electronics Engineering, NTU

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OutlineOutlineIntroductionSetting Design EnvironmentSetting Design ConstraintsSynthesis Report and Analysis

Graduate Institute of Electronics Engineering, NTU

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What is SynthesisWhat is SynthesisSynthesis = translation + optimization

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Logic Synthesis OverviewLogic Synthesis Overview

no timing info.

timing info.

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SynopsysSynopsys Related FilesRelated Files

NoteThese 3 files are always read in the same order.Any repeated command can override the previous one.

Set path and environment variables and license check.cshrc

Three distinct files are read and executed when DC is invoked1. system-wide (do not modify):

(e.g. $SYNOPSYS/admin/setup/)2. User’s home directory (e.g. ~think/)3. User’s current working directory (e.g. ~think/dv/)

.synopsys_dc.setup

Set X terminal display variables.Xdefault

PurposeFiles

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Synthesis Design FlowSynthesis Design FlowSpecification

RTL Coding Prepare

Setting Design Environment

Setting Design Constraint

Compile Design

Analysis

CellLibrary

Gate-level Netlist

Develop the HDL design description and simulate the design description to verify that it is correct.Set up the .synopsys_dc.setup file.

Set the appropriate technology, synthetic, and symbol libraries, target libraries, and link libraries.Set the necessary compilation options, including options to read in the input files and specify the output formats.

Read the HDL design description.Define the design.

Set design attributesDefine environmental conditionsSet design rulesSet realistic constraints (timing and area goals)Determine a compile methodology

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Setting Design EnvironmentSetting Design Environment

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Setting Design EnvironmentSetting Design EnvironmentSetting Operating EnvironmentSetting Input Driving StrengthSetting Output LoadingSetting Input/Output DelaySetting Wire Load Model

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Setting Operating EnvironmentSetting Operating EnvironmentAttributes/Operating Environment

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Setting Operating ConditionSetting Operating ConditionAttributes/Operating Environment/Operating Condition

dc_shell> set_operating_conditions “slow”

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Setting Input Drive ImpedanceSetting Input Drive ImpedanceAttribute/Operating Environment/Drive Strength

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Setting Input Drive ImpedanceSetting Input Drive ImpedanceAlso can be set using “drive_of” command

Example: (P2A cell output)

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Setting Output LoadingSetting Output LoadingAttribute/Operating Environment/Load

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Setting Output LoadingSetting Output LoadingAlso can be set using load_of:

Example: (bufferd1 cell input)

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Setting Input DelaySetting Input DelaySelect input portsAttributes/Operating Environment/Input Delay

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Setting Output DelaySetting Output DelaySelect output portsAttributes/Operating Environment/Output Delay

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Setting Wire Load ModelSetting Wire Load ModelWire load model estimates wire capacitance based on chip area & cell fanoutSetting this information during compile in order to model the design more accuratelyAttributes/Operating Environment/Wire Load

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Setting Design ConstraintsSetting Design Constraints

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ConstraintsConstraintsConstraints are goals that the Design Compiler uses for optimizing a design into target technology library.Design Rule Constraints : technology-specific restriction; ex. maximum transition, maximum fanout, maximum capacitance.Optimization Constraints : design goals and requirements; ex. maximum delay, minimum delay, maximum area, maximum power.During compile, Design Compiler attempts to meet all constraints.

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Setting Design ConstraintsSetting Design ConstraintsOptimization Constraints

Basic clock constraints conceptConstraints & STA for Special CircuitConstraints for Area

Design Rule ConstraintsFinal check constraints before compile

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Define Clock SpecificationDefine Clock SpecificationWhat should be defined?

PeriodWaveformUncertainty

Skew

LatencySource latency (option)Network latency

TransitionInput transitionClock transition

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Specify Clock Constrains Specify Clock Constrains Select clock portAttributes/Clocks/Specify creat_clock : define your clock’s

waveform & respect the set-up time requirements of all clocked flip-flops

creat_clock “clk”-period 50 -waveform {0 25}

set_fix_hold : respect the hold time requirement of all clocked flip-flops

set_fix_hold clkset_dont_touch_network : do not re-buffer the clock network

set_dont_touch_network clk

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Constraints & STA for Special CircuitConstraints & STA for Special CircuitWhat should be noticed?

Multicycle PathClock Gating TechniqueLatch-Based & Timing Borrow AnalysisFalse Pathset_case_analysisMultiple Clocks Overlapping

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MulticycleMulticycle PathPath

To define setup multiplier 2 for the path from FF1 to FF2 but maintain a hold multiplier 0, use command:

set_multicycle_path 2 -from FF1 -to FF2

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False PathFalse PathA false path is a timing path that cannot propagate a signal, or a path we wish to ignore timing constraints.The set_false_path can be used to disable timing-based synthesis on a path-by-path basisIt is useful for:

Constraining asynchronous pathsConstraining logically false paths

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Setting Area ConstraintSetting Area ConstraintAttributes/OptimizationConstraints/Design ConstraintsArea Unit : gates

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Setting Design ConstraintsSetting Design ConstraintsOptimization Constraints

Basic clock constraints conceptConstraints & STA for Special CircuitConstraints for Area

Design Rule ConstraintsFinal check constraints before compile

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Design Rule ConstraintsDesign Rule ConstraintsDesign rules can’t be violated at any cost, even if it will violate the timing and area goal.Three kinds of design rule constraint are set:

set_max_transitionset_max_fanoutset_max_capacitance

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Setting Design ConstraintsSetting Design ConstraintsOptimization Constraints

Basic clock constraints conceptConstraints & STA for Special CircuitConstraints for Area

Design Rule ConstraintsFinal check constraints before compile

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Check DesignCheck DesignAfter you set up the deign attributes & design constraints, we recommend the next step is to check designAnalysis/Check DesignThe warning message is called “multiple design instance”, it results from that you use the same HDL description to represent more that one design instanceHow to handle ?

dont_touchungroupuniquify

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Method 1: Method 1: dont_touchdont_touchProcedures

Constrain the blockCompile the blockSelect the multiple design instances blockAttributes/Optimization Directives/Design & set the Don’t Touch buttonCompile the whole design using hierarchy compile

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Method 2: UngroupMethod 2: UngroupProcedures

Select the multiple design instances blockAttributes/Optimization Directives/Design & set the Ungroup buttonCompile whole design using hierarchy compile

Remove a single level of hierarchyDoes not preserve the hierarchyTake more memoryTake more compile time

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Method 3: Method 3: UniquifyUniquify

Create a unique design file for each instanceMay select one cell or entire design hierarchy to be uniquifyAllow design to be customized to its interfaceIf the environment varies significantly, use uniquify rather than compile+dont_touchUniquify uses more memory and cause longer compile time than compile+dont_touch

Select the most top designof the hierarchyEdit/Uniquify/Hierarchy

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Multiple Design Instance (summary)Multiple Design Instance (summary)Use “dont_touch, ungroup, uniquify” to fix itThe easiest way is uniquify, but needs much memory & compile timeIf you want to preserve the hierarchy & source sharing, use don’t_touchIf you want your design to have the BEST result, recommend to use ungroup, but it needs the most memory and compile time

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Setting Design ConstraintsSetting Design ConstraintsOptimization Constraints

Basic clock constraints conceptConstraints & STA for Special CircuitConstraints for Area

Design Rule ConstraintsFinal check constraints before compile

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Check Constraints & AttributesCheck Constraints & AttributesUse the following reports to check constraints & attributes before compilingAnalysis/Report

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Save Constraints & AttributesSave Constraints & AttributesSave attributes & constraints setting as the design setup file in dc_shell command format, use File/Save Info/Design Setup

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Execute Script FileExecute Script FileExecute dc_shell command script file, use Setup/Execute Script

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Synthesis Report and AnalysisSynthesis Report and Analysis

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ReportReportAnalysis/Report

From report and analysis, you can find the set attributes and the results after optimization

Attribute reportsAll attributes, clock, port,design, net

Analysis reportsArea, hierarchy, constraints,timing, point timing

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Timing ReportTiming Report

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Analyze Circuit with SchematicAnalyze Circuit with SchematicTo determine the time the signal arrived at pin which is selected in the schematicAnalysis/Show Timing

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Analyze Circuit with SchematicAnalyze Circuit with SchematicTo determine the net load which selected in the schematicAnalysis/Show Net Load

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Save DesignSave DesignSave your design in verilog format, run Verilog gate-level simulation, and we will use Verilog In interface to translate it into OPUS database for place & routeIf you can’t Verilog In, please check assign problemif there is any assignment problem, choose the block & use the dc_shell command as follow to fix it

set_fix_multiple_port_nets -all -buffer_constantscompile -map_effort medium

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GateGate--Level Simulation (Verilog)Level Simulation (Verilog)Write out gate-level netlist

File/Save As Verilog (for File format)dc_shell> write -format verilog –hierarchy -output chip.vg

Get SDFFile/Save Info Design timing Select chip.sdfdc_shell> write_sdf –version 1.0 -context verilog chip.sdf

Modify your testbench file$sdf_annotate (“the_SDF_file_name”, top_module_instance_name);

Simulation using Verilog-XL>> Verilog chip.vg testbench.v –v cell_model.v

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Design ExampleDesign Example

Ben2006.02.16

Graduate Institute of Electronics Engineering, NTU

pp. 47

SynopsysSynopsys Design Vision (GUI) /Design Vision (GUI) /Design Compiler (text mode) Design Compiler (text mode)

Unix% dv –dcsh_mode & Unix% dc_shell

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Read Read VerilogVerilog FileFile

read -format verilog {"Lab1_alu.v"}

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Schematic viewSchematic viewSynopsys Design analyzer will translate verilog code into G-tech model. Double click the icon “ALU”, and click the right button then choose Schematic view. We can get the G-tech MAP

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Symbol viewSymbol viewOr you can create a symbol view by click on the following symbolview button. The symbol view is as the right window

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Set Clock (1/2)Set Clock (1/2)“Attributes”-“Specify Clock”

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Set Clock (2/2)Set Clock (2/2)Specify the clock as period 10ns. (100 MHz). Don’t forget to select “don’t touch network” and “fix hold”

create_clock -name "clk" -period 10 -waveform {"0" "5"} {"clk"}set_dont_touch_network find( clock, "clk")set_fix_hold clk

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Operating ConditionOperating Conditionset_operating_conditions "typical" -library "typical"

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WireloadWireload ModelModelset_wire_load_model -name "ForQA" -library "typical"set_wire_load_mode "segmented"

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Operating EnvironmentOperating EnvironmentSelect “inputA” in the Symbol View and click “Attribute”-“operating environment”-“input delay”. Set 2.5ns input delay.

set_input_delay -clock clk 2.5 inputA[*]set_input_delay -clock clk 3.8 inputB[*]set_input_delay -clock clk 4.5 instruction[*]set_input_delay -clock clk 5.2 reset

set_output_delay -clock clk 8 alu_out[*]

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Area & Area & FanoutFanout & Transition& TransitionClick “Attribute”-”optimization Constraints”-“Design constraints”. Set max area is 0. Max fan-out is 8. max transition is 1.

set_max_area 0set_max_fanout 8 find (design, ALU)set_max_transition 1 find (design, ALU)

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Compile DesignCompile DesignClick “Design”-”Compile Design”. Click “OK”, start to optimize ALU

compile -map_effort medium

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ReportReport

report_timing -path full -delay max -max_paths 1 -nworst 1report_powerreport_area -nosplit

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Save FilesSave FilesSave gate-level netlist. Select “File”->”Save As”Save your design. Select “File”-“Save”Save the timing information. Select “File”-“Save Info”-”Design Timing”, choose sdf format.

Save script file with the constraints you have made. Use “write_script > script_file” command or “File”-”Save Info”-”Design Setup“ button.Re-run all steps automatically. Use “include script_file”command or “File”-“Execute Script” button.

write -format verilog -hierarchy -output "ALU_s.v" find (design, ALU)write -format db -hierarchy -output "ALU_s.db" find (design, ALU)write_sdf ALU_s.sdf

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gate level simulationgate level simulationBefore gate level simulation, $sdf_annotate(“top_design.sdf”, top_design)must be added after initial in testbench`timescale 1ns/10ps must be added in the 1st line of testbench

//RTL simulationUnix% verilog testfixture.v

//gate level simulationUnix% verilog testfixture_vg.v –v umc18.v

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View wave formView wave formUnix% nWave&Open verilog.dump file to see the waveform