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Test Solution Challenges
2012.10.31
삼성전자㈜ Test 기술팀
Contents
DFT & BOST2
Challenges for Future Test4
33
Device Roadmap31
TSV
1 / 20
Mobile Market 변화
‘91 ‘93 ‘95 ‘97 ‘99 ‘01 ‘03 ’05 ‘ 07 ’09 ’11 ’13 ’15 ’17
PC DRAM장기호황
NAND 수요형성PC DRAM 호황
메모리 Trend 주요 변수1) 수요 : 스마트폰, PC 출하량과 시스템 메모리 채택2) IT 수요 동향 및 신규 제품 출시
PC DRAM단기호황
모바일 및Nand 급성장기
IBM,MS,INTEL주도 노키아,인텔,삼성,퀄컴주도 애플,구글,삼성주도
Mobile 혁명AP+LP+NAND
수요 급증
매출
1. Device Roadmap
2 / 20
DRAM1. Device Roadmap
3 / 20
DRAM1. Device Roadmap
4 / 20
Card1. Device Roadmap
5 / 20
SSD1. Device Roadmap
6 / 20
MCP1. Device Roadmap
7 / 20
Flash Storage I/F Trend1. Device Roadmap
8 / 20
Normal Operation Time
256M 512M 1G 2G 4G 8G 16G
10S
50S
100S
200S
400S
800S
Time/6n[Sec]
Density[Bit]
5ea
10ea
20ea
30ea
40ea
50ea
Test Item
※ 산출기준 : DRAM x8, 6N Pattern, Test Time 500Sec
0.6ea1.2ea
41ea
21ea
10ea
5.2ea
2.6ea
※ 제품 고용량화에 따라 단위시간기준 Test coverage 향상 필요
1. Device Roadmap
9 / 20
Multi W/L Activation2. DFT & BOST
10 / 20
Multi Cell Test
A C
H
G
B D F
EM
ulti
Dat
a
Multi
Dat
a
CompressData 출력
Compress Compress
2. DFT & BOST
11 / 20
PLL
SERDES
FPGA
Signal Switching
FPGA
Look Up table
Low-End ~ Middle End 설비 성능향상 기술로 활용
ATE + BOST 접목을 위한 기술활동 필요
고속 제품 대응 → ASIC 개발
FPGA
BOST
Speed Parallelism Function
2. DFT & BOST
12 / 20
BOST
MASTERFPGA
DR[34]
I/O[9]
I/O[9]
SLAVEFPGA
SOCKET BOARDBASE BOARD
VDD- PPS
40I/O
DR[2]Power Block
DR
DR
DR
DR
27DR
27DR
27DR
40I/O
40I/O
40IO
JTAG
ATE
AC
27DR
DUT1
DUT2
DUT3
DUT4
I/O[9]
I/O[9]
DR[1]
DR[1]
DC Meas
DR[6]
PLL
Look up table
FIFO
PLL
Look up table
FIFO
2. DFT & BOST
14 / 20
TSV3. TSV
15 / 20
TSV (COW : Chip On Wafer)3. TSV
16 / 20
Boundary SCAN & Memory BIST4. Challenges for Future Test
17 / 20
Adaptive Test
Higher Quality, Fast Test Time ReductionLower cost, Fast yield learning
출처 : ITRS2011
4. Challenges for Future Test
18 / 20
Test Parallelism4. Challenges for Future Test
19 / 20
Challenges for Future Test
구 분 항 목 내 용
DFTTest Algorithm Cost Effective Algorithm 개발
Repair Package Repair 및 특성 Trimming
BOSTFPGA Speed 상용 FPGA Speed Limitation 극복
고속 ALPG 3.2Gbps↑동작 ALPG 개발
TSV
TSV Contact Test 20um↓ upad contact 기술개발
Thermal Control 적층 구조 Heat Sink 기술개발
BIST & SCANFlexible Memory BIST, e-Fuse RepairSCAN Coverage 향상
TesterATE Platform 표준화, Concurrent Test
실장형 Solution 제품 HOST IP 개발
TestInterface
Fine pitch (0.30mm↓) Test Interface 개발 → PCB, H/D Contact
Software Embedded S/W → HDL, Device Driver
20 / 20
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