Week1 Electronic System-level ESL Design and SystemC Begin

Electronic System Level(ESL) Design and SystemC Begin

2014

NCKU CSIE

林英超蘇文鈺林敬倫

Outline

• Electronic System Level (ESL) Design Basics

• Hardware architecture

• SoC Design Flow (系統晶片設計流程)

• SystemC background

• SystemC Syntax by Example

– ex1: Counter

– ex2: Traffic Light

– ex3: Simple Bus

Why learn ESL

• if you are an undergraduate student, and/or

• if you are a C.S. student, and/or

• if you still do not know in which areas you are really interested,

• when you still do not know what ESL is?

Because

• This is one of the best ways to start your learning of C++,

• This is the best way for a C.S. student to study SoC design,

• This is the biggest advantage C.S. students can take over E.E. students in SoC related areas,

• This is one of the best ways to learn lots of tools and languages in HW/SW designs.

What is ESL?

• ESL = Electronic System Level

• ESL doesn’t specify which levels of design should be employed. It focuses on the concepts of designing a system, instead of specific components.

• Then, what is Electronic System Level design flow?

• Design, debug, verify the system using ESL methodologies, languages, tools and CONCEPTS.

What does level mean?

• In HW design, level means the degree of the design details, or the level of abstraction, of the model of the target design. For example,– Transistor level– Gate level– Register transfer level (RTL)– Transaction level– Behavior level– Architecture level– Algorithmic level– …. And so on.

Before the answer is made

• Let’s ask “Why ESL design flow is needed?”– Huge system

– Extraordinarily high complexity

– Design reuse

– Slow simulation speed

– Difficulty in integration

– Mixed/multiple disciplines

– HW/SW co-design/co-simulation/co-….

– And so on.

– Most importantly, time-to-market

Design Complexity from Different Design Generation

David C. Black

Jack Donovan

These are not reasons

• They are just problems. Imagine– You have a system with 10 processor cores, each

having its own memory system. There are sharedmemory spaces for the cores. 20 different peripheralsto control. There are 20 programmers using 8 differentlanguages to develop 30 different applications on thissystem which needs to support 2 different OS. And thebiggest problem is

• To cope with these problems, what do we need?

We need

• A super fast simulator

• A simulator supports mixed abstraction level designs

• An integrated HW/SW co-development environment

• A super fast simulation environment

• … and so on.

• To do this, what are the first few steps?

Hareware? FPGA? MCU?

• Microcontroller：

– CPU, Memory, …, etc.

– Software program

• (.C->.asm->.out)

• FPGA：

– Verlog code, VHDL code.

– Hardware program

• (.v->.bit)

傳統系統 (System-on-a-Board) V.S.系統晶片(System-on-a-Chip)

CPU

IO Bridge

MPEG

DecoderSDRAM

DiskVideo

Encoder

印刷電路板 (System-on-a-Board)

20 cm

CPU

IO Bridge

MPEG

DecoderSDRAM

DiskVideo

Encoder

系統晶片 (System-on-a-Chip)

2 cm

傳統系統開發流程

硬體開發

軟體開發

系統架構

系統規格

系統整合

系統雛形

產品

理想系統開發流程

硬體開發 軟體開發

系統架構

系統規格

系統整合

產品

CoWare : ESL design hardware

OPENESL : ESL design hardware

FPGA : Hardware circuit design and verify

傳統硬體開發方法

• 硬體描述語言

– VHDL, Verilog

– RTL (Register Transfer Level)

• Simulation(模擬)

–非常慢

– Linux開機 = 109小時

硬體設計抽象化

RTL

Gate

Transistor

Architecture

Algorithm

Synthesis

(合成)

Abstraction

(抽象)

High Level

Low Level

PRODUCT DESIGN DEVELOPMENT FLOW

交互驗證Detailed Flow: Early stage

TLM/ESL Modeling stage

Final Integration Stage

Three stage pipeline design：

A. SW model: high abstraction level model

B. TLM model：very close to architecture

C. HW model：HDL

Verification and Debugging

Why SystemC?

• 標準語法 (IEEE Standard 1666)

–模擬系統

–更高抽象化

–既有的C++開發環境

–硬體合成

SystemC Doesn’t Speedup Simulation,

High Level does!!

SystemC Use Case

• 硬體工程師– 硬體描述語言(HDL)

– 更高階、更抽象描述硬體

• 系統工程師– System Virtual Platform (系統虛擬平台)

• Architecture Analysis (架構分析)

• Performance Exploration (效能評估 )

• System Verification (系統驗證)

• 軟體工程師– 早期開發環境

– 更多硬體資訊

SystemC Background

• C++

–物件導向程式語言 (Object-Oriented)

• 類別(Class)

• 純虛擬函式(pure-virtual-function)

• 硬體

–元件(Component)

• 模組(Module)

• 介面(Interface)

SystemC Library

Data types

4-valued logic type

4-valued logic vectors

Bit vectors

Arbitrary-precision integers

Fixed-point types

Core Language

Module

Ports

Processes

Interfaces

Channels

Events

Programming Language C++

Predefined channels

Signals, clock, FIFO,

Mutext, semaphore

Utilities

Vector, strings,

traceing

Methodology- and technology-specific libraies

SystemC verification library, bus models, TLM interface

Application

Written by the end user

Module (模組)

• A Module

– A CPU

– A Gate

• With

– Port (埠口)

– Process (排程)

– Sub-module (子模組)

Port PortProcessPortProcess Port

Top Module

Module 1Module 1

Outline

• Background

– Hardware architecture

– SoC Design Flow (系統晶片設計流程)

– SystemC background

• SystemC Syntax by Example

– ex1: Counter

– ex2: Traffic Light

– ex3: Simple Bus

Example 1 –Counter (計數器)

#include “counter.h”counter::process_func(){

val = 0;while(1){

wait();val = val+1;

}}

#include <systemc.h>SC_MODULE(counter){

// port- declarstions;sc_in_clk clk;sc_out<int> val;

// process declarations;void process_func();

// module constructor;SC_CTOR(counter) {

SC_CTHREAD(process_func, clk.pos());}

};

Module Syntax (語法)

“counter.h” “counter.cpp”

Run Simulation#include “counter.h”int sc_main(int argc, char* argv[]){

// signal declarationsc_clock clk(“clk”, 1, SC_NS, 0.5);sc_signal<int> val;

// module declarationcounter counter0(“counter0”);

// signal connectioncounter0.clk(clk);counter0.val(val);

// run simulationsc_start(100, SC_NS);

return 0;}

“main.cpp”

Outline

• Background

– Hardware architecture

– SoC Design Flow (系統晶片設計流程)

– SystemC background

• SystemC Syntax by Example

– ex1: Counter

– ex2: Traffic Light

– ex3: Simple Bus

Example 2 –Traffic Light (紅綠燈)

Finite State Mache (有限狀態機)

void fsm::cthread_func(){

while(1) {// redred=true, green=false, yellow=false;wait(10);// greenred=false, green=true, yellow=false;wait(10);// yellowred=false, green=false, yellow=true;wait(2);

}}

SC_METHOD

#include <systemc.h>SC_MODULE(light){

// port declarationssc_in<bool> on;

// process declarationsvoid method_func();

// contructorSC_CTOR(light) {

SC_METHOD(method_func);sensitive << on;

}};

#include “light.h”void light::method_func(){

if(on) {printf(“%6lld ps: %s\n”, \

sc_time_stamp().value(),\name())

}}

“light.h” “light.cpp”

紅綠燈

red

green

yellow

clk

on

light “red”

light “green”

light “yellow”

red

green

yellow method

method

methodon

oncthread

fsm“fsm”

執行結果

0 ps: red10000 ps: green20000 ps: yellow22000 ps: red32000 ps: green42000 ps: yellow44000 ps: red54000 ps: green64000 ps: yellow66000 ps: red76000 ps: green86000 ps: yellow88000 ps: red

Process In SystemC

• Methods

• Threads

• Clocked Threads

Methods

• Methods behaves like a function

• Sensitive list signals which trigger a process can be a signal or local variable or port.

Threads

• Thread Process can be suspended.

• The Thread Process can contain wait() functions that suspend process execution until an event occurs on one of the signals the process is sensitive to.

• The process will continue to execute until the next wait()

Clocked Threads

• SC_CTHREAD can have only one bit wide ports as trigger.

Outline

• Background

– Hardware architecture

– SoC Design Flow (系統晶片設計流程)

– SystemC background

• SystemC Syntax by Example

– ex1: Counter

– ex2: Traffic Light

– ex3: Simple Bus

Example 3 –Simple Bus (匯流排)

Interface

#include <systemc.h>class bus_if: public sc_interface {public:

virtual void write(unsigned addr, int data) = 0;virtual void read(unsigned addr, int& data) = 0;

};

“bus_if.h:

Slave – RAM#include “bus_if.h”class ram:

public bus_if,public sc_module {

public:// interface functionvoid write(unsigned addr, int data);void read(unsigned addr, int&data);

// constructorram(sc_module_name);

// destructor~ram();

private:// memory contentsint* pMem;

};

“ram.h”

“ram.cpp”

#include “ram.h”ram::ram(sc_module_name nm)

: sc_module(nm){

pMem = new int[16];}

ram::~ram(){

delete[] pMem;}

void ram::write(unsigned addr, int data){

pMem[addr] = data;}

void ram::read(unsigned addr, int& data){

data = pMem[addr]}

Slave – ROM#include “bus_if.h”class rom:

public bus_if,public sc_module {

public:// interface functionvoid write(unsigned addr, int data);void read(unsigned addr, int&data);

// constructorrom(sc_module_name);

// destructor~rom();

private:// memory contentsint* pMem;

};

#include “rom.h”rom::rom(sc_module_name nm)

: sc_module(nm){

pMem = new int[16];for(int i=0; i<16; i++) pMem[i] = i;

}

rom::~ram(){

delete[] pMem;}

void rom::write(unsigned addr, int data){

assert(0);}

void rom::read(unsigned addr, int& data){

data = pMem[addr];}

“rom.h”

“rom.cpp”

Master

#include “bus_if.h”class cpu: public sc_module {public:

// port declarationsc_in_clk clk;sc_port<bus_if> mem_port;

// process declarationvoid cthread_func();

// constructorcpu(sc_module_name nm);

};

“cpu.h”

#include “cpu.h”cpu::cpu(sc_module_name nm)

: sc_module(nm){

SC_HAS_PROCESS(cpu);SC_CTHREAD(cthread_func, clk.pos);

}

void cpu::cthread_func(){

while(1){

int data;for(int i=0; i<16; i++) {

mem_port->read(i, data);mem_port->write(i+16, data);

}sc_stop();

}}“cpu.cpp”

Bus

bus

cpu

rom ram

master

slave

rom

ram

0x00

0x0f

0x10

0x1f

Memory

Map

Bus#include “bus_if.h”class bus:

public bus_if,public sc_module {

public:// port declarationsc_port<bus_if> rom_port;sc_port<bus_if> ram_port;// interface functionvoid write(unsigned addr, int data);void read(unsigned addr, int&data);

// constructorbus(sc_module_name);

};

#include “bus.h”bus::bus(sc_module_name nm)

: sc_module(nm){}

void bus::write(unsigned addr, int data){

if(addr < 16)rom_port->write(addr, data);

elserqm_port->write(addr, data);

}

void bus::read(unsigned addr, int& data){

if(addr < 16)rom_port->read(addr, data);

elseram_port->read(addr, data);

}

“bus.h”

“bus.cpp”

• www.doulos.com/knowhow/systemc/

• www.asic-world.com/systemc/

• www.systemc.org/

TOOLS

Commercial tool: SOC DesignerWork Space

Cache Profiling window

Waveform Viewer

Memory maps

Assembly code window

Commercial tool: CoWare

Open Source: GreenSoc (not so open)

User IP 1 GreenBus I/F

GreenScript

SystemC

User IP 2

User IP 3

Config User I/F

GreenBus I/F

GreenBus I/F

Config User I/F

Config User I/F

Config PlugIn

GreenAV PlugIn

Specific PlugIn

Gree

nC

on

trol C

ore

GreenAV User I/F

Specific User I/F

ESLTools

SCREAM Lab OpenESL

SCREAM Lab OpenESL

FPGA tool: Berkeley BEE2

FPGA tool: NCKU Multicore

FPGA tool: SMIMS

LAB 1

SystemC環境建構及範例程式運行

安裝說明

• 請參閱doc檔。

• 環境統一使用Linux。

專案說明

• 其中包含三個檔案main.cpp hello_module.hhello_module.cpp

• 可將main.cpp視同電路板，在上面做接線等等的動作。

• hello_module是一個具有process的硬體元件。

Main.cpp

將所需元件的.h檔和systemC.h引入

Sc_main是systemC程式的進入點

宣告一組clk的訊號週期為10ns

宣告一組hello_module的元件

將clk接上module的clk訊號上

開始進行模擬模擬1000ns內的硬體運作

Hello_module.h

宣告一組元件定義hello_module

宣告hello_module的訊號線clk

宣告hello_module的運作函式

hello_module的建構子

整組元件具有process(method) process執行的函式Method_func

Process會經由clk正緣觸發

Hello_module.cpp

運作函式本體

訊號有產生改變才執行

印出模擬時間

印出hello word!

執行結果