Sankula

////////////////////////////////////////////////////////////////////////////////// Copyright (c) 2004 Xilinx, Inc.// All Rights Reserved////////////////////////////////////////////////////////////////////////////////// ____ ____// / /\/ /// /___/ \ / Vendor: Xilinx// \ \ \/ Version: 1.01// \ \ Filename: bbfifo_16x8.v// / / Date Last Modified: 08/04/2004// /___/ /\ Date Created: 10/14/2002// \ \ / \// \___\/\___\////Device: Xilinx//Purpose: // 'Bucket Brigade' FIFO// 16 deep// 8-bit data//Reference:// None//Revision History:// Rev 1.00 - kc - Start of design entry in VHDL, 10/14/2002.// Rev 1.01 - sus - Converted to verilog, 08/04/2004.// Rev 1.02 - njs - Synplicity attributes added, 09/06/2004.// Rev 1.03 - njs - defparam values corrected, 12/01/2005.////////////////////////////////////////////////////////////////////////////////// Contact: e-mail [email protected]////////////////////////////////////////////////////////////////////////////////////// Disclaimer: // LIMITED WARRANTY AND DISCLAIMER. These designs are// provided to you "as is". Xilinx and its licensors make and you// receive no warranties or conditions, express, implied,// statutory or otherwise, and Xilinx specifically disclaims any// implied warranties of merchantability, non-infringement, or// fitness for a particular purpose. Xilinx does not warrant that// the functions contained in these designs will meet your// requirements, or that the operation of these designs will be// uninterrupted or error free, or that defects in the Designs// will be corrected. Furthermore, Xilinx does not warrant or// make any representations regarding use or the results of the// use of the designs in terms of correctness, accuracy,// reliability, or otherwise.//// LIMITATION OF LIABILITY. In no event will Xilinx or its// licensors be liable for any loss of data, lost profits, cost// or procurement of substitute goods or services, or for any// special, incidental, consequential, or indirect damages// arising from the use or operation of the designs or

// accompanying documentation, however caused and on any theory// of liability. This limitation will apply even if Xilinx// has been advised of the possibility of such damage. This// limitation shall apply not-withstanding the failure of the // essential purpose of any limited remedies herein. //////////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1ps

module bbfifo_16x8 (data_in, data_out, reset, write, read, full,

half_full, data_present,

clk);

input [7:0] data_in;output [7:0] data_out;input reset;input write; input read;output full;output half_full;output data_present;input clk;

//////////////////////////////////////////////////////////////////////////////////////// Start of BBFIFO_16x8// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// wires used in BBFIFO_16x8//////////////////////////////////////////////////////////////////////////////////////

wire [3:0] pointer;wire [3:0] next_count;wire [3:0] half_count;wire [2:0] count_carry;

wire pointer_zero;

wire pointer_full;wire decode_data_present;wire data_present_int;wire valid_write;

//////////////////////////////////////////////////////////////////////////////////////// Attributes to define LUT contents during implementation // The information is repeated in the defparams for functional simulation////////////////////////////////////////////////////////////////////////////////////////

// synthesis attribute init of zero_lut is "0001"; // synthesis attribute init of full_lut is "8000"; // synthesis attribute init of dp_lut is "BFA0"; // synthesis attribute init of valid_lut is "C4"; // synthesis attribute init of data_srl_0 is "0000"; // synthesis attribute init of data_srl_1 is "0000"; // synthesis attribute init of data_srl_2 is "0000"; // synthesis attribute init of data_srl_3 is "0000"; // synthesis attribute init of data_srl_4 is "0000"; // synthesis attribute init of data_srl_5 is "0000"; // synthesis attribute init of data_srl_6 is "0000"; // synthesis attribute init of data_srl_7 is "0000"; // synthesis attribute init of count_lut_0 is "6606";// synthesis attribute init of count_lut_1 is "6606";// synthesis attribute init of count_lut_2 is "6606";// synthesis attribute init of count_lut_3 is "6606";

//////////////////////////////////////////////////////////////////////////////////////// Start of BBFIFO_16x8 circuit description//////////////////////////////////////////////////////////////////////////////////////

// SRL16E data storage SRL16E data_srl_0 ( .D(data_in[0]), .CE(valid_write), .CLK(clk), .A0(pointer[0]), .A1(pointer[1]), .A2(pointer[2]), .A3(pointer[3]), .Q(data_out[0]) )/* synthesis xc_props = "INIT=0000"*/;

// synthesis translate_offdefparam data_srl_0.INIT = 16'h0000; // synthesis translate_on

SRL16E data_srl_1 ( .D(data_in[1]), .CE(valid_write), .CLK(clk), .A0(pointer[0]), .A1(pointer[1]), .A2(pointer[2]), .A3(pointer[3]), .Q(data_out[1]) )/* synthesis xc_props = "INIT=0000"*/;








SRL16E data_srl_5

( .D(data_in[5]), .CE(valid_write), .CLK(clk), .A0(pointer[0]), .A1(pointer[1]), .A2(pointer[2]), .A3(pointer[3]), .Q(data_out[5]) )/* synthesis xc_props = "INIT=0000"*/;






// 4-bit counter to act as data pointer // Counter is clock enabled by 'data_present' // Counter will be reset when 'reset' is active // Counter will increment when 'valid_write' is active

FDRE register_bit_0 ( .D(next_count[0]), .Q(pointer[0]), .CE(data_present_int), .R(reset), .C(clk) );

LUT4 count_lut_0 ( .I0(pointer[0]), .I1(read), .I2(pointer_zero),

.I3(write), .O(half_count[0]) )/* synthesis xc_props = "INIT=6606"*/;

// synthesis translate_offdefparam count_lut_0.INIT = 16'h6606; // synthesis translate_on


LUT4 count_lut_1 ( .I0(pointer[1]), .I1(read), .I2(pointer_zero), .I3(write), .O(half_count[1]) )/* synthesis xc_props = "INIT=6606"*/;







// synthesis translate_off

defparam count_lut_3.INIT = 16'h6606; // synthesis translate_on

MUXCY count_muxcy_0 ( .DI(pointer[0]), .CI(valid_write), .S(half_count[0]), .O(count_carry[0]) ); XORCY count_xor_0 ( .LI(half_count[0]), .CI(valid_write), .O(next_count[0]) );

MUXCY count_muxcy_1 ( .DI(pointer[1]), .CI(count_carry[0]), .S(half_count[1]), .O(count_carry[1]) ); XORCY count_xor_1 ( .LI(half_count[1]), .CI(count_carry[0]), .O(next_count[1]) );

MUXCY count_muxcy_2 ( .DI(pointer[2]), .CI(count_carry[1]), .S(half_count[2]), .O(count_carry[2]) ); XORCY count_xor_2 ( .LI(half_count[2]), .CI(count_carry[1]), .O(next_count[2]) );

XORCY count_xor ( .LI(half_count[3]), .CI(count_carry[2]), .O(next_count[3]) );

// Detect when pointer is zero and maximum

LUT4 zero_lut( .I0(pointer[0]),

.I1(pointer[1]), .I2(pointer[2]), .I3(pointer[3]), .O(pointer_zero ) )/* synthesis xc_props = "INIT=0001"*/;

// synthesis translate_offdefparam zero_lut.INIT = 16'h0001; // synthesis translate_on

LUT4 full_lut

( .I0(pointer[0]), .I1(pointer[1]), .I2(pointer[2]), .I3(pointer[3]), .O(pointer_full ) )/* synthesis xc_props = "INIT=8000"*/;

// synthesis translate_offdefparam full_lut.INIT = 16'h8000; // synthesis translate_on

// Data Present status

LUT4 dp_lut ( .I0(write), .I1(read), .I2(pointer_zero), .I3(data_present_int), .O(decode_data_present ) )/* synthesis xc_props = "INIT=BFA0"*/;

// synthesis translate_offdefparam dp_lut.INIT = 16'hBFA0; // synthesis translate_on

FDR dp_flop( .D(decode_data_present),

.Q(data_present_int), .R(reset), .C(clk) );

// Valid write wire

LUT3 valid_lut ( .I0(pointer_full), .I1(write), .I2(read), .O(valid_write ) )/* synthesis xc_props = "INIT=C4"*/;

// synthesis translate_offdefparam valid_lut.INIT = 8'hC4; // synthesis translate_on

// assign internal wires to outputs

assign full = pointer_full; assign half_full = pointer[3];

assign data_present = data_present_int;

endmodule

//////////////////////////////////////////////////////////////////////////////////////// END OF FILE BBFIFO_16x8.V//

////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////// Copyright (c) 2004 Xilinx, Inc.// All Rights Reserved////////////////////////////////////////////////////////////////////////////////// ____ ____// / /\/ /// /___/ \ / Vendor: Xilinx// \ \ \/ Version: 1.03// \ \ Filename: kcuart_tx.v// / / Date Last Modified: November 2, 2004// /___/ /\ Date Created: October 14, 2002// \ \ / \// \___\/\___\////Device: Xilinx//Purpose: // Constant (K) Compact UART Transmitter//Reference:// None//Revision History:// Rev 1.00 - kc - Start of design entry in VHDL, October 14, 2002// Rev 1.01 - sus - Converted to verilog, August 4, 2004// Rev 1.02 - njs - Synplicity attributes added, September 6, 2004// Rev 1.03 - njs - Fixed simulation attributes from string to hex, // November 2, 2004////////////////////////////////////////////////////////////////////////////////// // Contact: e-mail [email protected]////////////////////////////////////////////////////////////////////////////////////// Disclaimer: // LIMITED WARRANTY AND DISCLAIMER. These designs are// provided to you "as is". Xilinx and its licensors make and you// receive no warranties or conditions, express, implied,// statutory or otherwise, and Xilinx specifically disclaims any// implied warranties of merchantability, non-infringement, or// fitness for a particular purpose. Xilinx does not warrant that// the functions contained in these designs will meet your// requirements, or that the operation of these designs will be// uninterrupted or error free, or that defects in the Designs// will be corrected. Furthermore, Xilinx does not warrant or// make any representations regarding use or the results of the// use of the designs in terms of correctness, accuracy,// reliability, or otherwise.//// LIMITATION OF LIABILITY. In no event will Xilinx or its// licensors be liable for any loss of data, lost profits, cost// or procurement of substitute goods or services, or for any

// special, incidental, consequential, or indirect damages// arising from the use or operation of the designs or// accompanying documentation, however caused and on any theory// of liability. This limitation will apply even if Xilinx// has been advised of the possibility of such damage. This// limitation shall apply not-withstanding the failure of the // essential purpose of any limited remedies herein. //////////////////////////////////////////////////////////////////////////////////


module kcuart_tx (data_in, send_character, en_16_x_baud, serial_out, Tx_complete, clk);

input [7:0] data_in;input send_character;input en_16_x_baud;output serial_out;output Tx_complete;input clk;

////////////////////////////////////////////////////////////////////////////////////////// Start of KCUART_TX// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// wires used in KCUART_TX////////////////////////////////////////////////////////////////////////////////////////wire data_01;wire data_23;wire data_45;wire data_67;wire data_0123;wire data_4567;wire data_01234567;wire [2:0] bit_select;wire [2:0] next_count;

wire [2:0] mask_count;wire [2:0] mask_count_carry;wire [2:0] count_carry;wire ready_to_start;wire decode_Tx_start;wire Tx_start;wire decode_Tx_run;wire Tx_run;wire decode_hot_state;wire hot_state;wire hot_delay;wire Tx_bit;wire decode_Tx_stop;wire Tx_stop;wire decode_Tx_complete;//////////////////////////////////////////////////////////////////////////////////////////// Attributes to define LUT contents during implementation // The information is repeated in the generic map for functional simulation////////////////////////////////////////////////////////////////////////////////////////

// synthesis attribute init of mux1_lut is "E4FF"; // synthesis attribute init of mux2_lut is "E4FF";// synthesis attribute init of mux3_lut is "E4FF";// synthesis attribute init of mux4_lut is "E4FF";// synthesis attribute init of ready_lut is "10";// synthesis attribute init of start_lut is "0190";// synthesis attribute init of run_lut is "1540";// synthesis attribute init of hot_state_lut is "94";// synthesis attribute init of delay14_srl is "0000";// synthesis attribute init of stop_lut is "0180";// synthesis attribute init of complete_lut is "8";// synthesis attribute init of count_lut_0 is "8";// synthesis attribute init of count_lut_1 is "8";// synthesis attribute init of count_lut_2 is "8";

////////////////////////////////////////////////////////////////////////////////////////// Start of KCUART_TX circuit description////////////////////////////////////////////////////////////////////////////////////////

// 8 to 1 multiplexer to convert parallel data to serial

LUT4 mux1_lut ( .I0(bit_select[0]), .I1(data_in[0]), .I2(data_in[1]), .I3(Tx_run), .O(data_01) )/* synthesis xc_props = "INIT=E4FF"*/;

// synthesis translate_offdefparam mux1_lut.INIT = 16'hE4FF; // synthesis translate_on

LUT4 mux2_lut ( .I0(bit_select[0]), .I1(data_in[2]), .I2(data_in[3]), .I3(Tx_run), .O(data_23) )/* synthesis xc_props = "INIT=E4FF"*/;


LUT4 mux3_lut (.I0(bit_select[0]), .I1(data_in[4]), .I2(data_in[5]), .I3(Tx_run), .O(data_45) )/* synthesis xc_props = "INIT=E4FF"*/;


LUT4 mux4_lut (.I0(bit_select[0]), .I1(data_in[6]), .I2(data_in[7]), .I3(Tx_run), .O(data_67) )/* synthesis xc_props = "INIT=E4FF"*/;


MUXF5 mux5_muxf5 ( .I1(data_23), .I0(data_01), .S(bit_select[1]), .O(data_0123) );

MUXF5 mux6_muxf5 ( .I1(data_67), .I0(data_45), .S(bit_select[1]), .O(data_4567) );

MUXF6 mux7_muxf6 ( .I1(data_4567),

.I0(data_0123), .S(bit_select[2]), .O(data_01234567) );

// Register serial output and force start and stop bits

FDRS pipeline_serial ( .D(data_01234567), .Q(serial_out), .R(Tx_start), .S(Tx_stop), .C(clk) ) ;

// 3-bit counter // Counter is clock enabled by en_16_x_baud // Counter will be reset when 'Tx_start' is active // Counter will increment when Tx_bit is active // Tx_run must be active to count // count_carry[2] indicates when terminal count [7] is reached and Tx_bit=1 (ie overflow)

FDRE register_bit_0 (.D(next_count[0]), .Q(bit_select[0]), .CE(en_16_x_baud), .R(Tx_start), .C(clk) );

LUT2 count_lut_0 (.I0(bit_select[0]), .I1(Tx_run), .O(mask_count[0]) )/* synthesis xc_props = "INIT=8"*/;


MULT_AND mask_and_0 (.I0(bit_select[0]), .I1(Tx_run), .LO(mask_count_carry[0]) );

MUXCY count_muxcy_0 ( .DI(mask_count_carry[0]), .CI(Tx_bit), .S(mask_count[0]), .O(count_carry[0]) );

XORCY count_xor_0 (.LI(mask_count[0]), .CI(Tx_bit), .O(next_count[0]) );

FDRE register_bit_1 (.D(next_count[1]),

.Q(bit_select[1]), .CE(en_16_x_baud), .R(Tx_start), .C(clk) );

LUT2 count_lut_1 (.I0(bit_select[1]), .I1(Tx_run), .O(mask_count[1]) )/* synthesis xc_props = "INIT=8"*/;


MULT_AND mask_and_1 ( .I0(bit_select[1]), .I1(Tx_run), .LO(mask_count_carry[1]) );

MUXCY count_muxcy_1 ( .DI(mask_count_carry[1]), .CI(count_carry[0]), .S(mask_count[1]), .O(count_carry[1]) );

XORCY count_xor_1 ( .LI(mask_count[1]), .CI(count_carry[0]), .O(next_count[1]) );

FDRE register_bit_2 ( .D(next_count[2]), .Q(bit_select[2]), .CE(en_16_x_baud), .R(Tx_start), .C(clk) );

LUT2 count_lut_2 ( .I0(bit_select[2]), .I1(Tx_run), .O(mask_count[2]) )/* synthesis xc_props = "INIT=8"*/;


MULT_AND mask_and_2 ( .I0(bit_select[2]), .I1(Tx_run), .LO(mask_count_carry[2]) );

MUXCY count_muxcy_2 ( .DI(mask_count_carry[2]), .CI(count_carry[1]), .S(mask_count[2]) ,

.O(count_carry[2]) );

XORCY count_xor_2( .LI(mask_count[2]),

.CI(count_carry[1]), .O(next_count[2]) );

// Ready to start decode

LUT3 ready_lut ( .I0(Tx_run), .I1(Tx_start), .I2(send_character), .O(ready_to_start ) )/* synthesis xc_props = "INIT=10"*/;

// synthesis translate_offdefparam ready_lut.INIT = 8'h10; // synthesis translate_on

// Start bit enable

LUT4 start_lut ( .I0(Tx_bit), .I1(Tx_stop), .I2(ready_to_start), .I3(Tx_start), .O(decode_Tx_start ) )/* synthesis xc_props = "INIT=0190"*/;

// synthesis translate_offdefparam start_lut.INIT = 16'h0190; // synthesis translate_on

FDE Tx_start_reg ( .D(decode_Tx_start), .Q(Tx_start), .CE(en_16_x_baud), .C(clk) );

// Run bit enable LUT4 run_lut ( .I0(count_carry[2]), .I1(Tx_bit), .I2(Tx_start), .I3(Tx_run),

.O(decode_Tx_run ) )/* synthesis xc_props = "INIT=1540"*/;// synthesis translate_offdefparam run_lut.INIT = 16'h1540; // synthesis translate_on

FDE Tx_run_reg ( .D(decode_Tx_run), .Q(Tx_run), .CE(en_16_x_baud), .C(clk) );

// Bit rate enable

LUT3 hot_state_lut ( .I0(Tx_stop), .I1(ready_to_start), .I2(Tx_bit), .O(decode_hot_state) )/* synthesis xc_props = "INIT=94"*/;

// synthesis translate_offdefparam hot_state_lut.INIT = 8'h94; // synthesis translate_on

FDE hot_state_reg ( .D(decode_hot_state), .Q(hot_state), .CE(en_16_x_baud), .C(clk) );

SRL16E delay14_srl ( .D(hot_state), .CE(en_16_x_baud), .CLK(clk), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b1), .Q(hot_delay) )/* synthesis xc_props = "INIT=0000"*/;

// synthesis translate_offdefparam delay14_srl.INIT = 16'h0000; // synthesis translate_on

FDE Tx_bit_reg ( .D(hot_delay), .Q(Tx_bit), .CE(en_16_x_baud), .C(clk) );

// Stop bit enable LUT4 stop_lut ( .I0(Tx_bit), .I1(Tx_run), .I2(count_carry[2]), .I3(Tx_stop), .O(decode_Tx_stop) )/* synthesis xc_props = "INIT=0180"*/;

// synthesis translate_offdefparam stop_lut.INIT = 16'h0180; // synthesis translate_on

FDE Tx_stop_reg ( .D(decode_Tx_stop), .Q(Tx_stop), .CE(en_16_x_baud), .C(clk) );

// Tx_complete strobe

LUT2 complete_lut ( .I0(count_carry[2]), .I1(en_16_x_baud), .O(decode_Tx_complete) )/* synthesis xc_props = "INIT=8"*/;

// synthesis translate_offdefparam complete_lut.INIT = 4'h8; // synthesis translate_on

FD Tx_complete_reg ( .D(decode_Tx_complete), .Q(Tx_complete), .C(clk) );

endmodule

//////////////////////////////////////////////////////////////////////////////////////// END OF FILE KCUART_TX.V//////////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: // Design Name: // Module Name: top_uart_tx// Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// // date: 02/06/2015// Additional Comments: // baud rate: 9600 b/s// start bit: 1-bit// stop bit : 1-bit// parity bit: No parity bit// data bits : 8// External clock: 50MHz// description:// hard coded data is given to uart transmitter module.// tested on smart-track board,results are fine.

//08.06.15: To this RTL we added UART RX & TX IP Cores of SPARTAN-6// It is tested on TDR board & found OK.////01.07.15: The seperate uart tx rx loop is proven on board/TDR.// data is given from the hyper terminal of pc & again seen back on the hyper terminal.:// 020715 : to be proven on Smart track board //// 08-07-15: wr_en <= 1'b1; it is "1" -- during the entire WRITE period ,// On hyperterminal we are able to see the 10 bytes which are hardcoded inside FPGA // ready - used for test purpose.// FSM is used to send hardcoded 10 bytes to hyperterminal -- used for testing// Right now not checked for tx_buffer_full signal /////////////////////////////////////////////////////////////////////////////////////////////module top_uart_tx( input clk, input rst_n,

input ready, // for testing purpose only

//ops output en_16_x_baud, output tx );

wire serial_out,rst_p,buffer_full;

assign rst_p = ~rst_n; // check this ??

reg [7:0]data_in;reg wr_en;

// -- for testing ONLY ---posedge detect of readyreg switch_in_reg, switch_in_reg_dly;

always @ (posedge rst_p or posedge clk) begin

if(rst_p) begin

switch_in_reg <= 0;switch_in_reg_dly <= 0;

endelse begin

switch_in_reg <= ready;switch_in_reg_dly <= switch_in_reg;

endend

assign pos_out = switch_in_reg & !switch_in_reg_dly;

//////////////////////////////////////

parameter idle = 11'b00000000001;parameter byte1_write = 11'b00000000010;parameter byte2_write = 11'b00000000100;parameter byte3_write = 11'b00000001000;parameter byte4_write = 11'b00000010000;parameter byte5_write = 11'b00000100000;parameter byte6_write = 11'b00001000000;parameter byte7_write = 11'b00010000000;parameter byte8_write = 11'b00100000000;parameter byte9_write = 11'b01000000000;parameter byte10_write = 11'b10000000000;

(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [10:0] state = idle;

always@(posedge clk) if (rst_p) begin state <= idle;

data_in <= 8'b0; wr_en <= 1'b0;

end else

begin (* PARALLEL_CASE *) case (state) idle: begin

wr_en <= 1'b0;

if (pos_out)begin state <= byte1_write;

end else

state <= idle;end

byte1_write : begin

data_in <= 8'h 21;wr_en <= 1'b1;

state <= byte2_write; end

byte2_write : begindata_in <= 8'h 23;wr_en <= 1'b1;












byte8_write : begindata_in <= 8'h47;wr_en <= 1'b1;



state <= byte10_write;end


state <= idle; end

default: begin // Fault Recovery state <= idle;

wr_en <= 0;end

endcaseend

// reg [3:0]enable_count;reg [11:0]enable_pulse_counter;reg enable_pulse_signal;

wire [7:0]data_out_signal;

// uart transmitter Codes//en_16_x_baud pulse generation

always@(posedge clk)begin

if (rst_p)begin

enable_pulse_signal <= 1'b0;enable_pulse_counter <= 12'b0;

end

else begin

if (enable_pulse_counter == 12'd325)begin

enable_pulse_signal <= 1'b1;enable_pulse_counter <= 12'b0;

endelse beginenable_pulse_counter <= enable_pulse_counter + 1;enable_pulse_signal <= 1'b0;end

endend

assign en_16_x_baud = enable_pulse_signal;

// Instantiate the moduleuart_tx u1 ( .clk(clk), .data_in(data_in), .write_buffer(wr_en), .reset_buffer(rst_p), .en_16_x_baud(en_16_x_baud), //

// ops .serial_out(serial_out), // thru tx .buffer_half_full(tx_buffer_half_full), .buffer_full(tx_buffer_full) );

assign tx = serial_out;

endmodule

////////////////////////////////////////////////////////////////////////////////// Copyright (c) 2004 Xilinx, Inc.// All Rights Reserved////////////////////////////////////////////////////////////////////////////////

// ____ ____// / /\/ /// /___/ \ / Vendor: Xilinx// \ \ \/ Version: 1.01// \ \ Filename: uart_tx.v// / / Date Last Modified: 08/04/2004// /___/ /\ Date Created: 10/14/2002// \ \ / \// \___\/\___\////Device: Xilinx//Purpose: // UART Transmitter with integral 16 byte FIFO buffer// 8 bit, no parity, 1 stop bit//Reference:// None//Revision History:// Rev 1.00 - kc - Start of design entry in VHDL, 10/14/2002.// Rev 1.01 - sus - Converted to verilog, 08/04/2004.////////////////////////////////////////////////////////////////////////////////// Contact: e-mail [email protected]////////////////////////////////////////////////////////////////////////////////////// Disclaimer: // LIMITED WARRANTY AND DISCLAIMER. These designs are// provided to you "as is". Xilinx and its licensors make and you// receive no warranties or conditions, express, implied,// statutory or otherwise, and Xilinx specifically disclaims any// implied warranties of merchantability, non-infringement, or// fitness for a particular purpose. Xilinx does not warrant that// the functions contained in these designs will meet your// requirements, or that the operation of these designs will be// uninterrupted or error free, or that defects in the Designs// will be corrected. Furthermore, Xilinx does not warrant or// make any representations regarding use or the results of the// use of the designs in terms of correctness, accuracy,// reliability, or otherwise.//// LIMITATION OF LIABILITY. In no event will Xilinx or its// licensors be liable for any loss of data, lost profits, cost// or procurement of substitute goods or services, or for any// special, incidental, consequential, or indirect damages// arising from the use or operation of the designs or// accompanying documentation, however caused and on any theory// of liability. This limitation will apply even if Xilinx// has been advised of the possibility of such damage. This// limitation shall apply not-withstanding the failure of the // essential purpose of any limited remedies herein. //////////////////////////////////////////////////////////////////////////////////


module uart_tx( data_in,

write_buffer,reset_buffer,en_16_x_baud,serial_out,buffer_full,buffer_half_full,clk);

input[7:0] data_in;input write_buffer;input reset_buffer;input en_16_x_baud;output serial_out;output buffer_full;output buffer_half_full;input clk;

wire [7:0] data_in;wire write_buffer;wire reset_buffer;wire en_16_x_baud;wire serial_out;wire buffer_full;wire buffer_half_full;wire clk;

//----------------------------------------------------------------------------------//// Start of UART_TX// ////----------------------------------------------------------------------------------//// Signals used in UART_TX////----------------------------------------------------------------------------------//wire [7:0] fifo_data_out;wire fifo_data_present;wire fifo_read;////----------------------------------------------------------------------------------//// Start of UART_TX circuit description////----------------------------------------------------------------------------------

//

// 8 to 1 multiplexer to convert parallel data to serialkcuart_tx kcuart( .data_in(fifo_data_out), .send_character(fifo_data_present), .en_16_x_baud(en_16_x_baud), .serial_out(serial_out), .Tx_complete(fifo_read), .clk(clk));

bbfifo_16x8 buf_0( .data_in(data_in), .data_out(fifo_data_out), .reset(reset_buffer), .write(write_buffer), .read(fifo_read), .full(buffer_full), .half_full(buffer_half_full), .data_present(fifo_data_present), .clk(clk));

endmodule

//----------------------------------------------------------------------------------//// END OF FILE UART_TX.V////----------------------------------------------------------------------------------

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date: 18:40:48 07/07/2015// Design Name: uart_rx// Module Name: E:/Demo_2/uart_rx/TB/tb_uart_txrx_module.v// Project Name: uart_rx// Target Device: // Tool versions: // Description: //// Verilog Test Fixture created by ISE for module: uart_txrx_module//// Dependencies:// // Revision:// Revision 0.01 - File Created

// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////

module tb_uart_txrx_module;

// Inputsreg tb_clk;reg tb_rst_n;reg tb_ready;

// Outputswire tb_en_16_x_baud;wire tb_tx;

// Instantiate the Unit Under Test (UUT)top_uart_tx uut (

.clk(tb_clk),

.rst_n(tb_rst_n),

.ready(tb_ready),

.en_16_x_baud(tb_en_16_x_baud),

.tx(tb_tx));

always #10 tb_clk = !tb_clk;

initial begin// Initialize Inputstb_clk = 0;tb_rst_n = 0;tb_ready = 0;// Wait 100 ns for global reset to finish#100;tb_rst_n = 1;

// Add stimulus here#120;@(negedge tb_clk) tb_ready = 1;@(negedge tb_clk) tb_ready = 0;

end

endmodule

##################################################################################### Project - smart tracker# Module - led_testig# Date - 15/05/15# ucf file - led_testig_ucf####################################################################################

# i/p's

NET "clk" LOC = A8;NET "rst_n" LOC = B14;NET "ready" LOC = C2;//NET "rx" LOC = D3;

# o/p'sNET "tx" LOC = E3;NET "en_16_x_baud" LOC = D14;//NET "rx_buffer_data_present" LOC = F13;

#NET "rx_data_out[7]" LOC = R1;#NET "rx_data_out[6]" LOC = P1;#NET "rx_data_out[5]" LOC = N1;#NET "rx_data_out[4]" LOC = M1;#NET "rx_data_out[3]" LOC = F1;#NET "rx_data_out[2]" LOC = E1;#NET "rx_data_out[1]" LOC = D1;#NET "rx_data_out[0]" LOC = C1;