中国国际半导体技术大会 2009 Distinguished China …server.semiconchina.org/downloadFile/1286860792406.pdf · 大会包括主题演讲及九个技术分会,由业界

ISTC/CSTIC 2009 March 19-20, 2009 Shanghai, China

Dr. J. Georg Bednorz Dr. Robert Chau Prof. Gilbert Declerck Mr. Ray RobergeNobel Laureate, IBM Fellow Intel Senior Fellow CEO, IMEC CTO, Praxair Inc.

Organizers:

Co-organizer: China's High-Tech Expert Committee (CHTEC)

Co-sponsors:

2009 Distinguished Conference Keynote Speakers

中国国际半导体技术研讨会(ISTC/CSTIC)旨在打造世界级半导体产业技术会

议。大会包括主题演讲及九个技术分会,由业界领袖和技术精英担纲演讲300

多篇顶尖技术论文，内容涵盖半导体制造工艺的整个流程。

● Design and Device Engineering● Metrology, Reliability and Testing● New Materials and Process Integration● Photolithography● CMP and Cleaning● Thin Film, Etch and Plating● Packaging Technology● Emerging Semiconductor Technologies● Silicon Technology for Semiconductor, Electronic, and Solar Applications

立刻上网登记，以确保您的听课席

位并获取精美礼品

http://semiconchina.semi.org/cistc

中国国际半导体技术研讨会

http://semiconchina.semi.org/cistchttp://semiconchina.semi.org/cistc

联系人：曹明霞

电话：021-50270909-258邮箱：[email protected]

The largest annual semiconductor industry technology conference in China

中国国际半导体技术大会

CSTIC

China Semiconductor Technology International Conference

March 18-19, 2010,

Plaza Royale Oriental Shanghai, Shanghai, China上海兴荣豪廷大酒店(浦东大道2288号)

http://semiconchina.semi.org/cstic

March 18-19, 2010 Plaza Royale Oriental Shanghai, Shanghai, China http://semiconchina.semi.org/cstic

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中国国际半导体技术大会CSTIC

Welcome to China Semiconductor Technology International Conference (CSTIC)

2010, the largest annual technology conferences for semiconductor industry in China.

CSTIC 2010 will be held on March 18-19, 2010 in Shanghai, China, in conjunction

with SEMICON China 2010. It will cover all the aspects of semiconductor technology

and manufacturing, including devices, design, lithography, integration, materials,

processes, manufacturing as well as emerging semiconductor technologies and

silicon material applications. Hot topics like PV, III-V semiconductors and MEMS will

also be included in the conference.

CSTIC 2010 will be one the best platforms for technical staffs from industry and

academia around the world to have face-to-face communications about the latest

innovations, technologies and industry solutions. It is also a platform to explore

business and collaboration opportunities in China.

中国国际半导体技术大会（CSTIC）是世界水平的半导体技术大会，CSTIC 2010将汇聚

数百名全球知名半导体与光伏等领域的技术专家同台演讲，9场技术分会共收到超过340

篇投稿，一场国际水准的技术盛宴期待您的参与！

Who Should Attend 适合参会人员Chief Technology OfficersFab ManagersProcess EngineersProduct ManagersTechnical ExpertsProfessors and Researchers

Date and Venue 时间地点March 18-19, 2010

Plaza Royale Oriental Shanghai, Shanghai, China

上海兴荣豪廷大酒店 (浦东大道2288号)

中国国际半导体技术大会China Semiconductor Technology International Conference


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Plenary Session9:00 - 12:00 March 18, 2010 —— Thursday

Some Conference Keynote and Invited Speakers

Symposium I: Design and Device EngineeringRich Liu Macronix International

Charge trapping devices for future NAND flash memories

Huiming Bu IBM Advanced device beyond 32nm technology

Subramanian S. Iyer IBM

Three Dimensional Integration for Memory Applications

Minhwa Chi SMIC CMOS Technologies toward Green

Hsing-Huang Tseng Texas State University High-K/metal gate

Cor Claeys IMEC

Impact of radiation on the operation and reliability of deep submicron CMOS

Symposium II: Metrology，Reliability and Testing J. V. Martinex de Pinillos National Institutes of Standards and Technology, USA

Yervant Zorian Virage Logic Corp. USA

Dr. Xiaoqing Wen Kyushu Institute of Technology, Japan

Benjamin Bunday International Sematech Manufacturing Initiative

Richard J. Matyi National Institute of Standards and Technology, USA

Wen-li Wu NIST, USA

Symposium III: Materials and Process Integration for Device and Interconnection Stefan Lai Being Advanced Memory

Future Trend and Opportunities of Non-Volatile Memory

David B. Graves UC-Berkeley

Pushing the Limits of Plasma Etch to the Nanoscale

Jingang Wu SMIC Different Interface Role in CuOx Based RRAM

Supratik Guha IBM Materials Science at the Nanometer Scale in High-k

Oxides Technology for Silicon Technology

XiuFeng Han Institute of Physics, Chinese Academy of Sciences

Inserted ultrathin Co, Cr and Mg layers effect in single crystal Fe/MgO/Fe

magnetic tunnel junctions for developing MRAM technologies

Symposium IV: Patterning and LithographyBurn J.Lin TSMC

Making a Decision on a Manufacturing Technology for 32-nm Half-Pitch Nodes

Yan Borodovsky Intel Complementary Patterning - Viability and Gaps

Andreas Erdmann Fraunhofer IISB Mask and Wafer Topography Effects in

Optical and EUV-Lithography

Tracy Weed Synopsys OPC

Banqiu Wu Applied Materials EUV lithography: coming with many challenges

Yalin Xiong KLA-Tencor

Lithography Simulation in Mask Inspection and Defect Dispositioning

Symposium V: CMP and Post-CMP Cleaning Duane Boning MIT CMP Mechanisms and Models: Progress and Challenges

Chris Yu Anji Microelectronics

Feng Chen SMIC CMP Mechanisms and Models: Progress and Challenges

Lee Cook Dow Electronic Materials

Scaling of Critical Wiring and Implications for Barrier CMP

Yuchun Wang Applied Materials CMP process technology in TSV application

Leonard Borucki Araca Incorporated The Nature of Large Contact Areas in

Chemical-Mechanical Planarization

David Yin ATMI High Productivity Combinatorial Analysis of Cu Post-CMP

Cleans: Copper Corrosion Protection and Queue Time

Symposium VI: Thin Film, Etch & PlatingYue Kuo Texas A&M University

ULSI vs. TFT Technologies - from Nano to Giga Electronics

Roy G. Gordon Harvard University

Vapor Deposition of Materials for Microelectronics

Sven Van Elshocht IMEC

On the process and material sensitivities for high-k based dielectrics

Larry Zhao Intel A Novel Test Structure for Barrier/Low-k Development

Jon Reid Novellus Cu Electrodeposition for 22nm Damascene Structures

Tom Ni AMEC

Yulong Jiang Fudan University

Modulation and extraction of Schottky barrier height for advanced source/drain

contact

Symposium VII: Packaging and AssemblyJohn Knickerbocker IBM System on Package & 3D Integration

Michael Todd Henkel Materials Roadmap to Support The Packaging Trend

Robert Lo ITRI Commercialization of 3D IC

William Chen IEEE CPMT

The Critical Role of Packaging in the Overall Semiconductor Value Chain

Symposium VIII: Emerging Semiconductor TechnologiesRoy G. Gordon Harvard University CVD of Self-Aligned Contacts,

Barriers, Adhesion and Seed Layers

Chung H. Lam IBM Phase Change Memory: Opportunities and Challenges

George Bourianoff Intel Post Si CMOS

Bo Shen Peking University

MOCVD growth of GaN-based heterostructures and the 2DEG transport/spin

properties

Do Y. Yoon Seoul National University

Microstructure and Applications of Organosilicate Polymers for Nanoelectronics

and Optoelectronics

Christine Ouyang IBM Fully Depleted SOI Devices for 15nm and beyond

Symposium IX: Silicon Technology for Electronic and Photovoltaic ApplicationsHenry F. Erk MEMC

Wet Etching Technology for Semiconductor and Solar Silicon Manufacturing

Wang Xi Shanghai Simgui Industrial SOI technology by ion implantation

Frank J. Bottari BTU International

Advances in Inline Diffusion Processes for the Manufacture of Crystalline Silicon

Solar Cells

Robert L Rhoades Entrepix Polishing of Semiconductor Materials

Ichiro Yonenaga Tohoku University

Dislocation control through interactions with impurities in Si

Michel Frei Applied Materials

End-to-end Modeling for Thin-Film Silicon Photovoltaics

2010 Distinguished Conference Keynote Speakers

Dr. Simon YangSenior Vice President, Chartered

Dr. Zhengrong ShiChairman and CEO, Suntech

Dr. T.P. MaDirector of Yale Center for Microelectronics, Yale University

Dr. Stuart S.P. ParkinIBM Fellow


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Conference Agenda 会议日程

** Keynote * Invited


Symposium Chairs:Ru Huang Peking University, China.Cor Claeys IMEC, BelgiumShaoning Mei HHNEC, ChinaBoyong He CSMC, ChinaHong Wu SST, ChinaHuiling Shang IBM, USA

Thursday, March 18

Session I: Memory Technology

13:15-13:20Chairman Remarks

13:20-13:50** Charge Trapping Devices for Future NAND Flash MemoriesRich Liu, Macronix International

13:50-14:15* 3D Technology for Memory ApplicationSubramanian S. Iyer, IBM

14:15-14:40*RRAM Device for High Performance and High Density ApplicationsMinjin Tsai , ITRI

14:40-14:55Forming-less Unipolar TaOx-based RRAM with Large CC-independence Range for High Density Memory ApplicationLijie Zhang, Peking University

14:55-15:15Coffee Break

Session II: Device and Process Design-1

15:15-15:40* Hole/electron Transport in (110) MOSFETsKen Uchida, Tokyo Institute of Technology

15:40-16:05* Nano CMOS DevicesJong-ho Lee, Kyungpook National University

16:05-16:20Calculating Electrical Current Densities of MOS Transistors Under Process Variations at Sub-100nm TechnologiesLifu Chang, Semiconductor Manufacturing International Corporation

16:20-16:35Process Simulation and Experimental Study of Stress Memorization in Strained Silicon nMOSFETsWong Kin Shun Terence, Nanyang Technological University

1Symposium I: Design and Device Engineering

16:35-16:50Investigations of Different Strain Configurations in Gate-All-Around Silicon Nanowire TransistorQuanxin Yun, Peking University, China

16:50-17:05Review on Methods for Trench MOSFET Gate Oxide Reliability and Switching Speed ImprovementNG HONG SENG, X-FAB SARAWAK SDN BHD

Friday, March 19

Session III: Advanced CMOS Technology-1

8:30-9:00** Advanced Device Beyond 32nm TechnologyHuiming Bu, IBM, USA

9:00-9:25 * CMOS Technologies toward GreenMinhwa Chi, SMIC, China

9:25-9:40A Novel Regular Layout Style Using the Matching Design Rule for 65-nanometer Standard Cell LibraryJosh Yang, SMIC(Shanghai),China

9:40-9:55 Threshold Voltage Increasing Induced by Gate Poly Silicon Counter pre-doping in NMOSFETJinhua Liu, SMIC(Beijing), China

9:55-10:15 Coffee Break

Session IV: Advanced CMOS Technology-2

10:15-10:40* Impact of Radiation on the Operation and Reliability of Deep Submicron CMOSCor Claeys , IMEC

10:40-11:05* Junction TechnologyBunji MIZUNO, UJT LAB, Panasonic, Japan

11:05-11:20Drive Current Improvements for NMOS Narrow Width Devices Through STI Process and INDIUM ImplatationZhaoxu Shen, SMIC, China

11:20-11:35The Combined Impact of Total Ionizing Dose Effect and Negative Bias Temperature Stress on Deep Sub-Micron pMOSFETsJian Wang, Institute of Microelectronics, Peking University


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111:35-11:50 Fluorine Implantation Effect on Negative Bias Temperature Instability and Process Induced DefectsAllan Zhou, SMIC, China

11:50-13:15Lunch

Session V: Device and Process Design-2

13:15-13:40 * Outlook of Nonvolatile Memories: New Applications and Technology BenchmarksEdwin Chihchuan Kan, Cornell University

13:40-14:05 * High-K/Metal GateHsing-Huang TSENG , Texas State University

14:05-14:20 Formation of Cobalt Nanodots Embedded in Silicon Oxide for Nonvolatile Memory ApplicationYanli Pei, Tohoku University, Japan

14:20-14:35 An Accurate Physical Analytical Model of Planar Spiral Inductor on SOI SubstrateDawei He, Shanghai Institute of Microsystem & Information and Technology


Session VI: Novel Devices and Power Devices

14:50-15:05 AlGaN/GaN Heterostructure HEMT Simulation with Density Functional TheoryYiqing Hu , Wide-band group, institute of microelectronics,Peking Univ.

15:05-15:20 Fabrication and Characterization of Polycrystalline SiC Comb ResonatorsNing Jin, Institute of Semiconductors, Chinese Academy of Sciences

15:20-15:35 Fabrication of Polysilicon-based Clamped-clamped FilterYongmei Zhao, Institute of Semiconductors, Chinese Academy of Sciences

15:35-15:50 Design and Fabrication Using Hot Embossing Lithography of a Microfluidic Chip for Microsphere Single-pass ApplicationsHuaibo Qu, College of Information Engineering, Hebei University of Technology

15:50-16:05 Comparison of High Voltage (200-300 Volts) Devices for Power Integrated CircuitsGene Sheu, Asia University

16:05-16:20 Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETsZhu Congyi, Tsinghua University

16:20-16:35 Reduced Kink Effect in SOI LDMOS Structure with Graded Drift Region ThicknessGene Sheu, Asia University

16:35-16:50 Analysis and Optimization of High-Voltage Devices in a BCD ProcessChunxiao Fu, Shanghai Research Institute of Microelectronics, Peking University

16:50-17:05 Combining 2D and 3D Device Simulations for Optimizing LDMOS DesignChin-Che Lin, Asia University


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Symposium II: Metrology, Reliability and Testing

Symposium Chairs:Peilin Song IBM, USA.Bin Wang Spansion, ChinaWen-li Wu NIST, USAYuhua Cheng Peking University, ChinaFrancis Jen KLA-Tencor, ChinaKelvin Xia Verigy, ChinaSrinivas Raghvendra SynopsysXiaowei Li Institute of Computing Technology, Chinese Academy of Sciences

Thursday, March 18

Session I: Metrology

13:00-13:05 Chairman Remarks

13:05-13:35 ** TBDDr. J. V. Martinex de Pinillos, National Institutes of Standards and Technology, USA

13:35-14:00 * TBDDr. Benjamin Bunday, International Sematech Manufacturing Initiative

14:00-14:20 Characterization of Oxidation Induced Substrate LossGary Ditmer, Liam Cunnane, Metryx Ltd.

14:20-14:40 Grazing Incident X-ray Scattering/Reflectivity for Characterizing Nano-patterns on Flat SubstrateWen-li Wu, NIST, USA

14:40-15:00 Outlier Detection to Assure Good Quality for Metrology Bias Acceptance TestSiyuan Frank Yang, SMIC


Session II: Metrology, DFM and Design

15:20-15:45 *TBDDr. Richard J. Matyi, International Sematech Manufacturing Initiative (ISMI)

15:45-16:05 Nanoscale Non-Destruct ive Semiconductor Dopant Characterization and Failure AnalysisHassan Tanbakuchi, Agilent Technologies, USA

16:05-16:25 Modeling of Variability in Geometric Parameters of MOSFETs for DFM ApplicationsDanqing Liu, Shanghai Research Institute of Microelectronics (SHRIME), Peking University

16:25-16:45 Wafer-area-saving Test Structures and Measurement Method for the Characterization of Interconnect Resistance and Capacitance in Nanometer CMOS TechnologiesXiaojing Qin, Shanghai Research Institute of Microelectronics (SHRIME), Peking University

16:45-17:05 Design and Optimization of Power Devices in a BCD ProcessFan Xu, Shanghai Research Institute of Microelectronics (SHRIME), Peking University

17:05-17:25 The Development of a Design Environment for MEMS/IC ApplicationsSun Xin, Shanghai Research Institute of Microelectronics (SHRIME), Peking University

Friday, March 19

Session III: Testing – I

8:15-8:45 ** TBDDr. Yervant Zorian, Virage Logic Corp. USA

8:45-9:05 MOP-DDPG: Mul t ip le Observa t ion Po in ts Or iented Deterministic Diagnostic Pattern GenerationFei Wang, Institute of Electronics, Chinese Academy of Sciences

9:05-9:25 Identify Yield limiters by Overlay Study of Wafer Sort and Inline Defect ScanCinti Chen,Gang Qian, Xilinx


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9:25-9:45 A Low Power Test Scheme Based on Consistent Segment CompressionWang Wei, School of Computer and Information, Hefei University of Technology, Hefei 230009, China

9:45-10:05 A Case Study of Hierarchical Diagnosis for Core-Based SoCEric Wang, Freescale Semiconductor

10:05-10:25 High-Efficiency Multi-site RF TestLiang Ge, Verigy Ltd.


Session IV: Testing - II

10:45-11:10 * CAT: Critical-Area-Targeted Test Set Modification for Reducing Yield Loss Risk in At-Speed Scan TestingDr. Xiaoqing Wen, Kyushu Institute of Technology, Japan

11:10-11:30High Precision Defect Inspection & BinningAllen Park, KLA-Tencor

11:30-11:40 Advanced in-line Monitoring BF Inspection Tool for E-test Correlation and Yield Analysis on 45nm Test ChipsVikram Gunda, KLA-Tencor

11:40-12:00 A Mathematics Model to Estimate ATE Performance Impacts on EVM Testing of RF 2G and 3G DevicesZaiman Chen, Verigy Ltd.

12:00-12:20 Effectiveness Indices for Statistical Process Control Chart PerformanceSiyuan Frank Yang, SMIC

12:20-13:20 Lunch

Session V: Reliability - I

13:20-13:50 ** Reliability of Advanced CMOS Devices and CircuitsDr. James H Stathis , IBM T. J. Watson Research Center, USA

13:50-14:10 Effects of Moisture Content on Dielectric Constant Lili Ma, University of Electronic Science and Technology of China

14:10-14:30 Reliability Issues in Devices with Advance Gate StackRino Choi, Inha University

14:30-14:50 The Hot-Carrier-induced Degradation and Positive/Negative Bias Temperature Instability in 65 nm CMOSFET DevicesChyuan Haur Kao, Chang Gung University

14:50-15:10 Reverse-bias Electroluminescence Observation for Reliability Investigations of the InGaN LEDHsiang Chen, National Chi Nan University (Taiwan, China)


Session VI: Reliability - II

15:30-15:50 Relating Extrinsic Breakdown Statistics to the Initial Current Leakage Distribution in Gate OxidesJordi Suñé, Universitat Autonoma de Barcelona

15:50-16:10 Breakdown statistics of gate dielectric stacksJordi Suñé, Universitat Autonoma de Barcelona

16:10-16:30 Effect of Oxidation-enhanced Diffusion on Hot-carrier Injection Induced Degradation in N-type High-Voltage DDDMOSFETZhangpeng Deng, East China Normal University

16:30-16:40 The Impact of Different Stress Condition Combinations on Parameters Estimations in Electromigration TestsJinyi Ma, Semiconductor Manufacturing International Corporation

16:40-17:00 Ag Migration Induced Reliability Concern on Micro-electro-mechanical StructurePengfei Zheng, Semiconductor Manufacturing International Corporation

17:00-17:20 A New BSIM3v3 SPICE Model for Reliability of Hot Carrier Injection Effect in MOSFETYueyun Yu, East China Normal University


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Symposium III: Materials and Process Integration for Device and

Interconnection

Symposium Chairs:Frank Chen SMIC, ChinaSowmya Krishnan SEMITRAC, USAMassayasu Tanjyo Nissin Ion EquipmentRan Liu Fudan University, ChinaGanming Zhao Applied MaterialsArchie Liao Air Products, China

Thursday, March 18

Session I

13:15-13:20 Chairman Remarks.

13:20-13:50 ** Future Trend and Opportunities of Non-Volatile MemoryStefan Lai, Being Advanced Memory

13:50-14:10 * Inserted Ultrathin Co, Cr and Mg Layers Effect in Single Crystal Fe/MgO/Fe Magnetic Tunnel Junctions for Developing MRAMXiuFeng Han, Institute of Physics, Chinese Academy of Sciences

14:10-14:25 Effect of 3.0wt.%Bi and 0.05wt.%Cr Addition on the Physical and Mechanical Properties of Sn-3.0Ag-0.5Cu Lead-free Solder AlloyYongjiu Han, Shanghai University

14:25-14:40 Study of Nitride-gate Dielectric Device Reliability and Process Stability Monitoring of the NitrogenJingXiu Tin, ZhaoYong Lu, SMIC

14:40-15:05 Impact of Doped Silicon Oxynitride Gate Dielectric on the 0.13μm CMOS device 1/f noise CharacteristicsZhaoYong Lu, SMIC

15:05-15:15 WCVD Seam Hole Improvement to Prevent BEOL Copper DiffusionXia Li, SMIC


Session II

15:30-15:45 Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC ProductGuan-Qun Zhang, SMIC

15:45-16:00 Mechanism and Solution of Isb Failure on 0.11um Deep Trench DRAMZhi-Chao Li, SMIC

16:00-16:15 Interfacial Microstructure Evaluation of Sn-3.8Ag-0.7Cu Solder Reinforced with Co NanoparticlesTay See Leng, University of Malaya

16:15-16:30 Temperature and Bias Voltage Dependence of Transport Properties in Epitaxial Fe/MgO/Fe Magnetic Tunnel JunctionsQinli Ma, Institute of Physics, Chinese Academy of Science

16:30-16:45 Gearing Towards Process Advancement: Application of Wafer Backside Coating (WBC) TechnologyGlory Jane C. Velasco, Fairchild Semiconductor, Philippines

16:45-17:00Highly Uniform Cu Film Electrochemical Deposition: Optimization of Equipment Chamber Design and Processing ConditionsXi Wang, ACM Research (Shanghai), Inc.

Friday, March 19

Session III

9:00-09:25**Pushing the Limits of Plasma Etch to the NanoscaleDavid B. Graves, UC-Berkeley

9:25-09:45 *Different Interface Role in CuOx Based RRAMJingang Wu, SOC Technology Development Center, Semiconductor Manufacturing International Corp., Shanghai

9:45-10:00 Method to Reduce Crystal Defects in AlCu Bond PadLibbert Peng, Anji Microelectronics(Shanghai) Co., Ltd.

10:00-10:10 Cluster Ion Implantation System for Beyond 32nm Device FabricationMasayasu Tanjyo, Nissin Ion Equipment Co.,Ltd.


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10:10-10:20 Thin Wafer Stencil Print CoatingJeff Schake, DEK Printing Machines

10:20-10:30 The Study on the Stability of μc-Si:H Materials with Different Crystal Volume FractionZhaoZhiWen, HeBei University of Technology


Session IV

10:45-11:15 *Materials Science at the Nanometer Scale in High-k Oxides Technology for Silicon TechnologySupratik Guha, IBM

11:15-11:30 Anomalous off-leakage Currents in CMOS Devices and Its CountermeasuresYonggen He, Semiconductor Manufacturing International Co

11:30-11:40 Growth Control of GaAs Epilayers with Specular Surface on Nonmisoriented (111)B Substrates by MBERuixia Yang, Hebei University of Technology

11:40-11:50 STI Liner Evolution as the CMOS Scaling DownZHAO Zhibiao, Applied Materials China

11:50-12:00 Gate Dielectric Transition from SiO2 to Oxynitride and High K MaterialJi Yue Tang, Applied Materials China

12:00-13:15 Lunch

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Session V

13:15-13:30 Improvement of Characteristic Ramped Voltage Breakdown in Multi-level Cu/SiOC Low k IntegrationYuwen Chen, Semiconductor Manufacturing International Corporation, SMIC

13:30-13:45 GOI Improvement in 65nm Sacrificial Oxide Free Process IntegrationDaniel Deng, Logic Technology Development Center, Semiconductor Manufacturing International 'Corporation

13:45-14:00 Mechanism Analysis of Plasma Charging Damage on Gate Oxide for HDP FSG ProcessXi Li, East China Normal University


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Symposium IV: Patterning and Photolithography

Symposium Chairs:Kafai Lai IBM, USAKen Wu ASML, ChinaZhibiao Mao Toppan, ChinaXiaoming Ma Dow ChemicalZewen Liu Tsinghua University, ChinaHeping Wang Brewer ScienceGary Zhang Dow ChemicalBenjamin Lin Cymer, Taiwan, ChinaLinyong (Leo) Pang Luminescent, USA

Thursday, March 18

Session I: Keynotes


13:20-13:55 **Making a Decision on a Manufacturing Technology for 32-nm Half-Pitch NodesBurn Lin, TSMC

13:55-14:30 ** Complementary Patterning - Viability and GapsYan Borodovsky, Intel

14:30-14:50 *EUV Lithography: Coming with Many ChallengesBanqiu Wu, Applied Materials, Inc.

14:50-15:10 *Mask and Wafer Topography Effects in Optical and EUV-LithographyAndreas Erdmann, Fraunhofer IISB


Session II: Computational Litho

15:30-15:50 * Guang Ke De Moore Fa (Moore's Litho Magic)Vivek Singh, Intel

15:50-16:10 * TBDTracy Weed, Synopsys

16:10-16:30 *3D Challenges Using Conventional 2D LithographyH. W. van Zeijl, Delft Unviersity

16:30-16:50 *Regular izat ion in Inverse Li thography: Enhancing Manufacturability and Robustness to Process VariationsEdmund Lam, University of Hong Kong

16:50-17:10 *From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)Leo Linyong Pang, Luminescent Technologies, Inc.

17:10-17:30 *ArF Scanning Exposure Tool Using High NA Projection LensJianrui Cheng, Shanghai Micro Electronics Co., Ltd.

17:30-17:50 Transformation Procedure from Sparse OPC Model to Grid-Based ModelQingwei Liu, Semiconductor Manufacturing International Corp.

Friday, March 19

Session III: Computational Litho

8:40-9:00 *Lithography Simulation in Mask Inspection and Defect DispositioningYalin Xiong, KLA-Tencor

9:00-9:20 *Litho/Design Co-optimization and Area Scaling for the 22-nm Logic NodeJames Blatchford, Texas Instruments

9:20-9:40 SRAF Optimization for 65nm Flash Memory Contact PatterningYao Xu, SOC TD, Semiconductor Manufacturing International Corp.

9:40-10:00 *Atomic Scale Overlay ControlNigel Smith, Nanometrics

10:00-10:20 *TBDWolfgang Staud, Applied Materials

10:20-10:40 A Copy Machine for Nnanostructures: Substrate Conformal Imprint Lithography (SCIL) on Mask AlignersRan Ji, Süss MicroTec Lithography GmbH



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Session IV: Emergent Technology

10:55-11:15 * EUV mask : Progress and IssueNaoya Hayashi, Dai Nippon Prinitng Co./Ltd

11:15-11:35 *HVM LPP EUV Source System Development StatusBenjamin Lin, Cymer Southeast Asia Ltd.,

11:35-11:55 Mask Cleaning in EUV and Nano-Imprint LithographyYuan Zhang, HamaTech APE GmbH&Co.KG

11:55-12:15 Double Patterning Technology Challenge Below 22nm Node LithographyXiaoming Ma, Dow Chemcials

12:15-13:15 Lunch

Session V: Resist

13:20-13:40 *Optimization of Double Patterning Stacks using Simulation SoftwareRamil Mercado, Brewer Science, Inc.

13:40-14:00 *Bottom-Anti-Reflective Coatings (BARC) for LFLE Double Patterning Process Bang-Ching Ho, Nissan Chemical Industries

14:00-14:20 *Polymer-bound PAGs for EUV LithographyJames W. Thackeray, Dow Advanced Materials

14:20-14:40 *Comparative Study of PS vs. NonPS DBARC SystemsC. Washburn, Brewer Science, Inc.

14:40-15:00 *Research and Optimization of PR/HM/SOC stack in Trilayer process using OptiStackJ. Macie, Brewer Science, Inc.

15:00-15:20 Study on Circle Defect Induced by TARC BubblesEric Wang, Semiconductor Manufacturing International Corporation


Session VI: Process

15:30-15:50 *Recent Topics of Immersion Lithography for Advanced Logic DevicesTakayuki Uchiyama, NEC Electronics Corporation

15:50:16:10 Implant Resist Technology for below 32nm Node ProcessYoshihiro Yamamoto, Dow Chemcials

16:10-16:30 Comparat ive Study of Photosensi t ive Versus Non-Photosensitive Developer-soluble Bottom Anti-reflective Coating SystemsJoyce Ann Lowes, Brewer Science, Inc.

16:30-16:50 Immersion BARC Technology for Hyper NA ApplicationsJeong Yun Yu, Dow Chemcials

16:50-17:10 45nm Post PatterningLeon Yi, Semiconductor Manufacturing International Corp

17:10-17:30 Wafer Nanotopography Interaction with Lithography ChuckSathish Veeraraghavan, KLA-Tencor

17:30-17:50 Effective Poly Gate CDU Control by Applying DoseMapper in 65nm and Sub-65nm Technology NodesLisa Qin, Semiconductor Manufacturing International Corp


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Symposium V: CMP and Post-CMP Cleaning

Symposium Chairs:Ara Phillipossian University. of Arizona, USShumin Wang Anji Microelectronics, ChinaCharles Xing SMIC,ChinaJingxun Fang HHNEC, ChinaKailiang Zhang Tanjin University of Science & Technology, ChinaKuochun Wu Cabot Microelectronics, AsiaMahadevaiyer Krishnan IBM, USGary Ding Intel, USWeichung Yu Dow ChemicalDavid Huang Praxair, USA.

Thursday, March 18

Session I: Process and New Technology ISession Chair: Shumin Wang


13:20-13:50 **CMP Mechanisms and Models: Progress and ChallengesDuane Boning, MIT

13:50-14:10 *CMP Challenges & Opportunities for Advanced TechnologyFeng Chen, Semiconductor Manufacturing International Corp.

14:10-14:30 Extending Cu Endpoint Application for In-situ Thickness Range DetectionYing Xu, Applied Materials

14:30-14:50 Novel In-situ Copper Residue Detection Method for Copper CMP ProcessWeifeng Zhang, Applied Materials


Session II: Process and New Technology IISession Chair: David Huang

15:05-15:35 *CMP Process Technology in TSV ApplicationYuchun Wang, Applied Materials

15:35-15:55 Novel Solution of High Throughput and Low Defects Process for Ultra Thick Cu Film CMPYing Xu, Applied Materials

15:55-16:15 Application and Advantage of CMP in Silicon Wafer ReclaimChangxing Tan, Applied Materials

16:15-16:35 Novel Approach for W Loss Defect Prevention on WCMP Re-clean ProcessJian Zhang, Shanghai Jiao Tong University

Friday, March 19

Session III: CMP Consumables ISession Chair: Kailiang Zhang

8:30-9:00 *TBDChris Yu, Anji Microelectronics (Shanghai) Co., Ltd

9:00-9:20 A Noval Si/Cu Slurry for TSV ApplicationsKanghua Lee, Epoch Material Co., Ltd.

9:20-9:40 Study on Effects of Slurry Key Factors On Advanced Oxide CMP PerformancePeter Song, Anji Microelectronics (Shanghai) Co., Ltd

9:40-10:00 Influence of Abrasive on CMP Quality for NiP Substrate of Computer Hard-diskBaimei Tan, Hebei University of Technology


Session IV: CMP Consumables IISession Chair: Charles Xing

10:15-10:45 *Scaling of Critical Wiring and Implications for Barrier CMPLee Cook, Dow Electronic Materials

10:45-11:15 *The Curious Case of Zeta Modified PVA Brushes for Post-CMP CleaningChris Wargo, Entegris, Inc.

11:15-11:35 Integrated Product and Process for Copper and Barrier CMPCliff Spiro, Cabot Microelectronics Corporation

11:35-11:55 Mosaic Diamond Pad Condit ioner for Improved CMP PerformanceJames Sung, KINIK Company


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11:55-12:15 The Black Pad with Graphite Impregnation for CMPJames Sung, KINIK Company

12:15-13:30 Lunch

Session V: FundamentalsSession Chair: Mahadevaiyer Krishnan

13:30-14:00 *The Nature of Large Contact Areas in Chemical-Mechanical PlanarizationLen Borucki, Araca, Inc.

14:00-14:20 Tribological and Kinetic Characterization of 300-mm Copper Chemical Mechanical Planarization ProcessAra Philipossian, University of Arizona

14:20-14:40 Investigation of Mechanical Effect on Copper CMPJianfen Jing, Anji Microelectronics (Shanghai) Co., Ltd

14:40-15:00 Effect of Pad Micro-Texture on Frictional Force, Removal Rate, and Wafer Topography during Copper CMP ProcessAra Philipossian, University of Arizona

15:00-15:20 Effect of Different Oxidizers on Ge2Sb2Te5 Phase Change Film Chemical Mechanical Polishing PerformanceZefang Zhang, Shanghai Institute of Microsystem and Information Technology


Session VI: Post-CMP CleaningSession Chair: Gary Ding

15:35-16:05 *High Productivity Combinatorial Analysis of Cu Post-CMP Cleans: Copper Corrosion Protection and Queue TimeDavid Yin, ATMI, Inc.

16:05-16:25 Novel Cleaning Solut ions for Next Generat ion CMP ApplicationsLennon Ko, Epoch Material Co., Ltd.

16:25-16:45 Post CMP Pits Defect Improvement in 90/65nm NodeWei Chen, Applied Materials

16:45-17:05 A Novel Post-CMP Electrochemical Cleaning Process Using the BDD Film Anode Combined with Special Chemical AgentsBaohong Gao, Hebei University of Technology


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6

Symposium VI: Thin Film, Etch and Plating

Symposium Chairs:WeiE Wang Intel, BelgiumJionping Lu SMIC, ChinaZhen Guo Intel, USAJason Tian Nikon Precision, ChinaCanyuan Wang Tokyo Electron, ChinaYing Zhang IBM, USAJinrong Zhao North Microelectronics, China

Thursday, March 18

Session I: Thin Film -1


13:20-13:50 ** ULSI vs. TFT Technologies - from Nano to Giga ElectronicsYue Kuo, Texas A&M University

13:50-14:15 *Vapor Deposition of Materials for MicroelectronicsRoy G. Gordon, Harvard University

14:15-14:30 Characterization of PECVD UV-Transparent Silicon Oxynitride for Passivation of Non-flash Memory devicesZheng-Jun Hu, Shanghai IC R&D Center

14:30-14:45 Advanced HDP STI Gap-fill Development in 65nm Logic DeviceYingjie Chen, Applied Materials China

14:45-14:55 Stress Reduction and Stability Improvement in Tungsten Thin FilmsPin-Sheng Hu, SMIC

14:55-15:05 Ta (N) Barrier Film Effect on Via RC in Advanced Cu InterconnectionLuo Liechao, Applied Materials China

15:05-15:15 TaN/Ta Bilayer Barrier Effect on Via RC in 90nm Copper Damascene StructuresLei Shao, Applied Materials China


Session II: Thin Film -2

15:30-15:55 *On the Process and Material Sensitivities for High-k Based DielectricsSven Van Elshocht, IMEC

15:55-16:10 *A Novel Test Structure for Barrier/Low-k DevelopmentLarry Zhao, IMEC

16:10-16:25 *Development of ALD HfZrOx with TDEAH, TDEAZ and H2OX. Shi, H. Tielens, S. Takeoka*, T. Nakabayashi*, L. Nyns, C. Adelmann, A. Delabie, T. Schram, L. Ragnarsson, M. Schaekers, L. Date** and S. Van Elshocht, IMEC

16:25-16:40 Remote Plasma Enhanced Atomic Layer Deposition (PE-ALD) ZnO for Thin Film Transistor (TFT)Jae-Min Kim, S.J. Lim, Doyoung Kim, Hyungjun Kim, Yonsei university

16:40-16:55 Mechamism of Surface Bump Defect Formation in Polysilicon-sti Usg Film Stack for 90nm FlashLi Qingshan, Novellus China

16:55-17:05 High Doping HDP PSG Process DevelopmentXinhua Cheng, Applied Materials China

17:05-17:15 HDP LTO Process Productivity ImprovementEvan Yan, Applied Materials China

Friday, March 19

Session III: Etch-1

9:00-9:25 *TBDTom Ni, AMEC

9:25-9:40 A Study of 65nm Logic Silicon EtchLinlin Zhao, SMIC

9:40-9:55 Synchronous Plasma Pulsing for Etch ApplicationsM. Darnon, CNRS-LTM

9:55-10:10 A Study of 32nm EtchLi-Hung Chen, Tokyo Electron


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10:10-10:20 Impact of Si Oxidation at Dry Strip Process on Device IDDQ PerformanceLingbo Yang, Novellus China

10:20-10:30 Study of Alternative Plasma Strip Techniques for Advanced Photoresist StripShijian Luo, Axcelis Technologies Inc.


Session IV: Etch -2

10:45-11:10 * Influence of the Top Chamber Window Temperature on the STI EtchDenis Shamiryan, IMEC

11:10-11:25 Impact of Etching Chemistry and Sidewall Profile on CD Uniformity and Contact Open in Advanced Logic Contact EtchXin-Peng Wang, SMIC

11:25-11:40 The Mechanism of Over-etch in Poly-gate EtchingZhang Qingzhao, North microelectronics (NMC)

11:40-11:50 300mm Cu BEOL Top Trench Etch Process Development For 65nm Logic TechnologyFrank Ren, Applied Materials China

11:50-12:00 Pattern Density Effect in 65nm/90nm Logic BEOL EtchYali Fu, SMIC

12:00-13:15 Lunch

Session V: Defect and Integration

13:15-13:40 *Modulation and extraction of Schottky barrier height for advanced source/drain contactYulong Jiang, School of Microlectronics, Fudan University

13:40-13:55 Use of Neural Network to Model the Refractive Property of PECVD Silicon Nitride Films to Prevent Water Permeability of Piezoresistive Pressure SensorThongchai Thongvigitmanee, King Mongkut's Institute

13:55-14:10 Study on the Effect of Contamination to WCVD Nucleation LayerYing-Yan Gong, SMIC

14:10-14:25 Study on the Tungsten CVD Periodic Plasma Clean OptimizationTao Liu, SMIC

14:25-14:40 Effective Methods for Crescent Defect Reduction in Cu MetallizationKan Wu, SMIC

14:40-14:55 Study on the Crater Defect Reduction in ECP ProcessLiang Chen, SMIC

14:55-15:10 Wafer Sticking Reduction and MTBF Improvement in AlCu Sputtering ProcessXuan Wang, SMIC


Session VI: Electro Plating

15:30-15:55 * Cu Electrodeposition for 22nm Damascene StructuresJon Reid, Novellus

15:55-16:10 Investigation on Stress and Voids in 65nm Ultra-thick Metal (UTM) Films with Electrochemical Plating ProcessesJia-Xiang Nie, SMIC

16:10-16:25 Advanced Barrierless Metallization of Cu(RuNx) and Cu(ReNx) FilmsC. H. Lin, Department of Environmental Engineering, Chin-Min Institute of Technology, Taiwan, China

16:25-16:35 Rs Uniformity Improvement in ECP SAC ProcessPeng Wang, SMIC

16:35-16:45 Effect of Plating and Anneal Processes on Properties of Electroplated Copper FilmsSheng Liu, SMIC


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7

Symposium VII: Packaging and Assembly

Symposium Chairs:Tom Jiang Micron, USALixi Wan Institute of Microelectronics, ChinaDaniel Lu ChinaJason Shi K&S ChinaRicky S W Lee CAMP, Hong Kong University of Science and Technology, ChinaRoy Yu IBM, USA

Thursday, March 18

Session I: 3D PackagingSession Chair: Tom Jiang


13:20-13:50 **System on Package & 3D IntegrationJohn Knickerbocker, IBM

13:50-14:20 **Commercialization of 3D ICRoert Lo, ITRI

14:20-14:40 3D IC Designs: Myth vs. RealityJing Jou Tang, Industry Technology Research Institute

14:40-15:00 Thin Wafer Handling Challenges and Emerging SolutionsShari Farrens, Suss MicroTec


Session II: Advanced PackagingSession Chair: Richy Lee

15:20-15:50 **The Critical Role of Packaging in the Overall Semiconductor Value ChainWilliam Chen, IEEE CPMT chairman

15:50-16:20 *Emerging Packaging Materials NeedHarold Hovel, IBM

16:20-16:40 Interconnect Technologies and Advanced Packaging for High Performance ComputingJing Shi , Sun Microsystems

16:40-17:00 Flip Chip Assembly by using Carbon Nanotubes Bumps and Anisotropic Conductive-adhesive FilmXia Zhang, Shanghai University

Friday, March 19

Session III: Packaging MaterialsSession Chair: Roy Yu

8:30-9:00 **Materials Roadmap to Support The Packaging TrendMichael Todd, Henkel

9:00-9:15 Studies on Cure Kinetic of a Novel Imidazole Derivative Curing Agent for Epoxy ResinLi Liu, Shanghai University

9:15-9:30 CMOS & CCD Image Sensor Package for UV adhesivesTaro Kenmochi, Kyoritsu Chemical & Co., Ltd.

9:30-9:45 Porosity Analysis on the Performance of Heatsink with MicrochannelsJer-Huan Jang, Ming Chi University of Technology

9:45-10:00 Improving Cost of Ownership for Underfill ApplicationsDan Ashley, Asymtek


Session IV: InterconnectionSession Chair: Daniel Lu

10:20-10:30 Power SO-8: An Interconnect Case StudyGarrett Wong, Orthodyne Electronics/KnS

10:30-10:45 PBGA Cost Reduction by Reducing Plated Au Thickness of Substrate PadsRobert Wang, Intel Corp

10:45-11:00 Interfacial Reaction of Lead Free Solder with Electroplated Ni & Ni-W alloys Films during Multiple ReflowChew Chee Sean, University of Malaya


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7

11:00-11:15 Effect of Thermal Aging on the Interfacial Structure of SnAgCu Nano Composite SolderAemi Nadia Ahmad Sauffi, University Malaya

11:15:11:30 Option for UBM: Good Solderability and Suppressed IMC GrowthLei Zhang, SYNL, IMR, CAS

11:30-11:45 Bond Ball Size Optimization on UCP Die of Chip Card ModuleShen Juan, Infineon Technologies (Wuxi, China)

11:45-13:15 Lunch

Session V: Process TechnologiesSession Chair: Lixi Wan

13:15-13:30 First Multi Beam Full Cut Laser Dicing of Thin Low-K WafersJeroen van Borkulo ,Advanced Laser Dicing International ALSI

13:30-13:45 Using Manufacturing Execution Systems (MES) to Track Complex Manufacturing ProcessesJessica Yue, Camstar Systems

13:45-14:00 Electrostatic Control and the Need of Feedback Control Ionization in Critical Environment of MEMS Manufacturing ProcessAnusorn Chakkaew, King Mongkut’s Institute of Technology Ladkrabang

14:00-14:15 A Solution for Extending Wire Bonding Capillary Life Span under Buildup Accumulation ConditionsTomer Levinson, Kulicke & Soffa Bonding Tools

14:15-14:30 The Effect of Chip Vibration on Bonding Reliability in the Cantilever Bonding ProcessGuozhengYan, Central South University


Session VI: Packages and CharacterizationsSession Chair: Jason Xu

14:50-15:05 Packaging of High-Temperature Power Semiconductor ModulesSimon S. Ang, University of Arkansas

15:05-15:20 Packaging Challenges on Shrink Chip TechnologyYang Xiao, Infineon Technologies (Wuxi) Co., Ltd

15:20-15:35 DDR2/DDR3 Interface Signal Integrity Analysis Based on IBM Generic Package ModelYin Wen, IBM

15:35-15:50 The Research of Iterative Learning Control Method on Linear Voice Coil Motor and Application in Flip ChipHai-Chen Qin, Huazhong University of Science & Technology

15:50-16:05 RF, Microwave, and Optoelectronic Packaging Die and Wire Bonding Case StudiesDaniel D. Evans, Jr., Palomar Technologies


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8

Symposium VIII: Emerging Semiconductor Technologies

Symposium Chairs:

Qinghuang Lin IBM, USA.Jia Chen Research Staff Member, IBM, USAEdward Y. Chang National Chiao Tung University, ChinaJing Kong MIT, USAHyungjun Kim Yonsei University, KoreaJinn P. Chu National Taiwan University of Science and Technology, ChinaJie Zhang Printovate Inc., USAFuhua Yang Institute of Semiconductor, Chinese Academy of Sciences, ChinaWang Yueh Intel, USAPaul R. Berger Ohio State University, USA

Thursday, March 18

Session I: Post Si CMOS: Materials and DevicesSession Chair: Qinghuang Lin & George Bourianoff


13:05-13:35 ** Post Si CMOSGeorge Bourianoff, Intel, USA

13:35-14:00 * Carbon Nano-Electronics – More Than Just SmallZhihong Chen, IBM T.J. Watson Research Center

14:00-14:25 *Fully Depleted SOI Devices for 15nm Node and BeyondChristine Ouyang, IBM T.J. Watson Research Center

14:25-14:50 * Reliability Issues in Devices with Advance Gate StackRino Choi, Inha University

14:50-15:05 Large Area Graphene Derived from Natural GraphiteJames C. Sung, Kinik Company


Session II: Memory Technology and Novel DevicesSession Chair: Jia Chen and Paul Berger

15:20-15:50 ** Phase Change Memory: Opportunities and ChallengesChung H. Lam, IBM T.J. Watson Research Center

15:50-16:15 * Novel 3D Nanofabrication Technique through Soft ElastomersSeokwoo Jeon, KAIST

16:15-16:40 * Challenges and Solutions of Extremely Thin SOI (ETSOI) for CMOS Scaling to 22nm Node and BeyondKangguo Cheng, IBM

16:40-17:05 * Low Resistance W Bit Line and Gate Processes Using Atomic Layer Deposited (ALD)-W Nucleation Layer Prepared Using B2H6 and WF6

Soo-Hyun Kim, Yeungnam University

17:05-17:20 Characteristics of Fluorinated HfO2/Si3N4/HfO2 Stacked Dielectric for Next Generation SONOS Flash MemoryYung-Yu Chen, Lunghwa University of Science and Technology

Friday, March 19

Session III: Novel Materials, Processes and ApplicationsSession Chair: Hyungjun Kim and Roy G. Gordon

8:30-9:00 ** CVD of Self-Aligned Contacts, Barriers, Adhesion and Seed LayersRoy G. Gordon, Harvard University

9:00-9:25 * A New Method for Measuring the Photoacid Diffusion Length and Reaction Kinetics in EUV PhotoresistsWen-li Wu, NIST

9:25-9:50 * Microstructure and Applications of Organosilicate Polymers for Nanoelectronics and OptoelectronicsDo Y. Yoon, Seoul National University

9:50-10:15 *Barrierless Cu-based Electrode for Oxide Thin-film DevicesJinn P. Chu, National Taiwan University of Science and Technology


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8

10:15-10:30 Electrode Surface Modifications for Efficient Polymer Bulk Heterojunction Photovoltaic DevicesPaul R. Berger, Ohio State University


Session IV: III-V SemiconductorsSession Chair: Edward Chang and Minghwei Hong

10:45-11:15** MOCVD Growth of GaN-based Heterostructures and The 2DEG Transport/Spin PropertiesBo Shen, Peking University

11:15-11:40* Nano-electronics of High K Dielectrics on InGaAs and Ge for Key Technologies Beyond Si CMOSMinghwei Hong, National Tsing Hua University, Taiwan, China

11:40-11:55Si and GaAs Layer Transfer Process Using Metallic BondingJizhong Li, Amberwave Systems, USA

11:55-12:10Selective Epitaxial Growth of InP and InxGa1-xAs in Shallow-trench-isolated Trenches on Miscut Si (001) SubstratesGang Wang, IMEC/KULeuven, Belgium

12:20-13:20 Lunch

Session V: Solar Cells and LEDsSession Chair: Jie Zhang and Deren Yang

13:20-13:45 * Silicon Based Opto-electronic Light Emitting Materials and DevicesDeren Yang, Zhejiang University

13:45-14:10 * Novel Device Concept Using Si Membrane Transfer PrintingTae-Yun Lee, Yonsei University, South Korea

14:10-14:25Delivering Production Worthy 200mm Toolset for The MEMS Industry Based upon Cost-effective, High-volume Production StrategiesDurga Chaturvedula, Applied Materials, Inc

14:25-14:40Amorphous Diamond Solar Cells with Nanodiamond Quantum WellsJames C. Sung, Kinik Company

14:40-14:55Diamond Islands Wafer for Super LED ManufactureJames C. Sung, Kinik Company


Session VI: Organic Semiconductors, New Materials and ProcessesSession Chair: Jinn P. Chu and Jae Kyeong Jeon

15:10-15:35* Emerging ZnO-based Oxide Thin Film TransistorsJae Kyeong Jeong, Inha University, South Korea

15:35-16:00* Silicon Monatomic Chain: MD and DFT Simulations of Formation and Physical-Mechanical PropertiesYa-Pu Zhao, State Key Laboratory of Nonlinear Mechanics, Institute of Mechanics, Chinese Academy of Sciences

16:00-16:15Low Voltage Organic Circuits with High-k MaterialsLiwei shang, Institute of Microelectronics, Chinese Academy of Sciences

16:15-16:30AMC Control inside Wafer Microenvironments – Challenges and Systematic SolutionsHuaping Wang, Entegris, Inc., USA

16:30-16:45Multivariate Statistical Process Control in Etching ProcessXie Kai, Beijing Northern Microelectronics, China

16:45-17:00Application of Pattern Recognition Technology in Process Fault DetectionZhang Shan Gui, Beijing Northern Microelectronics, China


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9

Symposium IX: Silicon Materials and Materials for Solar Applications

Symposium Chairs:David Huang Praxair Inc., USA.Koichi Kakimoto Kyushu University, JapanDeren Yang Zhejiang University, ChinaHenry Erk MEMC, USARenhe Jia Applied Materials, USAYing Shi Gritek,ChinaTimmy Bao BTU International, China

Thursday, March 18

Session I: Polysilicon Production and Photovoltaic Cell TechnologySession Chair: Dr. David Huang. Praxair, USA


13:05-13:30 *Solar Cells Technologies and Their TrendsTomi T. Li, Department of Mechanical Engineering, National Central University

13:30-13:55 *Rapid Technology Introduction of Large-area Thin-film Panels: Design, Production and DeploymentMichel FREI, Applied Materials

13:55-14:20 *Polysilicon FBR Technology for Solar and Semiconductor SiliconGraham R. Fisher and Milind Kulkarni, MEMC Electronic Materials Inc., Catholique de Louvain1, FEMAGSoft S.A. Company

14:20-14:45 *Best in Class Polysilicon Production ProcessRuss Hamilton, GCL Solar Energy, China / US


Session II: Crystal Growth and Impurity ControlSession Chair: Prof. Deren Yang, Zhejiang University, China

15:00-15:25 *Numerical Analysis of Carbon and Oxygen DistributionsKoichi KAKIMOTO, Kyushu University

15:25-15:40 Modeling the Early Stages of Oxygen AgglomerationGudrun Kissinger, IHP

15:40-15:55 Oxygen Precipitate Nucleation in Heavily Antimony-doped Czochralski SiliconWeijiang Zhu, State Key Laboratory of Silicon Materials and Department of Materials Science and Engineering, Zhejiang University

15:55-16:10 Modeling of the 3D Unsteady Melt Flow in a Cz-Si Crystal Growth Using LES Method.II. Analysis of the Turbulent Melt Flow in an Industrial-scale Cz-Si Growth.Lijun Liu, Xi’an Jiaotong University

16:10-16:35 Ge Doping of Si Substrates for Improved Crystal Quality and Device YieldJan Vanhellemont, Ghent University

16:35-16:50 Development and Application of a Structured/Unstructured Combined Mesh Scheme for Global Modeling of a Directional Solidification Process of SiliconLijun Liu, Xi’an Jiaotong University

16:50-17:05 Optimisation on Junction Formation by Three Stack Furnace POCl3 Diffusion and Analysis on Solar Cell PerformanceCheow Siu Leong, Solar Energy Research Institute, National University of Malaysia (UKM)

17:05-17:20 Copper Precipitates in Multicrystalline Silicon for Solar CellsXiaoqiang Li, Zhejiang University

Friday, March 19

S e s s i o n I I I : B u l k Wa f e ri n g a n d Substrate ProcessingSession Chair: Dr. David Huang. Praxair, USA

8:30-9:00 * Wet Etching Technology for Semiconductor and Solar Silicon ManufacturingHenry F. Erk, MEMC Electronic materials, Inc.

9:00-9:25 * Polishing of Semiconductor MaterialsRobert L Rhoades, Entrepix

9:25-9:50 * Historical Review on Silicon Wafer GrindingZ.J. Pei, Kansas State University

9:50-10:05 Simultaneous Double Side Grinding of Silicon Wafers: a Further Investigation into Grinding Marks PatternZhichao Li, North Carolina Agricultural & Technical State University

10:05-10:20 The Application of Reactive Ion Etching in Texturization of Polycrystalline Silicon Wafers for Solar CellsHu Liqiong, Beijing Northern Microelectronics

10:20-10:35 Fabrication of GaN on Patterned Silicon-on-insulator by Epitaxial Lateral Overgrowth Zhang Bo, Shanghai Institute of Microsystem and Information TechnologyZhang Bo, Shanghai Institute of Microsystem and Information Technology


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9


Session IV: Emerging Technology and MaterialsSession Chair: Prof. Deren Yang, Zhejiang University, China

10:50-11:15 *Industrial SOI Technology by Ion ImplantationWang Xi, Shanghai Simgui Technology Co., Ltd.

11:15-11:30 An Extraction Method of Solar Cell Parameters with Improved Particle Swarm Optimization AlgorithmMeiying Ye, Zhejiang Normal University

11:30-11:45 Physical and Electrical Characteristics of the High-K Er2O3

Polyoxide Deposited on Polycrystalline SiliconChyuan Haur, Kao Chang Gung University

11:45-12:45 Lunch

Session V: Device Engineering and ApplicationSession Chair: Prof. Koichi KAKIMOTO, Kyushu University, Japan

12:45-13:10 *Pathway to High Efficiency c-Si Solar CellsQi Wang, NREL

13:10-13:35 *Advances in Inline Diffusion Processes for the Manufacture of Crystalline Silicon Solar CellsFrank J. Bottari, BTU International

13:35-13:50 Recent Advance in Inline Thermal Process Technology for c-Si Solar Cell ManufacturingTianming Bao, BTU International

13:50-14:05 Fabrication of SB-MOSFETs on SOI Substrates Using Ni Silicide Containing Er InterlayerWataru Hosoda, Tokyo Institute of Technology

14:05-14:20 Performance of Silicon Ballistic Nanowires MOSFETs with Diverse Orientations and DiametersAbudureheman Abudukelimu, Tokyo Institute of Technology

14:20-14:35 The optimisation aspect of screen printed Si solar cellShahrul Anizan, Solar Energy Research Institute, Universiti Kebangsaan Malaysia

14:35-14:50 Novel Mechanically Stacked Multi-junction Solar Cells Applying Ultra-thin III-V Cells and Wafer Based Germanium CellLu Zhao, IMEC

14:50-15:05 Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate DielectricKatsuya Matano, Tokyo Institute of Technology


Session VI: Materials Properties and CharacterizationSession Chair: Prof. Koichi KAKIMOTO, Kyushu University, Japan

15:20-15:45 * Dislocation control through interactions with impurities in SiIchiro Yonenaga, Tohoku University, Japan

15:45-16:05 *Silicon Technology for Solar ApplicationS. Babu, Clarkson university, USA

16:05-16:20 Analysis of Elemental Impurities in Photovoltaic Silicon by Inductively Coupled Plasma Mass SpectrometryJianmin Chen, PerkinElmer Inc.

16:20-16:45 Laser Annealing and Local Heating Effects During Raman Measurement of Hydrogenated Amorphous Silicon FilmsYing-Jhe Yang, National Taiwan University

16:45-17:00 A Research on Thick PIN Detector with High Breakdown VoltageDongmei Wu, Institute of Microelectronics, Peking University

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Conference Chair

Dr. Hanming Wu, SMIC, China

Executive Committee

Dr. Qinghuang Lin, IBM, USA.Dr. Cor Claeys, IMEC, BelgiumDr. David Huang, Praxair, USA.Mrs .Ying Shi, Gritek,ChinaDr. Yue Kuo, Texas A&M University, USADr. Ru Huang, Peking University, ChinaDr. Peilin Song, IBM, USADr. Frank Chen, SMIC, ChinaDr. Kafai Lai, IBM, USADr. WeiE Wang, Intel, BelgiumDr. Tom Jiang, Micron, USADr. Ara Phillipossian, University of Arizona, USA

Advisory Committee

Dr. Minhwa Chi, SMIC, ChinaDr. Philip Wong, Stanford University, USADr. Swami Mathad, Tech. Consulting, USA Dr. Georg Bednorz, IBM, Dr. Gilbert Declerck, IMECDr. Hsing-Huang Tseng, Texas State University, USADr. Steve Yang, GSMC, ChinaDr. Qingyuan Han, Hans Consulting International, USADr. Shichang Zou, Chinese Academy of Sciences, ChinaDr. Hailing Tu, GRINM, China

Steering Committee

Dr. Roque Calvo, ECSDr. Allen Lu, SEMI, ChinaDr. Hiroshi Iwai, Tokyo Institute of Technology, JapanDr. Tomi T. Li, National Taiwan Central University

Committee MemberDr. Shaoning Mei, HHNEC, ChinaDr. Boyong He, CSMC, ChinaDr. Huiling Shang, IBM, USADr. Hong Wu, SST, ChinaDr. Bin Wang, Spansion, ChinaDr. Wen-li Wu, NIST, USADr. Yuhua Cheng, Peking University, ChinaDr. Francis Jen, KLA-Tencor, ChinaDr. Kelvin Xia, Verigy, ChinaDr. Srinivas Raghvendra, SynopsysDr. Xiaowei Li, Institute of Computing Technology, Chinese Academy of Sciences, ChinaDr. Sowmya Krishnan, SEMITRAC, USADr. Massayasu Tanjyo, Nissin Ion EquipmentDr. Ran Liu, Fudan University, ChinaDr. Curtis Liang, ASML, ChinaDr. Ganming Zhao, Applied Materials, ChinaDr. Archie Liao, Air Products, AsiaDr. Ken Wu, ASML, ChinaDr. Zhibiao Mao, Toppan, ChinaMr. Xiaoming Ma, Dow Chemical, ChinaProf. Zewen Liu, Tsinghua University, ChinaDr. Heping Wang, Brewer ScienceDr. Gary Zhang, Dow Chemical Dr. Benjamin Lin, Cymer, Taiwan, ChinaDr. Linyong (Leo) Pang, Sr.VP.& GM, Luminescent, USADr. Shumin Wang, Anji Microelectronics, ChinaDr. Charles Xing, SMIC, ChinaDr. Jingxun Fang, HHNEC, ChinaDr. Kailiang Zhang, Tanjin University of Science & Technology, ChinaDr. Kuochun Wu, Cabot Microelectronics, AsiaDr. Mahadevaiyer Krishnan, IBM, USADr. Gary Ding, Intel, USADr. Weichung Yu, Dow Chemical,Dr. Jionping Lu, SMIC, ChinaDr. Zhen Guo, Intel, USADr. Jason Tian, Nikon Precision, ChinaDr. Canyuan Wang, Tokyo Electron, ChinaDr. Ying Zhang, IBM, USAMr. Jinrong Zhao, North Microelectronics, ChinaDr. Lixi Wan, Institute of Microelectronics, ChinaDr. Daniel Lu, ChinaDr. Jason Shi, K&S ,ChinaDr. Ricky Swlee, Hong Kong University of Science and Technology, ChinaDr. Roy Yu, IBM, USADr. Jia Chen, IBM, USA Dr. Edward Y. Chang, National Chiao Tung University, Dr. Dorel Toma, Tokyo Electron , USADr. Jing Kong, MIT, USADr. Hyungjun Kim, Yonsei UniversityDr. Jinn P. Chu, National Taiwan University of Science and Technology, ChinaDr. Jie Zhang, Printovate Inc., USADr. Fuhua Yang, Institute of Semiconductor, Chinese Academy of Sciences, ChinaDr. Wang Yueh, Intel, USADr. Paul R. Berger, Ohio State University, USADr. Koichi Kakimoto, Kyushu University, JapanDr. Deren Yang, Zhejiang University, ChinaDr. Henry Erk, MEMC, USADr. Renhe Jia, Applied Materials, USADr. Timmy Bao, BTU International, China

SEMI and ECS thank the committee members for volunteering countless hours and providing the expertise necessary to bring you CSTIC 2010

Documents

中国国际半导体技术大会 2009 Distinguished China …server.semiconchina.org/downloadFile/1286860792406.pdf · 大会包括主题演讲及九个技术分会,由业界