Journal of Engineering Technology Vol. 2(1): 67-71, 2012 ISSN 2231-8798 © 2012 UniKLBMI

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Graduate Enhancement Programme for Building up IC Layout Technologies

M.A. Abas1, M.A.M. Rusli2, S. Sakrani2, N.I.Z. Aizudin2 & A.A. Syari2

1Section of Electronics Technology Universiti Kuala Lumpur British Malaysian Institute

2ICmic-UniKL Academy, Cyberjaya, Malaysia

Corresponding email: drmamir@bmi.unikl.edu.my

Abstract: When dealing with IC design, it is important to have a solid IC layout and there are so many things need to consider ensuring that the chip is working properly. Beside that, layout design must be well created to show that the chip has a strong performance, a small size and ability to be manufactured. To fulfill this requirement, someone must have a relevant skill due to the rapid growth in IC design industry increased a demand on qualified and skilled manpower. Therefore, a comprehensive training in IC design is really significant to the industry need. For this reason, the apprenticeship programme was developed by ICmic-UniKL Academy which focused on IC design competency. Through this apprenticeship, apprentice was exposed to the custom IC layout design tools and opportunity to do hands-on job then can directly involve in IC design industry thus closing the gaps with industry requirement. A Touch Screen Digitizer IC was highlighted to demonstrate one of the projects carried out by the apprentices. At the end of this apprenticeship, the apprentices will able to master the skills and become highly competent and knowledgeable engineers. Keywords: Apprentice, IC design, IC layout, touch screen

1.0 INTRODUCTION

IC Design industry is expected to growth faster as nowadays electronic products need new features which depending on the technology usage of IC to increase the marketing strategy [1]. The specialization field in IC Design offer an extensive job prospects starts from circuit design, layout design, fabrication, assembly and testing which has a wider option to choose. One of the jobs that get the higher demand from the industry is layout design engineer. This job require someone to have really high skilled due to the layout design is very important and complicated process which tiny transistors being constructed on a silicon wafer. A few considerations need to take into account by applying appropriate layout design techniques due to layout may affect the quality and reliability of the chips.

A significant number of newly hired layout engineer lacked relevant IC layout experience due to it is greatly different when using a commercial EDA tools [2] such as SILVACO. Even they have strong fundamentals in IC layout, but without any knowledge of commercial design flows often required them to undergo intensive training which would take a couple of months to educate and familiarize the tools [1][3]. Therefore, an intensive programme such as the academy is certainly required to

develop IC layout skill in more planned system. Apprenticeship programme has been established in collaboration with several entities namely UniKL, ICmic and Silvaco. Then, ICmic-UniKL Academy is formed to make sure the programmes are well organise. The project is moving progressively with the aims to cater the demand of IC design particularly in Malaysia and neighboring countries like Singapore, Thailand, China and etc. The remainder of this paper, Section II, describes the competencies structure as part of apprenticeship programme. Section III addresses the tools and technology implementation. Section IV explained the example of the project development carried out by the apprentice. Section V discussed on some of the IC layout techniques and their advantages. Finally, Section VI highlights the conclusions of the apprenticeship competency project. 2.0 COMPETENCIES

In the beginning, almost all of the participants of the apprenticeship programme only have little knowledge in IC layout design or none. This is due lack of local experties in IC layout design in educational fields. For this reasons, ICmic-UniKL Academy introduce the competency of IC layout design for the participants of the

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apprenticeship programme. There are several competency modules in IC layout design, which are analog layout design, mixed-signal layout design (analog mixed with digital), and layout design yield and manufacturing. Those competency modules are conducted accordingly to help the apprentices mastering it. One of the Silvaco EDA Tools is used for this purpose, which is EXPERT.

Firstly, the apprentices are needed to go through the analog layout design. Within this competency apprentices are required to design a layout for a typical opamp together with its compensate capacitance. A short lecture is given before the apprentices begin to design their layout. Here, the apprentices can take the opportunity to make them-selve understood about several analog IC layout design techniques, such as cross-couple, symmetry, fingering, and etc.

Secondly, the mixed-signal layout design. Mixed-signal means analog and digital design combined into one IC. The process apprentices need to go through is the same as the analog IC layout design, the apprentices need to go through lecture and complete the layout design assignments. This competency can be consider the tough one due to the IC comprise analog and digital layout design techniques, such as floorplan issue, latchup issue, matching issue, etc.

Finally, is about layout design yield and manufacturing competency. The apprentices are introduced to the yield information and calculation. It is a compulsory for the apprentices to master the first & second competencies layout design techniques to ensure their layout designs can achive high yield percentage on a wafer per layout design. Besides layout design yield, the apprentices also need to understood about layout fabrication manufacturing process. Manufacturing knowledge helps the apprentices to learn more about the IC layout design techniques.

All of the competencies have more than one assignments given to the apprentices in order to provide more practical problems solving towards each design techniques. Besides competencies, the apprentices are also given opportunity to discuss and ask questions regarding layout design techniques, yields, etc. to any professional IC layout design engineers available within the academy.

3.0 TOOLS AND TECHNOLOGY

ICmic-UniKL Academy provides Silvaco EDA Tools to each of the apprentice. EDA Tools is electronic design assistant tools which help researchers and designers to design and analyze their design performance. Silvaco EDA Tools is consisting of design tools for IC Design, IC Layout Design, Verilog IC Design, spice tools design, etc.

The academy is using 0.18µm CMOS Technology for Analog, Digital, and Mixed-Signal IC Design and IC Layout Design. 0.18µm CMOS Technology is one of the commercial CMOS Technology that’s being used today. The academy is collaborated with SilTerra for the technology, which the academy research for IC and IC Layout Designs, and SilTerra provide the technology model files and fabrication opportunities.

4.0 PROJECT DEVELOPMENT

Beside the competency modules, there is an anchor

project that’s the apprentices need to fulfill. The project is designed to enhance the development on circuits design, layouts design and IC fabrication. The project focused within this paper is “KTF7792: Touch Screen Digitizer IC” layout.

4.1 Circuit design stage Basically, the layout for touch screen IC divided into analog and digital area. The full layout consists of the main blocks which are Serial Port (SPORT), CDAC and RDAC, comparator, multiplexers, and the various types of analog and digital switches [5]. Fig.1 shows the full schematic that’s have been designed by the apprectices. The schematic is needed as reference to develop the IC layout and it is also used for verification process of IC layout design versus schematic.

Fig.1 Full circuits design schematic

4.2 IC layout design stage Fig.2 shows the full layout of touch screen IC. It shows the guard ring and pads around the chip layout. The pads will use as a connector between inside the chip with the packaging that will connected to TSSOP package. The next process is fabrication after the verification of layout has been fulfilled. The methods that have been used for optimization the layout performance was multifingering, common centroid, cross coupled, dummy devices, interdigitated, symmetry, and metal fill placement.

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Fig.2 Top level layout for touch screen

4.3 Design rules check (DRC) Fig.3 shows the Design Rules Check (DRC), which is a powerful feature of EXPERT that checks geometrical design rules during construction, in other words “on the fly”. Rules for checking are specified by SilTerra Process Technology DRC script, then the IC layout analyzed through EXPERT/GUARDIAN DRC. The violations are not saved in the DRC error database, but are reported by blinking markers on the screen.If the cursor is placed at a blinking error marker, a short description of the error appears as a small pop-up label [6].

Fig.3 DRC Verification 4.4 Layout versus schematic Fig.4 shows the next verification which is layout versus schematic (LVS). GUARDIAN LPE extracts the devices (MOSFETs, BJTs, diodes, resistors) and connectivity information from the layout and produces the circuit description in Spice netlist format. The extracted netlist of the designed chip layout can be compared with

the schematic design netlist by using GUARDIAN LVS, layout versus schematic (LVS) comparison tool.

Fig.4 LVS Verification

The total number of components used on this design is 2461 components consist of NMOS, PMOS, capacitors, resistors and BJT PNP. One of the important parameter that can be focused on this layout development is the area. The die size for this application IC is x-axis is 1699µm by y-axis is 1809µm. 4.5 File types There are several types of files that related to the layout development in EXPERT. These types of files are necessarily for operational of layout functionality and verification. Expert Layout Database (*.eld file)

It is a binary file (with an .eld extension) containing the layout data, technology data, and system setup parameters in EXPERT’s internal format.

GDSII file (*.gds file) GDSII, or stream files, are binary files uses to transfer layout designs between different CAD systems. Most often these files have the following extensions: *.gds, *.sf, *.stm, *.str. In some cases, however, they may have other extensions. For example, when the “DRC error reports” are output in the stream format. To make EXPERT recognize these extensions, specify them in the GDSII I/O setup.

Technology files (*.tcn file) The .tcn file extension defines layers and some design parameters of IC layout. It is used mainly when loading a project from different formats. Files in .eld format contain

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all necessary technology data. However, an external technology file also can be used for .eld files [6].

5.0 IC LAYOUT TECHNIQUES Several analog CMOS IC layout techniques are

implemented to fabricate high quality circuits. The pair groupings of transistors are maintained and the pairs are multifingered using fingering method and interdigitated to avoid mismatched and offsets. Symmetry is employed together with the cross-couple technique in the layout to lessen sensitivity to process variations (process corner) and improve matching issue to help improves supply noise rejection [7]. Guard rings are implemented as close as possible around the transistors for isolation. Routing within the circuit is minimized to avoid parasitic between metals and active devices. Almost all of the techniques mentioned are implemented in Fig.5.

Fig.5 Fingering, cross-couple, and symmetry layout of two PMOS

Furthermore, common centroid for capacitor can be used as shown in Fig.6 and Fig.7. This common centroid architecture with rounded capacitor as shown in Fig.8, can canceled any linear gradient in fabrication. It can be used as cancellation of the thermal gradient and die stress gradient. For the outcome, this technique can give low offset and stability over time.

Fig.6 Common centroid capacitor arrangement

Fig.7 Layout for capacitor with common centroid

Fig.8 Rounded capacitor type

Another method to optimize the performance of IC layout especially for the top level layout was pad placement and PMOS NMOS diffusion. The rules of distance between PMOS and NMOS that are connected to

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the pad which will be used to connect with external input should be more than 70um as shown in Fig.9. It can be used to prevent the latch-up between different diffusion of PMOS and NMOS. Fig.10 shows the layout connection for the pads and transistors.

Fig.9 Distance rules

Fig.10 Layout of pad placement and PMOS- NMOS diffusion connection

6.0 CONCLUSION This is a great platform to train those who desire to enhance their further knowledge and career in IC layout design, since the academy has provided the competency development that realize to the industry demands. The competency development effectively fulfill by the guidance from professional engineers based on practical design that can be used to boost the performance of the apprentices. Hence, the apprentices gained the significant experiences and knowledge to join in the industry.

REFERENCES

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Designer through Apprenticeship Programme”, IEEEin Industrial Electronics & Applications, ISIEA 2009, vol.1, pp.542-547, October 2009.

[2] M.Amir, D. Kinniment, G.Russel, “Designing IC Layout

through In-expensive Software Tool”, 1st Proceeding of International Conference on Engineering Technology ICET07, December 2007.

[3] Y.Ping Xu, “Two-Semester Project Based Mixed-Signal IC

Design course Using Commercial EDA Tools – From Design to Chip evaluation” Proceeding of the 2003 IEEE International Conference on Microelectronics System Education (MSE’03), 2003.

[4] R. Schaller, “Moore’s Law: Past, Present, and Future”

IEEE Spectrum, June 1997, pp. 52-59. [5] Analog Design, “Touch screen Digitizer Datasheet

AD7843”, www.analog.com, USA, 2004. [6] Simucad Design Automation, “Expert Software Manual”,

www.simucad.com, USA, 2004. [7] M. Afham et al, “Investigating Noise Reduction

Capabilities in CMOS Pre-Amplifier Circuits”, IEEEin Industrial Electronics & Applications, ISIEA 2010.