99101

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IC +=

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(Integration circuit, IC)(R) (C) (L)(Bipolar, D) (T)... (chip)

IC ?

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&

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1958IC, , , (sub-micro) (architecture)

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, (silicon valley) IC ?

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Gordon Moores Law

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Answer:

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What is silicon ?

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Zero LayerIC

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Po-Ying Chen*, Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination during Wafering Process, Jpn. Journal of Applied Physics, p. 8685-8690, SCI, N/M=50/94, IF: 2.85., IF: 2.47, (2008) citation: 3 2.

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(Metal-Oxide-Semiconductor Field-Effect Transistor)MOSFET6.

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Rough Si substrate -- The gate dielectric layer roughness will reduce the electronic mobility. ee2.5V for 0.25um DR1.0V for 0.09 um DR6.

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-- The flatness will result-in the patterning lose problem.7.

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"Stiff" ("Hard") Pad CMP Process Planarization Length ~ 7 - 10 mmOxideSiliconNanotopography Length

5 mm for example -- CMP process will induce nano-topography issue, and this problem will affect the device performance.7. Preferentially thins surface films in raised nanotopography areas.

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Improved Polishing

pad optimized

THA2: 17.7nm 9.3nm 2x2mm

THA4:32.7nm 21.9nm 10x10mmImpact on Nano-topography7.

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Raw Wafer COP

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Raw Wafer BMDBulk Micron Defect= Voids + O2

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BMDRaw Wafer BMD

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BMDRaw Wafer BMD

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Raw Wafer BMD

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Raw Wafer BMD

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Raw Wafer BMD

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OmaxOrOmaxVoltageOrV(a)OmaxOrO(b)Distance(inch)Surface Charges Accumulation (V)204681012024681012X10R11. IC

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121

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(2)

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(9) (9) ()

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(Summary)1. IC40,

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Thanks!

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