NREMotorola 68HC05 199610NRENRE/

3.1

1. ProcessorControl unitDatapathALURegistersIRPCControllerMemoryI/OControl/Status10......101111

2.

ProcessorControl unitDatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0R1100load R0, M[500]

ProcessorControl unitDatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0R1100load R0, M[500]

ProcessorControl unitDatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0R1100load R0, M[500]10

ProcessorControl unitDatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0R1100load R0, M[500]10

ProcessorControl unitDatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0R1100load R0, M[500]10

3.

4.

Cache

PC=100clk100

10PC=100FetchDecodeFetch opsExec.Store resultsclkPC=101clk101

1110PC=100FetchDecodeFetch opsExec.Store resultsclkPC=101FetchDecodeFetch opsExec.Store resultsclkPC=102clk102

12345678123456781234567812345678Fetch-instr.DecodeFetch ops.ExecuteStore res.1234567812345678123456781234567812345678TimeTimeTime 1

SISDSIMDMIMDMPSoC

: (C, C++, Java, etc.)

1. MOV Rn, directMOV @Rn, RmADD Rn, Rm0000Rndirect0010Rn0100RmRnRn = M(direct)Rn = Rn + RmSUB Rn, Rm0101RmRn = Rn - RmMOV Rn, #immed.0011RnimmediateRn = immediate.JZ Rn, relative0110RnrelativePC = PC+ (only if Rn is 0)RnMOV direct, Rn0001RndirectM(direct) = RnRmM(Rn) = Rm

2.

int total = 0;for (int i=10; i!=0; i--) total += i;// ...C MOV R0, #0; // total = 0MOV R1, #10; // i = 10JZ R1, Next; // i=0 ADD R0, R1; // total += iMOV R2, #1; // constant 1JZ R3, Loop; // Loop:Next:// ...SUB R1, R2; // i--MOV R3, #0; // constant 00123567

3. e.g., 64 Kbytes program, 256 bytes of RAM (expandable): 8086CPU8/1632ARM32SoCI/OInterrupts

.DB file_name out.txt -- store file name

MOV R0, 1324 -- system call open idMOV R1, file_name -- address of file-nameINT 34 -- cause a system callJZ R0, L1 -- if zero -> error

. . . read the fileJMP L2 -- bypass error cond.L1: . . . handle the error

L2:

4. PC

4.1 (Compiler)(Assembler) (Linker)(Debugger)(Profiler)

4.2 : : Instruction set simulator (ISS)ISS

ISS#include typedef struct { unsigned char first_byte, second_byte;} instruction;

instruction program[1024]; //unsigned char memory[256]; //

int run_program(int num_bytes) {

int pc = -1; unsigned char reg[16], fb, sb; while( ++pc < (num_bytes / 2) ) { fb = program[pc].first_byte; sb = program[pc].second_byte; switch( fb >> 4 ) { case 0: reg[fb & 0x0f] = memory[sb]; break; case 1: memory[sb] = reg[fb & 0x0f]; break; case 2: memory[reg[fb & 0x0f]] = reg[sb >> 4]; break; case 3: reg[fb & 0x0f] = sb; break; case 4: reg[fb & 0x0f] += reg[sb >> 4]; break; case 5: reg[fb & 0x0f] -= reg[sb >> 4]; break; case 6: pc += sb; break; default: return 1;

} } return 0;}

int main(int argc, char *argv[]) {

FILE* ifs;

If( argc != 2 || (ifs = fopen(argv[1], rb) == NULL ) { return 1; } if (run_program(fread(program, sizeof(program)ifs)) == 0) {print_memory_contents();return(0); } else return(-1);}

4.3 ISS , ...: emulatorPC

(ASIPs)e.g., CPPNRE, ASIPs e.g., , , , , , etc.

ASIP:(): e.g., VCR, , , Microcontroller ADC.

ASIP: (DSP)e.g., , TV, DSP e.g., ALUs, , etc.

ASIPs, (IP)e.g., VHDL modeldatapath: /ASIP: e.g., www.tensillica.com: compilerse.g., www.improvsys.com ( VLIW )

Sources: Intel, Motorola, MIPS, ARM, TI, and IBM Website/Datasheet; Embedded Systems Programming, Nov. 1998

Processor

Clock speed

Periph.

Bus Width

MIPS

Power

Trans.

Price

General Purpose Processors

Intel PIII

1GHz

2x16 K

L1, 256K

L2, MMX

32

~900

97W

~7M

$900

IBM

PowerPC

750X

550 MHz

2x32 K

L1, 256K

L2

32/64

~1300

5W

~7M

$900

MIPS

R5000

250 MHz

2x32 K

2 way set assoc.

32/64

NA

NA

3.6M

NA

StrongARM

SA-110

233 MHz

None

32

268

1W

2.1M

NA

Microcontroller

Intel

8051

12 MHz

4K ROM, 128 RAM, 32 I/O, Timer, UART

8

~1

~0.2W

~10K

$7

Motorola

68HC811

3 MHz

4K ROM, 192 RAM, 32 I/O, Timer, WDT, SPI

8

~.5

~0.1W

~10K

$5

Digital Signal Processors

TI C5416

160 MHz

128K, SRAM, 3 T1 Ports, DMA, 13 ADC, 9 DAC

16/32

~600

NA

NA

$34

Lucent

DSP32C

80 MHz

16K Inst., 2K Data, Serial Ports, DMA

32

40

NA

NA

$75

ISS

FSMD

Declarations: bit PC[16], IR[16]; bit M[64k][16], RF[16][8];1664K

DatapathIRPCController(Next-state and controllogic; state register)Memory

RF (16)RFwaRFweRFr1aRFr1eRFr2aRFr2eRFr1RFr2RFwALUALUs2x1 muxALUzRFsPCldPCincPCclr3x1 muxMsMweMre16Irld210AD10

datapathFSM FSMD RFwa=rn; RFwe=1; RFs=01;Ms=01; Mre=1;RFr1a=rn; RFr1e=1; Ms=01; Mwe=1;RFr1a=rn; RFr1e=1; Ms=10; Mwe=1;RFwa=rn; RFwe=1; RFs=10;RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=00RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=01PCld= ALUz;RFrla=rn;RFrle=1;MS=10;Irld=1;Mre=1;PCinc=1;PCclr=1;ResetFetchDecodeIR=M[PC];PC=PC+1Mov1RF[rn] = M[dir]Mov2Mov3Mov4AddSubJz011001010100001100100001op = 0000M[dir] = RF[rn]M[rn] = RF[rm]RF[rn]= immRF[rn] =RF[rn]+RF[rm]RF[rn] = RF[rn]-RF[rm]PC=(RF[rn]=0) ?rel :PCto Fetchto Fetchto Fetchto Fetchto Fetchto Fetchto FetchPC=0;from states belowFSMD!

GPPNRE, ISSICEin-circuit emulatorsASIPs, DSPs, ASIPsGPP

: PCI/O3 :

PC

Parallel port

Pin 13

Pin 2

Switch

LED

Parallel Port Example.386

CheckPortprocpushax; axpushdx; dxmovdx, 3BCh + 1; base + 1 1inax, dx; #1and al, 10h; 4cmpal, 0; al0 ?jneSwitchOn; LEDSwitchOff:movdx, 3BCh + 0; base + 0 0inal, dx; andal, f7h; 0outdx, al; aljmpDone ; we are done

SwitchOn:movdx, 3BCh + 0; base + 0 #0inal, dx; oral, 01h; 1outdx, al; Done: popdx; popax; CheckPortendpextern C CheckPort(void);void main(void) {while( 1 ) {CheckPort();}}

PC

Parallel port

Pin 13

Pin 2

Switch

LED

8086CPU

EU ALUEUBIU208 1616ALUS SD SE SI PC S8086213645AXBXDXCX

ARMIRQFIQR13_svcR14_svcSPSR_svcSPSR_abtR13_abtR14_abtSPSR_undR13_undR14_undR13_IRQR14_irqSPSR_irqR13_fiqR14_fiqR11_fiqR12_fiqR9_fiqR10_fiqR8_fiqSPSR_fiq

Intel PXA255 SOC

. MOV Rn, directMOV @Rn, RmADD Rn, Rm0000Rndirect0010Rn0100RmRnRn = M(direct)Rn = Rn + RmSUB Rn, Rm0101RmRn = Rn - RmMOV Rn, #immed.0011RnimmediateRn = immediate.JZ Rn, relative0110RnrelativePC = PC+ (only if Rn is 0)RnMOV direct, Rn0001RndirectM(direct) = RnRmM(Rn) = Rm

.

ISS#include typedef struct { unsigned char first_byte, second_byte;} instruction;

instruction program[1024]; //unsigned char memory[256]; //

int run_program(int num_bytes) {

int pc = -1; unsigned char reg[16], fb, sb; while( ++pc < (num_bytes / 2) ) { fb = program[pc].first_byte; sb = program[pc].second_byte; switch( fb >> 4 ) { case 0: reg[fb & 0x0f] = memory[sb]; break; case 1: memory[sb] = reg[fb & 0x0f]; break; case 2: memory[reg[fb & 0x0f]] = reg[sb >> 4]; break; case 3: reg[fb & 0x0f] = sb; break; case 4: reg[fb & 0x0f] += reg[sb >> 4]; break; case 5: reg[fb & 0x0f] -= reg[sb >> 4]; break; case 6: pc += sb; break; default: return 1;

} } return 0;}

int main(int argc, char *argv[]) {

FILE* ifs;

If( argc != 2 || (ifs = fopen(argv[1], rb) == NULL ) { return 1; } if (run_program(fread(program, sizeof(program)ifs)) == 0) {print_memory_contents();return(0); } else return(-1);}

IP1. 1. 2. 3. 2.Datapath

1.1.1 1.2 ALU ALU, 1.3

1.1 1.2 1.2.1Fetch: IR1.2.2 Decode: 1.2.3Fetch: datapath1.2.4Execute: ALU1.2.5Store results:

FetchIRPC: IR:

Decode

Fetch operandsdatapath registersExecute ALU

EG. ALU80868051

Cache RAM copy

:1. 2. speedUP3. ALUsSuperscalar VLIW: 4.

1.2. 3.4.

1.2.I/O3. 1.2. 1. IXP2800DSP TM32C

1.2. 3.4.

1.: 2.: ?

GPP116 rnrm464K 16 16 161. 2. FSMD ALU 3. 4.