. 1

Boole - - Karnaugh - - - Flip Flops.

Boole ( , , .)

. .

.

.

,

, LOW HIGH .

,

.

, LOW HIGH

on off . ,

, "1" "0".

, ('), AND( ), OR(+)

. '

, .

,

Boole George Boole.

Boole : ) ( ) ' ) AND ( )

. ) OR ( ) +

, "0", "1"

"1", "0". ,

: = '

AND

AND

"1", "1".

, AND :

. 2

OR

OR "1",

"1". , OR : = +

AND OR

AND 1 OR 0

x 1 = 1 x = x

x + 0 = 0 + x = x

AND OR

AND OR OR

AND.

x (y + z) = (x y) + (x z)

x + (y z) = (x + y) (x + z)

( )

x x' :

x x' = 0

x + x' = 1

1 2

x x = x x 0 = 0

x + x = x x + 1 = 1

De Morgan

(x y)' = x' + y' (x y z)' = x' + y' + z'

(x + y)' = x' y' (x + y + z)' = x' y' z'

. (

IC) , «chip»,

( , , ) . chip

, chip

«pins» . pins 14 '

IC 64 . IC

, .

. 3

, , ,

. :

(Small Scale Integration SSI) 10 .

(Medium – Scale Integration MSI)

10 100 .

(Large – Scale Integration LSI)

100 .

(Very Large – Scale Integration VLSI)

.

(AND, OR .) « » .

.

( ) , .

: TTL CMOS.

: TTL (Transistor – Transistor Logic)

L , . L

chip

.

chip TTL « » 5400 7400.

, ,

. chips 7400 7400, 7401, 7402 . , 7400

NAND 2- , 7404 . L

5V .

TTL, , ( «0»)

0,8V, ( «1») 2,0V

5,5V. 0,4V 2,4V

5,5V, .

TL . standard TTL

74 Schottky

74LS. TTL ,

, .

. 4

. . 7486 74LS86

XOR .

: CMOS (Complementary MOS)

MOS (CMOS) PMOS NMOS

. PMOS NMOS MOSFET P

. S

, ,

. CMOS

+3V +15V. 0 30%

«0», 70% 100% «1» . ,

5V, 0 1,5V,

3,5V 5V. . ,

5V, 5V 0V.

4000 CMOS TTL. TTL

CMOS

TTL. A , CMOS

74 C 74HCT. H 74 C , 74 CT

L.

74 CT TTL .

fan-out. fan-out C

« » . fan-out TTL

10, 10 -

. fan-out L 10. fan-out

Schottky TTL (LS – TTL) 20 4000 CMOS 50.

. 5

( ) , CMOS

TTL. ' .

. TTL CMOS CMOS L

1 LS-TTL CMOS.

pull-up 2,2k ( Standard TTL 1k ).

HIGH TTL 5V

CMOS IC. 2 CMOS ( )

LS-TTL. IC CMOS (Standard) TTL .

CD4050 3. TTL CMOS,

pull-up CMOS 74HCT00

4 IC 74HCT34.

. TTL ( IC 7404).

( 0 1)

, 12ns.

, 7ns.

. 6

.

,

, .

AND (4081, 4073, 4082, 7408, 7411, 7421) ,

Boole, ,

. .

AND ( ) AND ( ) .

AND 1,

1. 0, 0.

, ,

AND : Y = A B

AND :

AND

,

0

1 1.

: G = A B C D

4

2 ,

3 AND

: G = (A B) (C D).

:

. 7

AND CMOS CD4081, CD4073, CD4082

AND CMOS 74HC08, 74HC11, 74HC21

. 8

AND TTL compatible 74LS08, 74LS11, 74LS21, 74HCT08, 74HCT11, 74HCT21

OR (4071, 4075, 4072, 7432) OR ( )

OR ('H) : = +

OR ('H) "1" (High), "1" (High) "1" (High).

OR :

OR

, 1

1 0

0.

: Y = (A + B) C

3

2 .

OR: G = A + B

G C AND: Y = G C

:

. 9

OR CMOS CD4071, CD4075, CD4072

OR CMOS 74HC32

. 10

OR TTL compatible 74LS32, 74HCT32

NOT (4069, 7404, 7414)

( ) ( ) : = '

.

:

( )

, .

2 ,

. = G' = (A')' = A

: F = A' B' C + A C'

D ,

AND, NOT, OR.

F, :

) 3 , , C. ) 2 AND 3

A B C A C D ) 1 OR ( + )

.

. 11

3 , :

NOT CMOS CD4069, 74HC04 TTL compatible 74HCT04

. 12

NOT with Schimitt trigger input CMOS 74HC14 TTL compatible 74LS14, 74HCT14

NAND (4011, 4023, 4012, 4093, 7400, 7410,

7420, 74132) NAND (NOT AND)

AND, OR, NOT

. NAND

AND.

AND AND

.

NAND : Y = (A B)' NAND

:

NAND 1

0.

NAND

AND,

OR, NOT NAND. NAND

.

. 13

, AND, OR NAND

.

NAND

AND,

OR, NOT.

NAND OR

NAND , De

Morgan: Y = (A B)' = A' + B' NAND 2

OR, :

NAND CMOS CD4011, CD4023, CD4012

. 14

NAND CMOS 74HC00, 74HC10, 74HC20

NAND TTL compatible 74LS00, 74LS10, 74LS20, 74HCT00, 74HCT10, 74HCT20

. 15

NAND with Schimitt trigger input CD4093, 74HC132, 74LS132, 74HCT132

NOR (4001, 4025, 4002, 7402, 7427)

R (NOT OR) H NOR OR .

NOR : = ( + )'

OR .

:

NOR 1 0

. 16

NOR CMOS CD4001, CD4025, CD4002

NOR CMOS 74HC02, 74HC27

. 17

NOR TTL compatible 74LS02, 74LS27, 74HCT02, 74HCT27

XOR XNOR (4070, 7486, 4077)

XOR XOR (exclusive OR) "1",

( ' ). XOR :

XOR :

. 18

XOR CMOS CD4070, 74HC86 TTL compatible 74LS86, 74HCT86

XNOR XNOR (exclusive NOR) "1", ( '

). XNOR :

X OR :

. 19

XNOR CMOS CD4077

(74HC/HCT153, 74HC/HCT253, 74HC/HCT151, 74HC/HCT251)

(Multiplexer - MUX) 2n , n

( ) . ,

. 2n 1

2n .

4

4 (MUX 4X1) 0, 1, 2 3 S0 S1

, :

S1 S0,

0, 1, 2 3

,

:

S0 S1 0, 1, 2 3 :

Y = I0 S'1 S'0 + I1 S'1 S0 + I2 S1 S'0 + I3 S1 S0

. 20

, 4 1 ,

AND OR , :

8

8 (MUX 8X1) 0, 1, 2, 3, 4, 5, 6 7 S0,

S1 S2 , :

S0, S1 S2, 0,

1, 2, 3, 4, 5, 6 7

, :

, C: Y(A,B,C) = A' B' C' +

A' C + A C

:

. 21

: n=3. ,

8 (MUX 8X1) .

, C . 0, 1, 2, 3, 4,

5, 6 7 :

"0" "1", .

.

74HC/HCT153 74HC/HCT153

(S0, S1). active LOW

(1 , 2 ). (1 , 2 ) LOW HIGH.

74HC/HCT253

. 22

74HC/HCT253

(S0, S1). (1O , 2O )

HIGH (OFF-state).

74HC/HCT151 74HC/HCT151 (S0, S1, S2)

( ) ( ). active LOW

( ). ( ) LOW HIGH.

74HC/HCT251

74HC/HCT251 (S0, S1, S2)

( ) ( ). (O )

HIGH (OFF-state).

. 23

(74HC/HCT147, 74HC/HCT148)

(Encoder) n m (nxm) n m

(n 2m). n , .

m-bits .

8 3 8 3 (n=8) (m=3)

,

8 3

:

. 24

8 3 :

D3 = I4 +I5 +I6 +I7

D2 = I2 +I3 +I6 +I7

D1 = I1 +I3 +I5 +I7

8 3 OR

.

BCD 74HC/HCT147

74HC/HCT147 BCD.

.

" ", .

74HC/HCT147 (active LOW).

1-9

BCD ( ) .

. 25

, BCD ( )

. (

"1"), "1". 0.

74HC/HCT147 :

8x3 74HC/HCT148

74HC/HCT148 8x3.

.

" ", .

(active LOW)

(octal 4-2-1) .

. 26

74HC/HCT148 :

(CD4555/6B,

74HC/HCT139-138-238-42-154)

(Demultiplexer - DEMUX) 1X2n , n

2n .

2n , n .

.

1 4

1 4 , 1 0 D0, D1, D2 D3.

bits I1 0 .

. 27

1 4 :

1 4 D0, D1, D2 D3

0 1:

D0 = E I1' I0'

D1 = E I1' I0

D2 = E I1 I0'

D3 = E I1 I0

, 1 4

AND , :

. 28

(Decoder) n m (nXm) n m

(m 2n). n "0" "1",

2n .

.

(m=2n),

3 8, (m<2n),

4 10.

3 8

3 8 . 3 8

C, B 3-bits ( ) D0, D1,

D2, D3, D4, D5, D6 D7. "1" (

) "0".

. 29

3 8 :

3 8 :

D0 = C' B' A'

D1 = C' B' A

D2 = C' A'

D3 = C' A

D4 = C B' A'

D5 = C B' A

D6 = C B A'

D7 = C B A

3 8 (3)

(8) AND (3) ,

. , nX2n n 2n

AND n .

. 30

1x4 CD4555B, CD4556B

CD4555B CD4556B 1x4.

, (enable input) E . CD4555B

HIGH CD4556B LOW.

HIGH CD4555B

LOW CD4556B HIGH.

2-to-4 line 74HC/HCT139

74HC/HCT139 2-to-4 line .

nA0 nA1

(active LOW), nE active

LOW.

nE HIGH HIGH nA0

nA1 . nE 1x4

.

. 31

2-to-8 line 74HC/HCT138

74HC/HCT138 A0, A1, A2

(enableed) ( ),

(antive LOW).

To "138" (enable inputs): active LOW active HIGH.

E1 2 LOW E3 HIGH.

"138" actine LOW

LOW HIGH.

2-to-8 line 74HC/HCT238

74HC/HCT238 74HC/HCT138

(active HIGH).

To "238" (enable inputs): active LOW active HIGH.

E1 2 LOW E3 HIGH.

. 32

BCD (1-of-10) 74HC/HCT42

74HC/HCT42 (active HIGH) (LOW)

active LOW.

"42" BCD "9"

HIGH.

4-to-16-Line 74HC/HCT154

74HC/HCT154 4-to-16-line

(active LOW) (enable inputs) 1 2.

HIGH HIGH

0 3.

0 3

LOW.

. 33

BCD (74LS47,

74LS48, CD4511) 7

(dispays) (7) (segments)

0-9.

.

(LEDs)

. ,

.

(LCDs).

. LCDs

.

BCD 7

BCD 7 (BCD to 7 Segments Decoder)

(display), .

BCD 7 TTL 74(LS)47

74(LS)48 . CMOS CD4511

.

. 34

- BCD 7447 (74LS47) 7448 (74LS48)

TTL 7447A (74LS47) BCD

, TTL 7448 (74LS48) ,

.

:

TTL 7447A (74LS47)

( BI/RBO RBI ):

TTL 7448 (74LS48)

( BI/RBO RBI ):

. 35

BCD D(6), C(2), B(1), A(7)

D (MSB),

(LSB) BCD .

LT LOW, a - g.

BI/RBO . LOW RBI.

BI ( LOW), , OFF (

7447 HIGH 7448 LOW). ( LOW) RBI,

BI/RBO RBO LOW. " " (blanking)

LED .

, , ( ) .

, 7447 ( 7448) .

(ripple) RBI RBO

, .

, RBI IC6 .

RBI LOW BCD LOW ( 0),

. RBO LOW, RBI

(IC5). , 0000 IC5 RBI LOW, .

RBO IC5 LOW RBI IC4.

RBI LOW, IC4 , BCD 0011. RBO HIGH

IC3.

BCD IC1 0000 .

RBI ( LOW).

. 36

- BCD CD4511 CMOS CD4511 BCD

, .

:

o BCD D(6), C(2), B(1), A(7)

D (MSB),

(LSB) BCD .

LT LOW, ,

. LOW LT HIGH

( ).

LE LOW, BCD

. LE HIGH

BCD

LE LOW HIGH.

CD4511

.

. 37

D Flip - Flops (4013, 74HC/HCT74)

.

.

:

--- (synchronous sequential circuits)

--- (asynchronous sequential circuits)

' (latches).

flip-flops. To flip-flop

( 1 bit ).

.

(flip-flops) .

SR NOR

(latch) NOR, :

Q. ,

:

(set) Q=1 Q'=0

(reset) (clear) Q=0 Q'=1

NOR

1. S=0 R=0 . ,

, S=0 R=0.

2. S=0 R=1 . Q=0 ( ) Q=0

. 38

3. S=1 R=0 . Q=1 ( ) Q=1

4. S=1 R=1 . Q=0 Q'=0.

.

( Q=0 Q'=0) S=1 R=1 .

.

NOR, .

SR AND,

, SR,

:

CP 0, S1 R1 ,

S R. CP=0.

1 CP, S1 R1 S R .

.

SR

D. RS

S R D S SR.

. 39

, D=1 S=1 R=0,

Q=1. D=0, S=0 R=1, Q=0.

D Q D CP=1. CP

0, CP 1.

Flip - Flops

, D CP=0,

Q D CP=1.

D .

D ,

(level sensitivity)

,

. :

, "0" "1"

, "1" "0" .

(edge-triggering). Flip-

Flops.

. 40

, D Flip-Flop master-slave.

D. master (" ")

Clock=1. , slave (" ") Clock=0.

"1", master D slave

. "0", master

D. , slave Qm ( master)

. Qm Clock=0, slave

.

D Flip - Flops

D Flip-Flop , D

Q, , .

D Flip-Flop Q(n), ,

Q(n+1)

D Flip-Flop . Flip-Flop

, Flip-Flop

.

D Flip-Flop :

D D flip-flop ,

flip-flops CP .

. 41

D flip-flops , (SET

RESET) , flip-flops

.

flip-flop

flip-flops ( )

.

(PRESET) flip-flop (Q=1).

(CLEAR) Flip-Flop (Q=0).

D Flip - Flop CD4013

CD4013 CMOS Flip - flop. flip-flop

data clock, set reset,

Q Q. :

D Q

CLOCK. CLOCK schmitt trigger. HIGH

SET RESET, flip-flop set reset

. flip-flop :

. 42

D Flip - Flop 74HC/HCT74

74HC/HCT74 flip-flop,

data (D), clock (CP) set (SD) reset (RD) Q

Q. :

set reset LOW

data (D) clock (CP). D Q LOW

HIGH . Schmitt-trigger

. flip-flop

:

. 43

JK T Flip - flops (4027, 74HC/HCT73, 74HC/HCT112) J - K Flip - flops

S-R Flip-Flop (S=1 R=1) J-K Flip-Flop. '

J (set) (reset) J=1 =1, Flip-Flop (

Q=0 Q=1 ). J-K Flip-Flop S-R Flip-Flop.

J-K Flip-Flop :

1. J=0 =0, .

2. J=0 =1, Q=0.

3. J=1 =0, Q=1.

4. J=1 =1, Flip-Flop ,

.

J-K Flip-Flop .

J-K Flip-Flop :

T Flip - flops

J-K Flip-Flop , J-K Flip-Flop, Flip-Flop.

T Flip-Flop J-K Flip-Flop J K,

:

. 44

Flip-Flop :

1. =0, .

2. =1, Flip-Flop ,

.

T Flip-Flop (Toggle) .

Flip-Flop .

Flip-Flop :

J, K, D flip-flops ,

flip-flops CP .

flip-flops

, flip-flops .

flip-flop

flip-flops ( )

. :

(PRESET) flip-flop (Q=1).

(CLEAR) Flip-Flop (Q=0).

. 45

JK flip - flop CD4027 CD4027 J-K master-slave flip-flop

. flip-flop J, K, clock

SET RESET.

HIGH. SET RESET HIGH flip-flop

preset clear . HIGH.

:

flip-flop :

JK flip - flop 74HC/HCT73

74HC/HCT73 JK flip -flop

. J, clock (CP), reset (R)

Q Q.

reset (R) LOW. LOW J, K clock

flip-flop Clear Q LOW.

. 46

schmitt-trigger clock

.

:

flip-flop :

JK flip - flop 74HC/HCT112 74HC/HCT112 J-K flip-flops

. LOW S R flip-flop

(PRESET) (CLEAR) , J, K, clock.

S R HIGH, J K

, JK flip-flop.

:

. 47

flip-flop :

(clocks) . (

– binary counters), ( – Binary Coded Decimal

(BCD) counters). ,

(input), .

.

(counters) : ) (asynchronous counters)

(synchronous counters). flip-flops

.

. 48

, flip-flops, (

), flip-flops

. , flip-flops, ,

, flip-flop, flip-flops

, (ripple) flip-

flop .

(asynchronous) (binary) (counter)

flip-flops. 4 J-K flip-flops

.

flip-flop, flip-flops

flip-flop.

flip-flop flip-flop. flip-flops

(ripple).

J-K flip-flops «toggle» J=K=1

), .

. Q4, Q3, Q2, Q1 flip-flops

4-bits Q4Q3Q2Q1 ( Q4 MSB Q1 LSB)

. 49

:

Q1 ( J=K=1) .

, flip-flop 1 «0» «1», flip-flops

. , ,

: Q4Q3Q2Q1=0001

, flip-flop 1 . Q1 «1»

«0» ( ) flip-flop 2,

flip-flop 2 «0» «1». flip-flops

. ,

, : Q4Q3Q2Q1=0010

, flip-flop 1 . Q1 «0» «1»

flip-flop 2) flip-flop 2 .

flip-flops

. , (clock), :

Q4Q3Q2Q1=0011.

flip-flops

«1». , flip-flops «0»

.

. 50

’ , ,

.

BCD

BCD , 0 9,

0. BCD ( ) 4 flip-flops,

bits 10 .

, .

Q4Q3Q2Q1 flip-flops .

bits

BCD 9

. BCD flip-flops

.

BCD

bits. BCD .

. 51

J-K flip-flops J=K=1. BCD

bits,

NAND. flip-flops ,

Q4Q3Q2Q1=1001. (

flip-flops 1001, NAND, 1010

).

, Q4Q3Q2Q1=1010, NAND

«0» ( Q4 Q2). NAND

flip-flops, flip-flops «0» Q4Q3Q2Q1=0000.

Q4Q3Q2Q1=1001, NAND «1»,

flip-flops .

,

.

CP flip-flops .

,

flip-flops ,

. (up-counters)

, .

J-K flip-flops. J-K flip-flop ( )

J=K= «1».

flip-flops ,

J flip-flops .

. J-K

flip-flops bits. bit

( ) . J K

flip-flop FF1 «1» . flip-flop ( )

, bits flip-flops «1».

. 52

Q4Q3Q2Q1=0011

Q4Q3Q2Q1=0100. Q1 , Q2 Q1=1, Q3 Q2Q1=11 Q4

Q3Q2Q1=011 ( «1»).

bits. flip-flops

. J FF1 «1», ,

, .

flip-flops ,

flip-flops «1». AND

J flip-flops flip-flop

AND. AND

.

bits.

(down-counter)

. J-K flip-flops .

. 53

flip-flops .

( Q4Q3Q2Q1=1111).

,

.

modulo N modulo

( ). modulo N

( 0 -1). bits

16 ( 0 15) ’ modulo

. 54

16. O BCD 10 ( 0 9) ’

modulo 10.

. modulo.

modulo 16. 0000 .

1100.

;

12 (1100=1210). 12 28 (

=16 +12 ) 44 ( = 2 16 + 12) .

( 0 15) .

flip-flops modulo N 2 . , flip-flops

modulo 8,

modulo 7, modulo6 modulo 5. modulo 4 flip-flops.

modulo

modulo 5

modulo 8, , .

modulo 8 flip-flops (clear) «0».

0 7.

modulo 8 5 flip-flops

NAND Q3 Q2 Q1.

Q3Q2Q1=101 ( 5 ), Q3Q2Q1=111 NAND «0»

. ,

5 101 000 (

). 0 4 modulo 5.

modulo.

. 55

bits.

bits, .

flip-flops

, , flip-flop

2. ,

, . flip-flop

f, flip-flop f/2, flip-flop f/4 , f/8 .

. 56600 z, 28800Hz, 14400Hz,

7200Hz.

. 4 ,

bits

, . 113200 z,

. flip-flop 113200Hz/2= 56600Hz,

113200 z/2= 28800Hz, flip-flop 113200Hz/8=

14400Hz flip-flop 113200Hz/16= 7200Hz. (

bits ).

. 56

CD4040 CD4060 CMOS CD4040 12-stage CMOS

CD4060 14-stage ,

Q1, Q2, Q3 Q11. (reset) "1"

RESET (CT=0), clock. H clock CD4040 schmitt

triger. 8MHz (VDD=10V).

1.0V 15V.

CD4040 :

,

CD4040, Q:

CD4060 :

. 57

,

CD4060, Q:

CD4060,

- .

CD4017B

CD4017B CMOS 10

.

. 58

CLOCK ,

. "1" .

10 CLOCK.

RESET ' ,

"1", CLOCK.

CD4017B, :

CLOCK

,

:

CD4017B

RESET,

,

RESET

"0".