内容与要点

主要内容：– DSP Builder 工具介绍；设计流程；设计规范；模

块库；设计实例。

本章要点：– DSP Builder 设计流程、规范； Simulink 模型仿

真；利用 MATLAB 建模工具和 DSP Builder 开发环境，认识如何将算法级仿真向硬件模块实现过渡的设计过程。

目录 (1)

第一节、 第一节、 DSP BuilderDSP Builder 概述概述– DSP Builder 概述

– DSP Builder 特性

– DSP Builder 设计流程

– DSP Builder 软件安装

– 实例

目录 (2)

第二节、 第二节、 Altera DSP BuilderAltera DSP Builder 模块库模块库– AltLab 库– 算术库– 总线控制库– 复信号处理库– Rate Change 模块库– 状态机函数库– 存储器 (Storage ）模块库– MegaCore 函数支持– 其它库

Implementing DSP Designs

in FPGA

Overview

The Programmable Solutions Company®

Devices (continued)– MAX® II– Mercury™ Devices– ACEX® Devices– FLEX® Devices– MAX Devices

Tools– Quartus® II Software– SOPC Builder– DSP Builder– Nios II IDE

Intellectual Property (IP)– Signal Processing– Communications– Embedded Processors

Nios®, Nios II

Devices– Stratix® II™

– Cyclone™ II– Stratix GX– Stratix– Cyclone

Agenda

Overview Designing with DSP Builder Library Blocks Simulating & Debugging with DSP Builder Intellectual Property (IP) Implementation FIR, NCO and FFT IP Functions

Appendix Introduction to Altera Devices Hardware Acceleration Using Nios II

What Is a DSP Processor?

Microprocessor With Specialized Instructions & Hardware for DSP Applications

Optimized For High-Performance, Repetitive and Numerically Intensive Tasks

Hardware– Fixed & Floating Point Multipliers– Co-Processors– Special Memory Structures

Multiple Access Memories For Faster Computations Run Arithmetic Calculations Faster than General

Processors

What Is an FPGA?

Field Programmable Gate Array

Device that Has a Regular Architecture (Set of Blocks)

that Can Be Programmed for Various Functions

“Glue” Logic

Customizable Hardware Solution

Configurable Processors

MAC MAC

MAC MAC

Can implement hundreds of MAC functions in an FPGA

Parallel implementation allows for faster throughput

– 200 Tap FIR Filter would need 1 clock cycle per sample

1-8 Multipliers Needs looping for more than 8

multiplications Needs multiple clock cycles

because of serial computation 200 Tap FIR Filter would need

25+ clock cycles per sample with an 8 MAC unit processor

MAC MAC MAC MAC MAC MAC MAC MAC

MAC MAC MAC MAC MAC MAC MAC MAC

MAC MAC MAC MAC MAC MAC MAC MAC

MAC MAC MAC MAC MAC MAC MAC MAC

High Speed DSP Processor

High Level of Parallel Processing in FPGA

DSP Processors vs. FPGAs

100 -

Complete Hardware Implementation

Per

form

ance

(M

MA

Cs/

sec)

600 -

Embedded Processors

Embedded Processors Hardware Acceleration

New!New!

Extending Range of Altera Reconfigurable DSP SolutionsExtending Range of Altera Reconfigurable DSP Solutions

FPGA / DSP Challenges

Designing With FPGAs Is Different!!– Different Set of Tools

– C-Code vs. VHDL / Verilog

1) System-Level Development & Verification

2) Software/Hardware Co-Development

3) Software Design Optimization

Addressing Challenges

1) System-level Development & Verification

– DSP Builder Tool

System Integration

Bit-true & Cycle Accurate Models

Automatic Translation into Hardware

2) Hardware/Software Integration

– SOPC Builder Tool & Nios® II Processor

3) Design Optimization

– Hardware Acceleration

– Flexibility in System Partitioning

Matlab Simulink

Overview

Implementing DSP

Designs in FPGAs

Implementing DSP

Designs in FPGAs

The Mathworks

Headquarters in Natick, near Boston

Founded in 1984, Privately Held

Over 1000 employees Direct Offices in UK, France,

Italy, Germany, Switzerland, Spain, & Benelux

Distributors in 20 Countries

The Mathworks Product Family

StateflowStateflowStateflow

BlocksetsCode Generation, RTW, SF Coder

Toolboxes

Desktop ApplicationsAutomated Reports

DAQ cardsInstruments

*Slide Courtesy of The MathWorks

Validated Design

DSP/EmbeddedSoftware Tools

EDA Tools

Digital, A/M-SHardware

DSP, ControlSoftware

THIRD PARTYIMPLEMENTATION

TOOLS

System-Level Design

MATLABAlgorithm Development

and Analysis

SIMULINK

The Mathworks Design Environment

Top-Down Design

Design & Test System Behavior

Early in the Design Process

– Create Validated Reference

Design

Detect Design Flaws Early

Reduced Design Risk & Cost

Reduced Time-to-Market

MATLAB Environment

Results of CommandsErrors, etc.

Variables

Command History

Current Working Directory

Simulink

Simulink

Hierarchical Block

Diagram Design &

Simulation Tool

Digital, Analog/Mixed

Signal & Event Driven

Visualize Signals

Integrated with MATLAB

Simulink Blockset Libraries Simulink

– Sources– Sinks– Continuous– Discrete– Non-Linear– Math

……………………

…………………… Fixed-Point Blockset DSP Blockset Communications Blockset SimPowerSystems Blockset Others

Altera DSP Builder

Matlab / Simulink Model Created with Altera DSP Builder Libraries Matlab / Simulink Model Created with Altera DSP Builder Libraries

Design Flow with DSP Builder

( 八步法 )

What Is DSP Builder?

Links MATLAB/Simulink Design Environment to

Quartus II Development Tool for Altera FPGAs

Automatic HDL Code Generation from Simulink Model Generated by DSP Builder Libraries

Generates Bit & Cycle Accurate Models for DSP Functions

Automatic Generation of HDL Testbench

Integrated Intellectual Property (IP) Library Support

Enables Rapid Prototyping with Altera DSP Development Board

Facilitates Integration of Complex DSP Functions

HDL Synthesis

Verify in Hardware

Place and Route

Creates Simulation Testbench

DSP Builder Overview

Creates HDL Code

Download Design to DSP Development Kits

Creates SOPC Builder Ready Component

Altera DSP Builder Libraries AltLab Arithmetic Boards Complex Type Gate & Control IO & Bus Rate Change SOPC Builder Links State Machine Functions Storage MegaCore Functions Video and Image Processing

Design Flow Overview

1) Create Design in Simulink Using Altera Libraries

2) Simulate in Simulink

3) Add Signal Compiler to Model

4) Create HDL Code & Generate Testbench

5) Perform RTL Simulation

6) Synthesize HDL Code & Place & Route

7) Program Device

8) Signal Tap II Logic Analyzer

Step 1- Create Design in Simulink Using Altera Libraries

Drag & Drop Library Blocks into Simulink Design & Parameterize Each Block

Parameterization of IP Megacores

Step 2 - Simulate in Simulink

Step 3 - Add “Signal Compiler” to Model to Generate HDL code • Stratix & Stratix II

• Stratix GX• Cyclone & Cyclone II• ACEX 1K• Mercury• FLEX10K & FLEX 6000• Development Boards• APEX20K/E/C• APEX II

Message Window

• Leonardo Spectrum• Synplify• Precision• Quartus II

Testbench Generation

• Speed• Area• Balanced• Fast fit – No timing optimiz

ation• Use Current Quartus II proj

ect

Step 4 - Create HDL Code & Generate Testbench

altrfir32.vhd

altrfir32.mdl

Enable "Generate Stimuli for VHDL Testbench" Button

HDL Code Generation

DSP Builder Report File

Lists All Converted Blocks– Port Widths– Sampling Frequencies– Warnings & Messages

Step 5 – Perform RTL Simulation ( ModelSim )

1) Set working directory (File => Change Directory)

2) Run TCL file (Tools => Execute Macro)

Perform VerificationModelSim vs Simulin

k

Step 6 - Synthesize HDL & Place & Route

– Synthesis

• Leonardo Spectrum

• Synplify• Quartus II

– Quartus II Fitter

Step 7 – Program Device

Download Design to DSP Development

Kits

Step 8 - SignalTap II Logic Analyzer

Embedded Logic Analyzer

– Downloads into Device with Design

– Captures State of Internal Nodes

– Uses JTAG for Communication

SignalTap II Logic AnalyzerSignalTap II Logic Analyzer

Imported Data

Imported Plot

Analysis of Imported Data

Design Flow Review with DSP Builder

1) Create Design in Simulink Using Altera Libraries

2) Simulate in Simulink

3) Add Signal Compiler to Model

4) Create HDL Code & Generate Testbench

5) Perform RTL Simulation

6) Synthesize HDL Code & Place & Route

7) Program Device

8) Signal Tap II Logic Analyzer

Quartus II Assignments Settings

Stratix II DSP Development Board

Stratix II DSP Board Block Diagram

Demos Provided with DSP Builder

第二节 Altera DSP Builder 模块库

– AltLab 库– 算术库– 总线控制库– 复信号处理库– Rate Change 模块库– 状态机函数库– 存储器 (Storage ）模块库– MegaCore 函数支持– 其它

Altera DSP Builder Libraries

AltLab Arithmetic Boards Complex Type Gate & Control IO & Bus Rate Change SOPC Builder Links State Machine Functions Storage MegaCore Functions Video and Image Processing

1 、 AltLab 库 (1)

AltLab 库中的模块用于管理设计层次，并产生用于综合和仿真的 RTL 级的 VHDL 表述。

AltLab Library

Signal Compiler HDL SubSystem

– Build Hierarchical System HDL Import SignalTap II Block SignalTap II Analysis BP: Bus Probe Device programmer HIL Quartus II Global Project Assignment Quartus II Pinout Assignment VcdSink SubSystem Builder

– Creates Black-Box

1 、 AltLab 库 (2)

SignalCompilerSignalCompiler 模块模块 SignalCompiler 模块为 DSP Builder 的核心模块， 完成如下功能：

– 将 Simulink 模型转换为可综合的 RTL VHDL ；– 生成 VHDL testbenches ；– 生成 Verilog testbenches ；– 通过 Quartus® II 生成 Verilog HDL 仿真模型；– 将 Simulink 激励转换为 VHDL testbench 并生成 txt 格式的期望响应；– 生成 Tcl 脚本用于 Quartus II 的编译；– 生成适用于 LeonardoSpectrum 、 Precision RTL Synthesis 、 Synplify

和 ModelSim® 进行仿真的 Tcl 脚本；– 生成 Quartus II 仿真的波形文件；– 生成 PTF 配置文件，可将模型导入 SOPC Builder ；– 允许生成 SignalTap II (.stp) 文件；– 生成 Quartus II 模块符号文件 (.bsf) 。

1 、 AltLab 库 (3)

Update Diagram ： SignalCompiler模块是否对 Simulink 模型重新进行仿真再提取 DSP Builder 模块的信息。

Analyze ： SignalCompiler 模块读取当前仿真模型的 mdl 文件，测试模型的层次信息以及所有 DSP Builder 模块的采样时间。每次改变模型后都必须重新进行分析操作。

Skip Analyze ：跳过模型分析。

Update Diagram ： SignalCompiler模块是否对 Simulink 模型重新进行仿真再提取 DSP Builder 模块的信息。

Analyze ： SignalCompiler 模块读取当前仿真模型的 mdl 文件，测试模型的层次信息以及所有 DSP Builder 模块的采样时间。每次改变模型后都必须重新进行分析操作。

Skip Analyze ：跳过模型分析。

SignalCompilerSignalCompiler 模块模块 创建完 Simulink 仿真模型后利用 Simulink 进行仿真，如果无误

需要转换为 VHDL 实现时，可双击 SignalCompiler 模块或者调用 sc_altera 函数。运行界面如下图

1 、 AltLab 库 (4)

• 在菜单栏左边的工程设置选项中可以选择目标器件的类型、用于综合的综合器、综合与适配的优化目标、主时钟周期、全局复位电平、 reset 是否接地、是否嵌入SignalTap II 逻辑分析仪、是否生成测试激励、是否生成 SOPC ptf 文件、是否生成 Verilog 文件。• 在右边的硬件编译部分给出了 Signal Compiler 模块的工作流程 , 首先点击第一步，将 MDL 转换为 VHDL ，同时会生成Tcl 脚本文件 ; 第二步进行 VHDL 的综合；第三步调用 Quartus II 进行综合；如果目标器件为 DSP 开发板则可以直接将代码下载到 DSP 开发板上。• 底部的 Project Info 给出了当前系统的信息； Report File 给出了 SignalCompiler 转换后的硬件信息。

• 在菜单栏左边的工程设置选项中可以选择目标器件的类型、用于综合的综合器、综合与适配的优化目标、主时钟周期、全局复位电平、 reset 是否接地、是否嵌入SignalTap II 逻辑分析仪、是否生成测试激励、是否生成 SOPC ptf 文件、是否生成 Verilog 文件。• 在右边的硬件编译部分给出了 Signal Compiler 模块的工作流程 , 首先点击第一步，将 MDL 转换为 VHDL ，同时会生成Tcl 脚本文件 ; 第二步进行 VHDL 的综合；第三步调用 Quartus II 进行综合；如果目标器件为 DSP 开发板则可以直接将代码下载到 DSP 开发板上。• 底部的 Project Info 给出了当前系统的信息； Report File 给出了 SignalCompiler 转换后的硬件信息。

AltLab – HDL SubSystem

Create Hierarchical Design Separate HDL Code for Each Subsystem

AltLab – HDL SubSystem (cont.)

Defines Boundary for Lower-Level File

2 、算术库

算术库包括二进制补码有符号算术模块，如乘法器、加法器。有些模块有 Use Dedicated Circ

uitry 这一选项，即此类模块可以利用 Altera® t

ratix® II 、 Stratix 、 St

ratix GX 、 Cyclone II

的模块如 DSP 模块来实现。

Arithmetic Library

Comparator Divide Gain Increment Decrement Magnitude Multiply Accumulate Multiply Add Parallel Adder Subtract

or Product Sum of Partial Products Integrator Differentiator

Arithmetic Library– Multiply Add

2-4

Option to use DSP Blocks if target device is Stratix

Option to use constant values specified as a MATLAB array

•Signed Integer•Unsigned Integer•Signed Fractional

•Add Add•Add Sub •Sub Add•Sub Sub

•No Register•Inputs Only•Multiplier Only•Adder Only•Inputs and Multiplier•Inputs and Adder•Multipliers and Adder•Inputs Multiplier and Adder

Arithmetic LibraryDifferentiator & Integrator Blocks

Ex: CIC Filter （级联积分梳状滤波器 ）

Arithmetic LibraryAdder & Gain Blocks

Ex: IIR Filter （无限脉冲响应滤波器 ）

3 、 I/O 与总线控制模块库

主要是控制信号和总线来完成诸如截位、饱和、 bit 提取、总线类型转换等操作。

Bus Manipulation – AltBus

AltBus Modes

Input & Output Port– Defines Hardware Boundaries– Converts Floating-Point to Fixed-Point

Internal Node– Defines Internal Hardware Node Widths– Converts SBF Formats

Constant– Implements Constants in Hardware

Black Box– Defined Later

Bus Manipulation – Bus Conversion

•Signed Integer•Unsigned Integer•Signed Fractional

•ON: Output is rounded away from zero.

•OFF: LSB truncated <int>(input + 0.5)

•ON: If Output >Max. Positive value,• Output = Max Positive Value• Else Output < Min. Negative value• Output = Min. Negative value•OFF: MSB truncated

IO & Bus Library (cont.)Ex: Floating Point Operation

Ex: Floating Point Operationwith IO & Bus Library Blocks (Cont.)

BP: Bus Probe

4 、复信号处理库

Complex Signals Library

Butterfly

Complex Multiplexer

Complex Conjugate

Complex Delay

Complex Product

Complex AddSub

Complex Constant

Complex to Real-imag

Real-imag to Complex

ButterFly

Implement Decimation in Time FFT Butterfly

a,b,W,A,B Are Complex Number (Signed Integer)– a=x+jX; b=y+jY; W = v+jV– A = a+bW; B = a-bW– A = (x+yv)+YV + j(X+Yv-yV)– B = (x-yv)-YV + j(X-Yv+yV)

Complex – Real-Imag to Complex

X = a + Bj•Conjugate: Conjugate(X) = a - Bj•Invert: Invert(X) = -a - Bj

X = a + Bj Y = C + Dj•Multiply: X * Y = (A*C – B*D) + (A*D + BC)j

Gate & Control Library

Case Statement If Statement Logical Bit Operator Logical Bus Operator Single Pulse LUT N-to-1 Multiplexer 1-to-N Demux Decoder Bitwise Logical Bus Operat

or

Gate & Control LibraryEx: Convolutional Interleaver

5 、存储器（ Storage ）模块库

Storage Library Delay Down Sampling Dual-port RAM FIFO LFSR Sequence LUT Parallel to Serial Pattern ROM EAB Serial to Parallel Shift Taps Up Sampling

Storage – Shift Taps

Specifies the Number of Regularly Spaced Taps Along the Shift Register

Specifies the Distance Between the Regularly Spaced Taps in Clock Cycles

Use Output at the End of Shift Register for Cascading

ROM EAB & Shift Taps BlocksEx: Polyphase Filter

Memory Delay BlockEx: 2D Filter

6 、 Rate Change 模块库 (1)

该库模块允许控制 DSP Builder 模块如 Delay 或 Increment Decrement 模块的时钟。为保证 Simulink 和 VHDL 时钟精度的一致则必须设置 Simulink 的 Solver ，参数设置见图：– 选择 Fixed-step ；– 选择 discrete

(no continuous state) ；– 选择 Single Tasking 模式

6 、 Rate Change 模块库 (2)

ClockAltr 模块 —— 用于仿真模型中加入新的硬件时钟。 PLL 模块—— 可综合出一个基于某一参考时钟的时钟信号。 Multi-Rate DFF 模块 —— 用于采样频率的变化 Tsamp 模块 —— 用于指定内部数据的采样时间。

6 、 Rate Change 模块库 (3)

Variable pll_output_clock0 (defined in block untitled/PLL) = 1e-008Variable pll_output_clock1 (defined in block untitled/PLL) = 4e-008Variable pll_output_clock2 (defined in block untitled/PLL) = 2e-006

Rate Change – Multi-Rate DFF

•Synchronize data path intersectionsinvolving multiple rates

Rate Change – Tsamp & PLL BlocksEx: Polyphase Filter

7 、 SOPC Builder Link （ 1 ）

Nios® II 嵌入式处理器是业界领先的软核高性能、高带宽嵌入式处理器，适合网络、通信核大数据量存储等应用。 Nios 

II 嵌入式处理器包括 RISC CPU 和符合业界标准的 Cygnus 、Red Hat等的 GNUPro 软件。

用户可以使用 SOPC端口库中的模块搭建用户自定义的逻辑模块，且与 SOPC Builder相兼容。 SOPC Builder 支持两种类种类型的用户逻辑模块：– 基于基于 AvalonAvalon 总线的外设；总线的外设；– 基于基于 Nios IINios II 算术逻辑单元和用户指令的用户自定义逻辑。算术逻辑单元和用户指令的用户自定义逻辑。

7 、 SOPC Builder Link （ 2 ） 当把模型文件转换为 VHDL 时， SignalCompiler 生成一个 c

lass.ptf 文件。 Quartus® II 进行综合编译后即可加入 SOPC Builder 。 下图为 DSP Builder & SOPC Builder 设计流程。

DSP Builder & SOPC Builder 设计流程

SOPC Builder Library DSP Acceleration

Custom Peripheral– Interface to Nios Thr

ough Avalon Bus

Custom Instruction– Adds Customized Lo

gic to Nios ALUNios II

Memory

ALU

IQMap

FIR

NCO

c

CustomLogic

+->><<

&

NiosALUa

B

aB

Out

Custom Custom PeripheralPeripheral

Custom Custom InstructionInstruction

What is SOPC Builder?

Avalon Switch Fabric

32-BitProcessor

Ad

dress (32)

Read

Write

Data In

(32)

Data O

ut (32)

IRQ

IRQ

#(6

)

DMA

On Chip ROM

Dev board FLASH

Dev boardSRAM

On Chip RAM

Tri-StateBridge

User Defined

PeripheralUART

SOPC Builder LibraryCustom Instruction

2) Add Custom Instruction Blocks to Simulink Model

SOPC Builder Library Custom Peripheral

2)Add Avalon Ports to Simulink Model

SOPC Builder Library Avalon Blocks

SOPC Builder Library Avalon Blocks

8 、 DSP 板模块库

Board Library

9 、有限状态机

10 、 MegaCore 函数支持 Altera® 的 MegaCore 函数在 Altera 的 PLD 中已经做了严格

的测试和性能优化，所有的 MegaCore 函数都可以通过 Altera的 MegaWizard® Plug-In Manager 进行参数配置。

OpenCore Plus 的评估特点允许用户生成时间有限制的可编程文件，通过这些文件可以进行板级的设计验证，然后再购买 MegaCore 函数的许可证。

DSP Builder 目前有如下的 IP 核：– FIR Compiler ；– IIR Compiler – Reed-Solomon Compiler – Viterbi Compiler – FFT Compiler – NCO Compiler …

Altera’s IP Megafunctions

Shrink-Wrapped Functions Customers can Drop into Altera FPGA Designs

Optimized for Altera Architectures

Easily Parameterized through MegaWizard Plug-in Manager

Megacore IP in DSP Builder

DSP IP Type

FIR Compiler Filtering

FFT/IFFT Compiler Transforms

NCO Compiler Signal Generation

Reed-Solomon Compiler Error Detection/ Correction

Viterbi Compiler Error Detection / Correction

FIR Compiler

1.Generate Floating-Point Coefficients based on Filter Parameters

2. Scale Coefficients to Fixed-Point Values

3. Select Input/Output Specifications

4. Determine Filter Architecture5. Select Output Simulation Files

Numerically Controlled Oscillators (NCO)

Purpose – To Generate a Discrete-Time,

Discrete-Value Waveform Approximating a Continuous Waveform to a Defined Precision

Primary Application Area– Direct Digital Synthesis (DDS) of

Sinusoidal Waveforms- I-Q Modulation- Carrier Recovery- Pilot Generation.

Advanced Features

Black Boxing

Modelling Guidelines

- Clock Design Rules

- Multi-Rate Designs

- Data Width Propagation

- Automatic Sign Extension

- Word Growth

Black-Boxing

What is a “black-box” and why is it used?

Module or Group of Blocks Left Unprocessed by DSP Builder– Surrounding Blocks Still Converted to HDL

Allows HDL Code to Be Added to Simulink Design– Use Blocks, C-Based Model or M-File for Simulink Simul

ation Output Netlist Includes Port Connections to “Black-Box”

– “Black-Box” Code is Inserted by Quartus II Uses Altbus Blocks in Block Box Input Output Mode

Replace With Black BoxReplace With Black Box

Looking Under Black BoxLooking Under Black Box

AltBus Black Box Mode

Black Box Input & Output Port– Creates Black Box

Not Converted to HDLPort Connections Remain

Converted to Signal (Port Connection)

DSP Builder Block Non-DSP Builder Block

Converted to HDL

Converted to Black Box

实验四（上）实验四（上）

低通数字滤波器设计、高通数字滤波器

实验四（下）

基于滤波器的 DTMF 信号检测

本章结束

谢 谢 ！谢 谢 ！

计算机与信息技术学院