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경종민 kyung@ee.kaist.ac.kr

CAD Issues & Algorithms(1)

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CAD Issues & Algorithms

1. Simulation2. Verification3. Synthesis4. Place & Route

Contents

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1. Simulation 1) Circuit Simulation

• Function– DC analysis, AC analysis, noise analysis, transient or time-do

main analysis– very accurate but spends much time

• Method– treat the circuit as a continuous dynamical system and obtai

n a set of nonlinear algebraic-differential equations with electrical variables such as voltage, current, and charge to describe its behavior

– Gaussian eliminiation : O(N3), N:number of nodes– Sparse matrix : O(N1.5), only neighboring nodes have intercon

necting elements to reduce analysis time• SPICE

– the very popular circuit simulation tool developed at Berkeley– HSPICE - most commercially used

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Nonlinear differential equation

f(x,x’,t) = 0

Nonlinear simultaneous equationsg(x) = 0

Linear simultaneous equations

Ax = b

Circuit simulation algorithm

t=t0

Numericalintegration

Newton-Raphsonlinearization

Gaussianelimination

t=tstop

start

stop

t=t+t

No

Yes

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2) Switch-level Simulation

• Motivation– SPICE simulation is too slow for a large digital system.– Logic simulation may give misleading simulation results for syste

ms built from MOS transistors <- bidirectionality of signal flow, charge sharing effects, and transistor sizes.

– Switch-level simulation is the lowest level of digital simulation.

transistor as a gate-controlled switch

0

open switch

1

closed switch

X

indeterminate

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Vdd

gnd

out (4,1)

2

3

(4,0)

Input node : strong signals to the system, ex) Vdd, Gnd, clock

, data inputs

Storage node : state is determined by the

operation of network

Network model

(c, l)c : node capacitance relative to that of other nodes with which it may share charge, Vdd, Gnd has maximum valuel : logic level, one of (0, 1, X)

(s)Edge : transistors : strength, or conductance relative to those of TRs in a ratioed circuit

Range of c and s1<=c<=K, for storage nodesK<s<W, for transistor strengthc = W, for input nodes

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Network partitioning

Gate input is terminated

Each subnetwork is simulated to find steady-state response

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Steady-state response of subnetwork

Strength of conducting path = min(size(root(p)), min(strength of transistors))

. . . .root(p) dest(p)

(4,0)

2 3 5

strength=2 (3,0)

4 4 6

strength=3

Strength and level of storage node

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1

3 5

4 (5,1)maximum strength = 5same input values 1,1,1

00

0

2 3

4(4,0)

01

1

3 2

2 (3,X)conflicting input values 0,1,1

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3) Logic Simulation

• Simulation model– using logic gate model - AND, OR, NOT, NAND, NOR,

Flip-Flop, etc.– I/O value representation - Boolean logic value: 0, 1,

X(unknown)– time - integer, defined by a multiple of unit delay

• Classification by delay consideration– unit-delay simulator

i) assumes that each component has a unit delayii) avoids modeling any circuit delaysiii) simulates function but not performance

– variable-delay simulatori) allow components to have arbitrary delaysii) allow for more accurate modeling of fast-changing nets

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• Delay model– model delays physically occurring in logic gates– enable accurate performance analysis of the logic

designed– embedded in logic simulation engines– transport delay, ambiguity delay, rise-fall delay,

inertial delay

AB

Z Z'T

Transport delay

A B

A

B

B

Inertial delayminimum duration for changing gate state

I=1, T=1

I=4

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• Event-driven simulation– evaluate a component only when an even occurs on its input– keep track of event on a time wheel, which stores event in time order– spin the time wheel forward to the next time slot with an event, and

start simulating from there– evaluating a component can cause a new event to be added to later

slots in the time wheel for later action

ab

d

0

1

1

00

e

f g

1H

t=0t=1

t=4,5X

Y

Z W

t=2

t=3,4

DelayX,W:1Y,Z:2

Z

t=0

t=2

t=1

Z

t=0

W

t=2

t=1

Z

t=1

t=3 W

t=2

t=4 W

t=2

t=3

t=4 W

t=3

t=3

t=4

t=4

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• Compiled simulation– translate the given logic circuit into a fast code which is com

piled and executed1. Do a levelization - determining evaluation order of gates in th

e given circuit for correct simulation, a kind of topological sorting

2. Generate code for evaluating each gate from lower level to high level

3. Compile the generated code4. Run the compiled code

/* level = 1 */f=b^c;store P, fg=d^e;store Q,g

/* level = 2 */h=a^f;store R,hi=f^g;store S,i

/* level = 3 */j=h^i;store T, j;

P T

S

R

Q

a

bc

de

f

g

h

i

j

level=1 level=2 level=3

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4) Fault Simulation

• Digital logic testing– defect : physical deviation from some specified properties– error : incorrect response to applied stimuli caused by the

presence of defects– test : an experiment to detect defects and the source of

them

• Fault model– models defects introduced during manufacturing– stuck-at-0(/1) : the defect causes a logic gate output to be

always 0(or 1)– Single fault assumption : only one fault at any time in a

circuit1 -->

1 -->--> 1

Fault-free circuit

Bottom input is s-a-0

1 -->

1 -->--> 0

This input pattern can detect the fault

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Initial fault list

Generate stimulus to cover some remaining faults

Fault simulation

Remove faults covered from fault list

Coverage OK?

start

stop

# of test vectors

Fault coverage

100%

Test pattern generation satisfying target coverage

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• Appications– evaluation of a test sequence in t

erms of its fault detection and location capability

– analysis of circuit under failure condition

• Methods– general

i) serialii) paralleliii) deductiveiv) concurrent

– combinational circuitsi) parallel pattern methodsii) trace-basediii) combined

– synchronous sequential circuitsi) modified parallel(PROOFS)

Fault-freecircuit

Faultycircuit

Faultlist

110011110101111110101110

Test pattern

Fault detection

+

01

Compare

Fault detection failed

Fault injection

Fault simulation

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• Serial fault simulation– iteration of logic simulation after injecting each fault ->

heavy simulation time

• Parallel fault simulation– simulating fault-free circuit and N-1 faulty circuits

simultaneously– N = word size of host machine

110011110101111110101110

Circuitwith fault #1

Fault-freecircuit

Circuitwith fault #2

Circuitwith fault #N-1

……

..

+

+

+

Test pattern

#0A.#0

B.#0C.#0

#1A.#1B.#1

C.#1

#2A.#2B.#2 C.#2

#3A.#3

B.#3C.#3

A,B,C : 4 bit valueC = A & B performs 4 evaluations in parallel

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• Deductive fault simulation– simulate a large # of faults in one pass– only a few faults may produce values different from

fault-free values– approach - keep fault-free values and differences

Fault list : a set of faults that complement the fault-free value at a

line

a

bc

0

10

This can detect a/1 --> La={a/1}

This can detect b/0 --> Lb={b/0}

This can i)detect c/1 ii)La because a has controlling valueand Lb is eliminated because b has non-controlling value Lc=(La - Lb) U {c/1}

After simulation of fault-free circuit, fault list is deductively constructed

based on the fault-free logic values on each line

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La = {a/1}; Lb = {b/0}; Ld = {d/1};

Le = (La - Lb) U {e/0} = {a/1, e/0},Lf = (Ld - Lb) U {f/1} = {d/1, f/1}

Lg = (Le - Lf) U {g/0} = {a/1, e/0, g/0}

----> input pattern 010 can detect faults a/1,e/0 and g/0

ab

d

0

1

1

00

e

fg

1

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• Concurrent fault simulation– keep a fault list(with I/O values) for each gate– when inputs to a gate change or faults are

propagated, dynamically update the fault list for the gate

a=0b=0 c

d=0

e

f=0

gAB

C a=0-->1b=0 c

d=0

e

f=0-->1

gAB

C

A a b c

free 0 0 1

a/1 1 0 1

b/1 0 1 1

c/0 0 0 0

B c d e

free 1 0 1

d/1 1 1 1

c/0 0 0 0

e/0 1 0 0

C e f g

free 1 0 1

c/0 0 0 1

e/0 0 0 1

f/1 1 1 0

g/0 1 0 0

A a b c

free 1 0 1

a/0 0 0 1

b/1 1 1 0

c/0 1 0 0

Input pattern abdf=0000 detect faults f/1 and g/0

B c d e

free 1 0 1

d/1 1 1 1

b/1 0 0 0

c/0 0 0 0

e/0 1 0 0

C e f g

free 1 1 0

b/1 0 1 1

c/0 0 1 1

e/0 0 1 1

f/0 1 0 1

g/1 1 1 1

Input pattern abdf=1001 detect faults b/1,c/0,e/0,f/0, and g/1

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parallel deductive concurrent

values binary binary any

elements logic logic any

storage min, fixed medium, variable max, variable

delays restricted restricted any

Comparison of three methods

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2. Verification 1) Timing Verification

• 주어진 디지털 회로에 대하여 얼마나 빨리 동작할 수 있는 지와 디자인의 어느 부분을 개선해야 하는지에 대한 정보를 얻는 과정 .

• Critical delay (TC) 와 critical path– Primary output 이 최종 값으로 안정화 되는데 걸리는 가장 긴

시간과 해당 패스 .– TC 가 클럭 주기 (TCLK) 보다 길지 않아야 회로가 정상 동작한다 .

TC <= TCLK

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• Topologically longest path– 간단히 빠르게 구할 수 있다 .– 회로의 실제 딜레이는 구해진 값보다 짧을 수 있다 (false pat

h problem).

10

20

10

20

0

1

0

1

Topologically longest path = 40Actual delay = 30

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• 타이밍 시뮬레이션 (Dynamic timing analysis)– 주어진 입력 벡터를 이용하여 시뮬레이션 하여 크리티컬

딜레이와 패스를 찾는다 .– 입력 데이터에 따르는 결과만을 출력할 수 있다 .– 수행시간이 가능한 입력 벡터에 따라 선형적으로 늘어나며

입력벡터는 회로의 복잡도에 따라 기하급수적으로 증가한다 .

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• Static Timing analysis– Best first search 에 기반을 두고 있다 .

i) Topologically longest path 가 false path 가 아닌지를 검사한다 . ii) 아니면 sensitizable path 로서 critical path 가 된다 .iii) False path 인 경우 다음으로 긴 패스에 대하여 위의 작업을

반복한다 .– False path 인지를 효과적으로 빠르게 판단하기 위하여 path

sensitization criteria 를 정의하여 사용한다 .i) Path sensitization criteria 는 주어진 패스의 입력에서 패스의

최종 출력까지 신호를 전달하는 입력이 있는지 없는지를 결정하기 위해 사용되는 룰의 집합으로 이것에 의해 Timing analysis 의 정확도가 결정된다 .

ii) 연산속도와 정확도의 트래이드 오프를 위하여 수 많은 path sensitization criteria 가 제안되어 왔다 .

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2) Functional Verification

• 정의– 실제로 구현한 system 이 주어진 functional spec. 을

만족하는지 확인하는 작업• Complete verification 방법

– Implicit enumeration method– BDD-based method– Formal method

• Equivalence checking, correctness checking

SpecificationGolden

ReferenceModel

(Ideal model)

DesignEquivalence Correctness

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• Implicit Enumeration-State machine– 목표

i) 주어진 두개의 state machine 에서 같은 input sequence 에 대해 같은 output sequence 를 내는 state pair 를 찾는다 .

– 방법i) State machine S, Q 중 si 는 S 의 state, qi 는 Q 의 state

ii) si 와 qi 가 같은 입력에 같은 출력을 내는지 확인하고 , 같은 출력을 낸다면 같은 입력에 대한 next state 도 마찬가지인지 계속해서 확인한다 .

i3/o3

i1/o1 i1/o1

i2/o2

i2/o2

s0

s2

s1

q0 q2

i3/o3

i2/o2

i1/o1

s0 q0

s1 q0 s2 q1

s0 q0 s2 q1

s0 q0

i1 i2

i1 i2

i3

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• BDD(Binary Decision Diagram)– 구성

i) Internal node: Variable 을 나타냄ii) Leaf node: 0, 1 두 가지가 있으며 function 의 값을 나타냄iii) Edge: Variable 이 0 일 때 , 1 일 때의 상황을 나타냄iv) 0 edge 와 1 edge 가 같은 internal node 는 없앤다 .

– 특징i) Variable 순서가 같으면 functionality 에 따라 유일한 모양을

가진다 .ii) BDD 상호간의 operation 은 다음과 같은 recursive equation

으로 정의된다 .

)()(1211020121

iiii xxixxi fopfxfopfxfopf

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• BDD 예제

• Combinational network 의 equivalence check– 두 network 에 대해 같은 variable 순으로 BDD 를 만들고

reduction 한다 .– 두 BDD 가 isomorphic 하면 equivalent 하다 .

x1

x2

x3

0 1

0

0

0

1

1 1

F= x1*x2 + x3

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• Formal verification– Design 과 specification 을 모두 엄격한 수학적 논리에

바탕을 둔 “ language” 로 기술을 하고 , symbolic manipulation을 이용하여 검증하는 방법

– Higher-order logic 혹은 temporal logic 등으로 spec 과 design 을 표현하고 theorem prover 를 이용 , logic 을 확인하는 방법이 주로 쓰인다 .

• Temporal logic– 기존의 predicate logic 에 시간적인 개념을 도입하여 일반화

시킴– Finite state system 은 state transition graph 로

표현가능하며 , 이는 temporal logic 으로 formulation 이 가능하다 .

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• Computational Tree Logic (CTL)– State transition graph 를 풀면 initial state 를 root 로 한

infinite tree 가 생겨남 . 이 tree 의 path 는 system 의 모든 가능한 state 와 그 state 에 도달하는 과정을 나타낸다 .

R

Y G

R

Y

G R

G RG

R Y

unwind

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• CTL 의 구성– Path quantifier (A, E)

i) A: 모든 경로를 나타냄 ( 모든 도달 가능한 state …)ii) E: 어떤 경로를 나타냄 ( 어떤 도달 가능한 state …)

– Temporal modality(F, G, X, U)i) F : 가 현재 state 이후 언젠가 참이 되면 참이다 .ii) G : 가 현재 state 이후 항상 참이면 참이다 .iii) X : 가 현재 state 의 바로 다음 state 에서 참이면 참이다 .iv) U : 가 현재 state 이후 언젠가 참이 되고 , 그 이전 state

에서 가 항상 참이면 참이다 .

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• Traffic light controller specification– hwy_light 와 farm_light 는 동시에 green 이 되서는 안된다 .

i) farm_light 와 hwy_light 가 동시에 green 인 상태는 모든 경로에 , 항상 거짓이여야 한다 .

ii) AG ( !((farm_light =green) * (hwy_light=green)))– farm road 가 어떤 상태였던 간에 hwy_light 는 언젠가 green

이 되어야 한다 .i) 모든 경로에 대해 언젠가 hwy_light 가 green 이 되는 경우는

모든 경로에 대해 항상 참이여야 한다 .ii) AG(AF(hwy_light=green))