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金屬閘極與絕緣層上鍺 晶圓製程 Metal Gate and Ge on Insulator Process. 指導教授：劉致為 博士 學生：李呈峻 臺灣大學電子工程學研究所. Outline. Introduction The Electrical Characteristics of Tantalum Nitride Metal Gate Ge-on-Insulator Substrates Formation by Wafer Bonding and Layer Transfer - PowerPoint PPT Presentation
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金屬閘極與絕緣層上鍺金屬閘極與絕緣層上鍺晶圓製程 晶圓製程
Metal Gate and Ge on Insulator Metal Gate and Ge on Insulator ProcessProcess
指導教授：劉致為 博士學生：李呈峻
臺灣大學電子工程學研究所
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OutlineOutline• IntroductionIntroduction• The Electrical Characteristics of Tantalum The Electrical Characteristics of Tantalum Nitride Metal GateNitride Metal Gate• Ge-on-Insulator Substrates Formation by WaferGe-on-Insulator Substrates Formation by Wafer
Bonding and Layer Transfer Bonding and Layer Transfer • A Novel 850 nm, 1.3μm and 1.5μm GOI MOSA Novel 850 nm, 1.3μm and 1.5μm GOI MOS
Photodetector for Optical Communication Photodetector for Optical Communication • SummarySummary
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ITRS 2001 ASIC-HP Near Term Long Term
Calendar Year 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016Technology Node 130nm 90nm 65nm 45nm 32nm 22nm
Ph. GL (nm) 65 53 45 37 32 28 25 18 13 9EOT (nm) 1.3-1.6 1.2-1.5 1.1-1.6 0.9-1.4 0.8-1.3 0.7-1.2 0.6-1.1 0.5-0.8 0.4-0.6 0.4-0.5Elec. Thick. Adjust. Factor 0.8 0.8 0.8 0.8 0.8 0.8 0.5 0.5 0.5 0.5Vdd (V) 1.2 1.1 1.0 1.0 0.9 0.9 0.7 0.6 0.5 0.4Ioff (uA/um) 0.01 0.03 0.07 0.1 0.3 0.7 1 3 7 10Ion (uA/um) 900 900 900 900 900 900 900 1200 1500 1500Tech. Improvement 0 0 0 0 0 0 0 30% 70% 100%Parasitic S/D Rsd (ohm-um) 190 180 180 180 180 170 140 110 90 80Parasitic S/D Rsd percent (Vdd/Idd) 16% 16% 17% 18% 19% 19% 20% 25% 30% 35%CV/I (ps) 1.65 1.35 1.13 0.99 0.83 0.76 0.68 0.39 0.22 0.15Device Performance 1.0 1.2 1.5 1.6 2.0 2.1 2.5 4.3 7.2 10.7Energy of Switching Transition (fJ /Device) 0.347 0.212 0.137 0.099 0.065 0.052 0.032 0.015 0.007 0.002Static Power Dissipat. (Watts/Device) 6E-09 7E-09 1E-08 1E-08 3E-08 5E-08 5E-08 1E-07 1E-07 1E-07
Intern’l Technology Roadmap for Intern’l Technology Roadmap for Semiconductors-- ITRSSemiconductors-- ITRS
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Problems in conventional poly silicon gate (poly-Si)• High gate resistance• High gate tunneling leakage current• Poly silicon gate depletion• Boron penetration into the channel region
Solution• Metal gate
Why metal gate ?Why metal gate ?
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Pure Metal Work FunctionsPure Metal Work FunctionsThe work-function with various pure metals.
The band gap of silicon that between the conduction band (Ec) and valence band (Ev) is 1.12eV at room temperature.
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Why tantalum metal is suitable for Why tantalum metal is suitable for semiconductor industry?semiconductor industry?
• Advantages• Body-centered-cubic (BCC) crystal structure• High melting point(2996 )℃• Low-resistance ohmic contact
Cubic, Body Centered Cubic, Face CenteredFor instance, Al, Pt and Cu
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OutlineOutline
• IntroductionIntroduction• The Electrical Characteristics of Tantalum Nitride The Electrical Characteristics of Tantalum Nitride
Metal GateMetal Gate• Ge-on-Insulator Substrates Formation by Wafer Ge-on-Insulator Substrates Formation by Wafer
Bonding and Layer TransferBonding and Layer Transfer• A Novel 850nm, 1.3μm, and 1.5μm GOI MOS A Novel 850nm, 1.3μm, and 1.5μm GOI MOS
Photodetector for Optical CommunicationPhotodetector for Optical Communication• SummarySummary
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Alloy Work FunctionsAlloy Work Functions
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Experiment Process FlowExperiment Process Flow
P-type silicon(100)
Silicon dioxideTaNPt
P-type silicon(100)
P-type silicon(100)
TaNSilicon dioxide
Pt
P-type silicon(100)
Silicon dioxideTaN
P-type silicon(100)
Silicon dioxide
1. P-type silicon wafer(100)2. RCA cleaning3. HF dipped 1min
4. Tetraethoxysilane (TEOS) oxide 10nm,21nm,33nm
5. TaN 200nm deposition by sputter
6. Pt 50nm deposition by E-gun
7. Wet etching using NaOH
TaNSilicon dioxide
Pt
P-type silicon(100)
Al contact
8. Dipped BOE 1min.9. Al contact 200nm deposition
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C-V Curves of TaN with PMA 400℃C-V Curves of TaN with PMA 400℃
Before N2 Annealing After N2 Annealing
After PMA 5minutes in 400 , the interface traps of TaN gate device ℃ are significantly reduced by heat treatment.
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Calculation of Flat-Band VoltageCalculation of Flat-Band Voltage
Cox
Csi Cde Cin
Vg < Vfb
Cox
P-type substrate
TaN
Silicon dioxide
Pt
P-type silicon(100)
Al contact
Vg > Vfb
Accumulation Inversion
Gate
-6 -4 -2 0 2 4
0.00E+000
2.00E-011
4.00E-011
6.00E-011
8.00E-011
1.00E-010
1.20E-010
1.40E-010
TaN_25:10_Pattern_PMA_400C_5min
Cs(
F)
Vg(V)
1M 500K 100K 10K 1K 500 100
Cox , Vg, A as known
ox
D
OXfb
tL
CC
1
Here LD was the Debye length defined Ndq
kTL SiD 2
Vfb
Vfb
Cfb
CsiCox
CsiCox
dVg
QsdC
)(
max
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Flat-Band Voltages Versus Silicon Flat-Band Voltages Versus Silicon Dioxide ThicknessDioxide Thickness
OX
OXsmfb C
QV
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The VFB converge to a specific value (i.e. -0.42V) when the N2 flow rate is upto abut twenty.
Flat-Band Voltages Versus Nitrogen Flow Flat-Band Voltages Versus Nitrogen Flow RatioRatio
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Work Functions of Tantalum NitrideWork Functions of Tantalum Nitride
OX
OXTaNOXAlOXTaNFBAlFBAlmTaNm
TaNFBAlFBOX
OXTaNOXAlOXTaNmAlm
tQQVV
VVt
,,,,,,
,,,,,,
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The C-V Curves Dispersion After The C-V Curves Dispersion After PMA 900 20sec℃PMA 900 20sec℃
After PMA 900C 20sec, the Cox of TaN gate devices continues to decrease as nitrogen flow ratio.
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The Value of Cox Dispersion After The Value of Cox Dispersion After PMA 900 20sec℃PMA 900 20sec℃
If nitrogen gas flow ratio is higher than thirteen percents, the Cox dispersion phenomenon is obviously.
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The TaN Gate Analysis of Auger The TaN Gate Analysis of Auger Microprobe Microprobe
-5000
0
5000
10000
15000
1 2 3 4 5 6 7 8 9 10 11 12
Counts
Etch Level
Peak Height Profile
NKL1OKL1PTMN2SIKL1TAMN3
-50000
0
50000
100000
150000
1 2 3 4 5 6
Cou
nts
Etch Level
Peak Height Profile
Nkl1Okl1ptmn2sikl1talm3
After PMA 900 20sec ℃After PMA 400 5min ℃ With increasing nitrogen gas flow ratio, the thermal stability
decreased by tantalum diffusion into dielectric layer.
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OutlineOutline
• IntroductionIntroduction• The Electrical Characteristics of Tantalum Nitride The Electrical Characteristics of Tantalum Nitride
Metal GateMetal Gate• Ge-on-Insulator Substrates Formation by Wafer Ge-on-Insulator Substrates Formation by Wafer
Bonding and Layer TransferBonding and Layer Transfer• A Novel 850nm, 1.3μm, and 1.5μm GOI MOS A Novel 850nm, 1.3μm, and 1.5μm GOI MOS
Photodetector for Optical CommunicationPhotodetector for Optical Communication• SummarySummary
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Roadmap for GOI ProcessRoadmap for GOI Process
TRIM SimulationPage 24&25.
Direct Wafer BondingPage 20.
Hydrogen Induced Exfoliation of Ge
Page 22.
Cross section and Surface Roughness of GOI substrates
Page 26.
GOI Surface Roughness Reduction Page 27&28&29.
GOI Wafer FormationPage 21.
GOI Smart-CutProcess FlowPage 23. Bulk Si
BPSG 600nmGe 1460nm
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Direct Wafer BondingDirect Wafer Bonding Megasonic acoustic cleaning KOH cleaning
KOH:H20DI water rinseHydrophilic surface (OH-)
SC1 cleaningNH4OH:H2O2:H2ODI water rinseHydrophilic surface (OH-)
Pre-bondingAlignmentForm a single bonding wave
High temperature treatment6500C, O2, 30minStrength the chemical bonds
Host wafer(Ge wafer)
Handle wafer(Si wafer)
BPSG
Host wafer(Ge wafer)
Handle wafer(Si wafer)
BPSG
OH-
Host wafer(Ge wafer)
OH- OH-OH-OH- OH-
Handle wafer(Si wafer)
BPSGOH- OH- OH-OH-OH- OH-
OH- OH- OH-OH-OH- OH-
OH- OH- OH-OH-OH- OH- OH-
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The scanning electron microscopy (SEM) picture of a Ge wafer bonds to another Si wafer capped with 600 nm BPSG.
GOI Wafer FormationGOI Wafer Formation
Ge
BPSG
Si
Wafer Bonding Without Smart-cutWafer Bonding Without Smart-cut
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The hydrogen-induced exfoliation of The hydrogen-induced exfoliation of Germanium Germanium
BPSG
Handle wafer(Si wafer)
Ge
Host wafer(Ge wafer)
BPSG
Handle wafer(Si wafer)
Host wafer(Ge wafer)
CracksRp Rp
650℃
Formation of point defect in the lower concentration of hydrogen implant. Rearrangement of the defect structure above 650℃. H2 trap in the microvoids. Development of these microvoids into cracks leading to complete layer transfer.
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GOI Smart Cut Process FlowGOI Smart Cut Process Flow
Host waferBulk Ge
Ge
BPSG
Handle wafer
Ge
BPSG
Handle wafer
Host waferH+ H+ H+ H+H+ H+ H+
1). Hydrogen implantation
2). Hydrophilic bonding at low temperature
3). Splitting annealing
4). Polishing
Host wafer Bulk Ge
BPSG
Handle wafer
Ion Implant (Hydrogen Dose 1E17) Megasonic acoustic cleaning
Direct Wafer Bonding KOH Cleaning SC1 Cleaning Pre-bonding
H Induced Layer Transfer High temperature treatment (650 30min in Oxygen gas)℃
Surface Roughness Reduction High temperature annealing (825 60min in hydrogen gas)℃
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Ion Implantation DepthIon Implantation Depth
The hydrogen implant depth in Ge vs. implant energy. The longitudinal Straggle in Ge vs. implant energy.
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TRIM SimulationTRIM Simulation The concentration profile of hydrogen atoms is simulated by TRIM. The hydrogen implant into germanium with 200KeV implant energy.
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Ge
BPSG
Handle wafer(Si wafer)
Ge
SiBPSG
rough
The surface of GOI substrate is rough after smart cut process. The thin germanium layer (i.e. 1.46μm) transfers upon BPSG.
SEM of GOI After Smart Cut ProcessSEM of GOI After Smart Cut Process
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GOI surface Roughness-mean-square(RMS)~97nm.
After GOI annealed in furnace 825 with℃forming gas , GOI surface roughness reduced to RMS~27nm.
No Annealing With Annealing in F. G.
Microroughness Measurement After Smart-cutMicroroughness Measurement After Smart-cut
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After GOI annealed in furnace 825 ℃with N2 gas , GOI surface roughness reduced to RMS~62nm.
After GOI annealed in RTP 825 ℃with H2 gas , GOI surface roughness reduced to RMS~43nm.
With Annealing in N2 With Annealing in H2
Microroughness Measurement After Smart-cutMicroroughness Measurement After Smart-cut
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GOI Surface Roughness ReductionGOI Surface Roughness Reduction Surface microroughness of Ge-on-insulator with different kind of gas,
for an hour annealing at 825 in furnace. ℃
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OutlineOutline
• IntroductionIntroduction• The Electrical Characteristics of Tantalum Nitride The Electrical Characteristics of Tantalum Nitride
Metal GateMetal Gate• Ge-on-Insulator Substrates Formation by Wafer Ge-on-Insulator Substrates Formation by Wafer
Bonding and Layer TransferBonding and Layer Transfer• A Novel 850 nm, 1.3μm and 1.5μm GOI MOS A Novel 850 nm, 1.3μm and 1.5μm GOI MOS
Photodetector for Optical CommunicationPhotodetector for Optical Communication• SummarySummary
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GOI Smart-Cut at Low Temperature Splitting
AnnealingPage 32.
GOI MOS PhotodetectorProcess FlowPage 35.
Liquid Phase
Deposition
Current Reduction by Metal Technique
Page 34.
Cross section and Surface
Roughness of GOI substrates
Page 33.
Bulk Si
Thermal oxide 80nmGe 800nmLPD oxide AlAl
Pt
Dark and Photocurrent with different light source
Page 37&38.
Responsivity and Efficiency
Page 39.
Impulse Response and Bandwidth
Page 40&41.
Cross section GOI MOS Photodetector
Page 36.
Roadmap for GOI PhotodetectorRoadmap for GOI Photodetector
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GOI Smart Cut at Low Temperature GOI Smart Cut at Low Temperature Splitting AnnealingSplitting Annealing
Host wafer(Bulk Ge)
Ge
Thermal oxide
Handle wafer(Bulk Si)
Ge
Thermal oxide
Handle wafer(Bulk Si)
Host wafer(Bulk Ge)
H+ H+ H+ H+H+ H+ H+
1). Hydrogen implantation
2). Hydrophilic bonding at low temperature
3). Splitting annealing
4). Polishing
Host wafer (Bulk Ge)
Thermal oxide
Handle wafer(Bulk Si)
Ion Implant (Hydrogen Dose 1E17) Megasonic acoustic cleaning
Direct Wafer Bonding KOH Cleaning SC1 Cleaning Pre-bonding
H Induced Layer Transfer Low temperature splitting annealing (150 12hr in 10% Oxygen gas)℃
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Low Temperature Splitting Low Temperature Splitting AnnealingAnnealing
After low temperature splitting annealing 150 with N℃ 2 gas , GOI surface roughness is around 6.6nm (r.m.s).
After splitting annealing, the germanium layer thickness is 800nm.
Ge 800nm
Si
SiO280nm
After splitting, the microroughness of Ge-on-insulator substrate. The cross-section SEM image of Ge-on-insulator substrate.
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Current Reduction by Metal TechniqCurrent Reduction by Metal Technique ue
Al
3.1e
V
5.2eV
traps
Hole current
Ge N(100)EF
Electron current
Pt
4.3e
V
5.2eV
traps
Hole current
Ge N(100)EF
Electron current
EC
EV
EF
5.2eV
4.3e
V
Pttraps
Ge N(100)
Electron current
Hole current
EC
EV
EF
5.2eV
3.1e
V
Al
traps
Ge N(100)
Electron current
Hole current
Device Area = 3x10-4 (cm2)Pt is good selection for Ge N(100).
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GOI Photodetector Process FlowGOI Photodetector Process Flow
Ion implant (hydrogen dose=1E17).
Direct Wafer bonding.H induced layer transfer.
(150 12Hr in 10% Oxygen)℃Liquid Phase Deposition.Gate electrode fabrication.
(Pt gate and Al contact)
Host waferBulk Ge
GeThermal oxide
Handle wafer(Si wafer)
Host wafer(Ge wafer)
H+ H+ H+ H+H+ H+ H+
1). Hydrogen implantation 3). Splitting annealing
OH-
Host wafer(Ge wafer)
OH- OH-OH-OH- OH-
Handle wafer(Si wafer)
Thermal oxideOH- OH- OH-OH-OH- OH-
2). Surface cleaning and hydrophilic bonding at low
temperature
Al Contact
Pt Pattern
Top view
5). GOI detector fabrication
Bulk Si
Thermal oxide 80nmGe 800nm
LPD oxide 1.6nm
4). Liquid Phase Depositon
Bulk Si
Thermal oxide 80nmGe 800nmLPD oxide AlAl
Pt
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GOI Photodetector FormationGOI Photodetector Formation
Bulk Si
Thermal oxide 80nm
Ge 800nm
LPD oxide Pt 25nm
Ge800nm
Thermal oxide 80nm
Si
Pt LPD
The cross-section TEM image of Ge-on-insulator PMOS devices.
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Photocurrent Under 850nm Light Photocurrent Under 850nm Light SourceSource
The dark and photocurrent of the GOI PMOS detector exposures to 850nm lightwave with different light intensity.
Responsivity = 0.2 ~ 0.3 (A/W)GOI PMOS Photodetector
Responsivity = 0.2 (A/W)Bulk Ge MOS detector
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Photocurrent under 1300 and 1550 Photocurrent under 1300 and 1550 nm light sourcenm light source
Responsivity = 0.2 (A/W)
The dark and photocurrent of the GOI PMOS detector exposures to 1300nm and 1550 nm lightwave with different light intensity.
Responsivity = 0.06 (A/W)
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Responsivity and EfficiencyResponsivity and Efficiency The responsivity of GOI PMOS detector exposures to 850nm, 1.3μm, and 1.5μm
lightwave with different light intensity. The quantum efficiency (η) of the GOI photodetectors versus power under different
lasers exposure.
hP
eI s/
/
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Impulse Response Bulk Ge DetectorImpulse Response Bulk Ge Detector The Full-Width Half-Maximum (FWHM) is 722 ps for the typical Ge MOS detector
under 850nm pulse measurement. After fast fourier transform (FFT), the -3 dB bandwidth can be obtained about
340 MHz.
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Impulse Response GOI DetectorImpulse Response GOI Detector The Full-Width Half-Maximum (FWHM) is 543 ps for the typical Ge MOS detector
under 850nm pulse measurement. After fast fourier transform (FFT), the -3 dB bandwidth can be obtained about
340 MHz. The 60% enhancement is achieved with -3 dB bandwidth, comparing to bulk
Ge MOS detector. Since some of diffusion current is eliminated in GOI MOS photodetectors,
the speed and bandwidth of the device increases.
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OutlineOutline
• IntroductionIntroduction• The Electrical Characteristics of Tantalum Nitride The Electrical Characteristics of Tantalum Nitride
Metal GateMetal Gate• Ge-on-Insulator Substrates Formation by Wafer Ge-on-Insulator Substrates Formation by Wafer
Bonding and Layer TransferBonding and Layer Transfer• A Novel 850nm, 1.3μm, and 1.5μm GOI MOS A Novel 850nm, 1.3μm, and 1.5μm GOI MOS
Photodetector for Optical CommunicationPhotodetector for Optical Communication• SummarySummary
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SummarySummary
Tantalum Nitride Metal Gate• In experiment, we obtained that the oxide charges are positive in TEOS and the
flat-band voltages concentrated -0.42V at twenty percents nitrogen flow ratio.
• With increasing nitrogen gas flow ratio, the thermal stability decreased by tantalum diffusion into dielectric layer.
• If nitrogen gas flow ratio is higher than thirteen percents, the tantalum diffusion
phenomenon is obviously.
Ge-on-Insulator substrates Formation• The GOI surface roughness is reduced by thermal rapid annealing with hydrogen
gas in furnace.
• The bonding condition of low temperature heat treatment is at 150 with 10% ℃oxygen flow in furnace.
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SummarySummary
GOI MOS Photodetector • The leakage current is decreased at inversion bias by platinum gate electrode.
• The novel GOI PMOS photodetectors have high responsivity (0.3 A/W) and high quantum efficiency of 40% at 850nm (0.25mW).
• The 60% enhancement is achieved with -3 dB bandwidth, comparing to bulk Ge MOS detector.
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Future WorkFuture Work• The RF pattern can be designed to enhance the speed (3-dB bandwidth) of
GOI MOS photodetectors.
• The thickness of germanium layer on insulator can be designed for fabricating resonant-cavity-enhanced (RCE) photodetectors to increase the bandwidth-efficiency.
