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8/19/2019 0-TOC (2)
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Computer Organization & Architecture Lab
Lab ReportsMuhammad Jaleed Khan (11PC!"0937)
Abdul Lati# (11PC!"0933)
MIPS Assembly Language
Lab 1 1$ %aing t'o numbers as input and nding their sum$)$ *ispla+ing string 'ith ,-O$
Lab ) 1$ Compare t'o numbers)$ Read t'o numbers A. /$ *ispla+ multiples o# A upto A0/$ Multipl+ t'o numbers using repeated addition
2$ *i3ide t'o numbers using repeated subtractionLab 1$ 4se M4L% and *,5 to access lo'er and higher bits)$ 4se o# sll and srl$ %ae a number 6 as input$ ,mplement 17(68 'ithout using
multiplication$Lab 2 1$ %as program to nd the #th bit o# an+ number. and in3ert
it)$ Chec 'hether a number is palindrome or not$ 9ind size o# a string
Lab : 1$ 9ind size o# an arra+)$ Con3ert lo'er case string into uppercase
$ Reduction operator
Verilog HDL
Lab ; 1$ ,mplementation o# )61 M4<)$ ,mplementation o# 261 M4< using t'o )61 M4bit Adder)$ ,mplementation o# 2>bit Adder using 1>bit Adders$ ,mplementation o# ?e6adecimal to /C* con3erter
Lab 7 1$ ,mplementation o# 2>bit comparator)$ ,mplementation o# 7>bit ring counter
Lab @ 1$ ,mplementation o# JK 9lip 9lop)$ ,mplementation o# * 9lip 9lop