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Nhận hướng dẫn thiết kế số sử dụng ngôn ngữ Verilog-HDL trên FPGA
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30/05/2013 FPGA Class 1
TNG QUAN V THIT K S
TRN FPGA (FIELD-FROGRAMMABLE GATE ARRAY)
BI 1:
Nhn hng dn thit k s s
dng ngn ng Verilog-HDL
trn FPGA
mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]
Ni dung chnh
Lung thit k c bn
Cc phn mm s dng
Ngn ng m t phn cng
Khi qut v l thuyt thit k s
KIT DE1
Cu trc FPGA
Mt v d thit k (phn tch, tng hp, m
phng v np KIT)
30/05/2013 FPGA Class 2
Lung thit k c bn
(Design Flow)
S khi, s chn.
Thit k mc cng logic
Vit RTL (Register Transfer Level)
code
30/05/2013 FPGA Class 3
Tng hp v kim tra li.
M phng thit k.
Gn chn tn hiu v bin dch file
np.
Chy kim tra chc nng trn FPGA
Lung thit k c bn
30/05/2013 FPGA Class 4
module MUX2 (input SEL, A, B, output F);
input SEL, A, B;
output F;
INV G1 (SEL, SELB);
AOI G2 (SELB, A, SEL, B, FB);
INV G3 (.A(FB), .F(F));
endmodule
Min thit k
30/05/2013 FPGA Class 5
Circuit Gate Silicon
(Physical)
M phng vi ModelSim 6.4
Xem trc tip trn ModelSim 6.4
30/05/2013 FPGA Class 18
30/05/2013 FPGA Class 19
KT THC BI 1