4.DC1 Biasing - BJTs

8/7/2019 4.DC1 Biasing - BJTs

1/89

DC BiasingDC Biasing - - BJTsBJTs

CHAPTER 4


2/89

IntroductionIntroductionBJTs amplifier requires a knowledge of both the DC analysis( large signal) and AC analysis ( small signal).F or a DC analysis a transistor is controlled by a number of

factors including the range of possible operating points.

Once the desired DC current and voltage levels have been

defined, a network must be constructed that will establish thedesired operating point.

BJT need to be operate in active region used as amplifier.

The cutoff and saturation region used as a switches.

F or the BJTs to be biased in its linear or active operating region the following must be true:

a) BE junction forward biased, 0.6 or 0.7V

b) BC junction reverse biased


3/89

IntroductionIntroduction

DC bias analysis assume all capacitors are open cct.

AC bias analysis :

1) Neglecting all of DC sources

2) Assume coupling capacitors are short cct. The effect of

these capacitors is to set a lower cut-off frequency for the cct.

3) Inspect the cct (replace BJTs with its small signal model).

4) Solve for voltage and current transfer function and i/o and

o/p impedances.F or transistor amplifiers the resulting DC current and voltageestablish an operating point that define the region that can beemployed for amplification process.


4/89

Slide 1

Robert Boylestad Digital Electronics

Copyright 2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

T ransistor Construction

There are two types of transistors: pnp and npn -type.

N ote : the labeling of the transistor:E - Emitter B - BaseC - Collector


5/89

Slide 2




T ransistor Operation

With the external sources (V EE and V CC) in the polarities as shown:

The E-B junction is forward-biased and the B-C junction is reverse biased.


6/89

Slide 3




Currents in a T ransistor

Note that IC is comprised of two currents:

[Formula 3.1]

[Formula 3.2]

C III !

COminorityCmajorityC III !


7/89

Slide 4




Common Base Configuration

The base is common to both input (emitter base) and output (collector base) of thetransistor.


8/89

Important basic relationships for a transistor:

V BE =0.7V

I E =( +1)I

BI

C

I E = I C +I B

I C = I B

IntroductionIntroduction


9/89

Ope rating PointOpe rating PointF or transistor amplifiers the resulting dc current and voltage

establish an operating point on the characteristics that define the

region that will be employed for amplification of the applied

signal.

Operating point quiescent point or Q-point

The biasing circuit can be designed to set the device operation at

any of these points or others within the active region.

The BJT device could be biased to operate outside the max

limits, but the result of such operation would be shortening of thelifetime of the device or destruction of the device.

The chosen Q-point often depends on the intended use of the

circuit .


10/89

15

18

12

9

6

3

IC(mA)

VCE(V)

IB=60 uA

10 20 30

IB=50 uA

IB=0 uA

IB=40 uA

IB=30 uA

IB=20 uA

IB=10 uA

40

A

C

B

VCEsat

PCmaxICmax

VCEmaxCutoff

Saturation

Various o pe rating p oints within th e limits of o pe rationVarious o pe rating p oints within th e limits of o pe rationof a transistor of a transistor


11/89

Fixe dFixe d--Bias CircuitBias Circuit

F or the dc analysis the network can be isolated from theindicated ac levels by replacing the capacitors with an open-circuit equivalent because the reactance of a capacitor for dc is

The dc supply V cc can be separated into two supplies


12/89

Forward Bias of Bas eForward Bias of Bas e --Emitt e r Emitt e r

W rite KVL equation inthe clockwise directionof the loop :

+V CC IBRB V BE =0

Solving the equation for the current IB results :

B

B

V B V

+

+

--

IB

V

Base-emitter loop

+

-

B

BECCB

R

V-VI !


13/89

Coll e ctor Coll e ctor- -Emitt e r Loo pEmitt e r Loo pThe magnitude of the IC is related directly to IB through

IC= IB ; IB=0

Apply KVL in the clockwise directionaround the indicated close loop results:

V CE + ICRC V CC =0V CE = V CC ICRC

R ecall that :V CE = V C V E ; V E =ICRC

In this case, V E = 0V, soV CE =V C

C

V CE

V CC

C

C c


14/89

Exam p le 1Exam p le 1D etermine the f llowing f or the f ixed bias on f iguration.

The transistor has a = 50

a) I BQ and I CQ b) V CEQ c) V B and V C d) V BC


15/89

S olutionS olution

biased.

reverseisunction-BCthatindicatessignve-

6.13 V83.67.0VVV)d

V6.83VVV

V0.7VV)c

V83.6

k 2.22.35m-12R I-VV) b

m34.2u08.4750II

u08.47k 240

7.012

R VV

I)a

CBBC

CCEQCE

BBE

CCCCCEQ

BQCQ

B

BECCBQ

!!!

!!!

!!

!

!!

!! F!

!!

!


16/89

Exam p le 2Exam p le 2D etermine the f ollowing f or the f ixed bias con f iguration.

The transistor has a = 90a) IBQ and ICQ b) V CEQ c) V B d)V C e) V E

C = .7kohm

B

C

EV BE

V CE

V C C = 6 V

IC

IB

B = 7 0 kohm


17/89

S olutionS olution

V0V)e

V8.17VVd)V

V0.7VV)c

V17.8

k 7.22.93m-16

R I-VV) b

mA93.2u55.3290II

uA55.32k 470

7.016R

VVI)a

E

CCEQCE

BBE

CCCCCEQ

BQCQ

B

BECCBQ

!

!!!

!!

!

!

!

!! F!

!

!

!


18/89

Slide 7




3 Regions of Operation

Active

Operating range of the amplifier.

Cutoff -When I B = 0-The amplifier is basically off. There is voltage but littlecurrent.- small collector leakage current- VCE = V CC

Saturation- The amplifier is full on. There is little voltage but lots of

current.- VCE SAT, base-collector junction become forward

biased and IC cannot increase no further.- V CE SAT occur somewhere below the knee of the

collector curve.


19/89

Transistor S aturationTransistor S aturation

The term saturation is applied to any system where levels havereached their max values.F or a transistor operating in the saturation region, the current ismaximum value for a particular design.Saturation region are normally avoided because the B-C junction

is no longer reverse-biased and the output amplified signal will be distorted.

R C

V CE =0V

+

-

V CC

ICsat

R B+

-V RC =V CC

The sat ur at ion curren t f or the f ixed bias con f igur at ion is:

ICsa t R C

VCC


20/89

By refering to example 1 and the figure, determine the saturationlevel.

Solution

Exam p le 3Exam p le 3

limit.thewithinoperatesisIthat theconcluded becan

It.mA34.2Iin1exampleof designThe

mA45.5k 2.212

R V

I

CQ

CQ

C

CCCsat

!

!!!


21/89

F ind the saturation current for the fixed-bias configuration of figure example 2.

Solution

limit.the

withinoperatesisIthat theconcluded becan

It.mA93.2Iin2exampleof designThe

mA92.5k 7.2

16R

VI

CQ

CQ

C

CCCsat

!

!!!



22/89

LoadLoad- -Lin e AnalysisLin e AnalysisW e investigate how the network parameters define the possiblerange of Q-points and how the actual Q-point is determined.R efer to figure below (output loop) one straight line can be draw at output characteristics. This line is called load line .This line connecting each separate of Q-point.

At any point along the load line, values of I B, I C and V CE can be picked off the graph.

The process to plot the load line as follows:


23/89

Step 1:

R efer to circuit, V CE =V CC I C R C (1)

Choose I C =0 mA. Subtitute into (1), we get

V CE =V CC (2) located at X axis

Step 2:Choose V CE =0V and subtitute into (1), we get

I C =V CC / R C (3) located at Y-axis

Step 3:

Joining two points defined by (2) + (3), we get straight line that can be drawn as F ig. 5.6.

LoadLoad- -Lin e AnalysisLin e Analysis


24/89

IC (m )

V CE (V )

Load lineV CC /R C

IC = 0 m

V CC

IBQQ -pointV CE = 0 V

F ig. 5.6



25/89

IC(mA)

VCE(V)

VCC/R C

VCC

IBQ2

Q-point

Fig. 5.7:Movement of Q-point with increasinglevels of I B

Q-point

Q-point

IBQ3

IBQ1

Cas e 1:

Level IB changed by var ying the value of R B.

Q oint moves up and down



26/89

IC(m )

V CE (V )

VCC /R C1

V CC

IBQQ -point

F ig. 5.8 : Eff ect o f increasing levels o f R C on theload line and Q -point

Q -pointQ -point

VCC /R C2

VCC /R C3

R C3 > R C2 > R C1

Cas e 2:

V CC f ixed and RC change the load line will shi f t as shown in Fig 5.8

IB f ixed, the Q point will move as shown in the same f igure.



27/89

IC(m )

VCE (

V)

VCC 1/R C

VCC 1

IBQQ-point

Fig. 5.9: Eff ect o f lo er values o f V CC on the load line and Q-point

Q-point

Q-point

VCC 2/R C

VCC 3/R C

VCC 2VCC 3

VCC1 > VCC2 > VCC3

Cas e 3:

RC f ixed and V CC varied, the load line shi f ts as shown in Fig. 5.9


28/89

Exam p le 5Exam p le 5G iven the load line of F ig. 5.10 and defined Q-point, determine therequired values of V CE , R C and R B for a fixed bias configuration.

15

18

12

9

6

3

I C (m )

V C E (V )

I B = 60 u

10 20 30

I B = 50 u

I B = 0 u

I B = 40 u

I B = 30 u

I B = 20 u

I B = 1 0 u

40

I C m ax

F i . .1 0

Q - p o i tIB=17 u A


29/89

S olutionS olution

kohm2311

177.040I

VVR

R V-V

I

kohm67.2m15

40I

VR

0V .VatR

VI

m0IatV40VV

B

BECCB

B

BECCB

C

CCC

CEC

CCC

CCCCE

:2tep

:1tep

!

Q!

!

!

!!!

!!

!!!


30/89

Exam p le 6Exam p le 6Determine the value of Q-point for this figure. Also find the new

value of Q-point if F change to 150 .

100! F


31/89

16.95mA)V,(2.51 point-Q NewV51.2

56016.95m-12

R I-VV

:4Step

mA16.95113150II

same,isvaluetheA113100k

0.7-12I

150,new:3Step

mA3.11,V67.5int poQV67.5

560m3.11-12

R I-VV

:2Step

mA11.3113100II

A113100k

0.7-12I

100,

:1Step

CCCCCE

BC

B

CCCCCE

BC

B

!

!Q! F!

Q!!

! F

!

!

!

!Q! F!

Q!!

! FThe change of

F cause the big change of Q-point value.

This shows that f ixed

biased con f iguration is

NOT sta ble

The change of

F cause the big change of Q-point value.

This shows that f ixed

biased con f iguration is

NOT sta ble

S olutionS olution

ICQ & V CEQ


32/89

Emitt e r Bias (E- S ATB ILIZED B IAS)The DC bias network below contains an emitter resistor to

improve the stability level of fixed-bias configuration.The analysis consists of two scope:

- Examining the base-emitter loop (input loop)

- Use the result to investigate the collector-emitter loop (output

loop)

Vi

Vo

R C

C 1

C 2

VCC

IC

I

R B

F i . .11 R E

IE


33/89

Bas eBas e --Emitt e r Loo pEmitt e r Loo p

EBBECC

B

EBBEBBCC

BE

EEBEBBCC

R 1R V-V

I

get,finally weequ,theRearrange

0R I1-V-R I-V

get,we(1)intosubtitute,I1Iknown that

(1) 0R I-V-R I-V:KV

F!

! F

F!

!

IE= IC + IB ; IC = I B

IE= I B + IB

= ( + 1)IB


34/89

Coll e ctor Coll e ctor- -Emitt e r Loo pEmitt e r Loo p

EBEBBBCCB

CCCCCECEC

ECCE

EEE

ECCCCCE

CE

EECECCCC

VVV OR R I-VV

R I-VV OR VVV

V-VV

R IV

knowcanalsoweFig.5.13theFrom

)R (R I-VV

get,we(1)equrearrangeIIAssuming

(1) 0R I-V-R I-V:KV

!!

!!

!

!

!

$

!

V CC ICRC = V CE + IERE = V C


35/89

Slide 12




Characteristics of Common-Emitter

Collector characteristics = output characteristics.Base characteristics = input characteristics.


36/89

Slide 13




Amplifier Currents

IE = IC + IB

IC = E IE


37/89

Slide 14




Actual Amplifier Currents

IC = E IE + ICBO

ICBO = minority collector current. This is usually so small that it can be ignored, except inhigh power transistors and in high temperature environments.

[Formula 3.9]

When I B = 0 QA the transistor is in cutoff, but there is some minority current flowing calledICEO .

A0I1I

I BCBO

CEO QE

!!


38/89

Slide 15




Beta ( F)

In DC mode: [Formula 3.10]

In AC mode: [Formula 3.11]

F indicates the amplification factor of a transistor. ( F is sometimes referred to as hfe, aterm used in transistor modeling calculations)

B

C

II

dc !&

constantVII

ac CEB

C!

((

!&


39/89

Slide 1




D etermining beta ( F) from a Graph

Note: F AC = F DC

1087.5)(f or VCEA25

2.7mADC !!!&

Q

1007.5)(f or VCE010

1mA)020330(

2.2mA)(3.2mAAC !!!!&

QQQQ


40/89

Slide 17




Relationship between F and E

Both indicate an amplification factor.

[Formula 3.12a]

[Formula 3.12b]

1&&

!E

1!&

E

E


41/89

Slide 18




F provides a Relationship between Currents

[Formula 3.14]

[Formula 3.15]

BC II &!

BE 1)I(I &!


42/89


F or the emitter-bias network for F ig.5.14 determine:a)I B b)I C c)V CE d)V C e)V E f)V B g)V BC

R C=2 kohm

VCC =+20 V

IC

IB

R B=430 kohm

Fi . .14 R E=1 kohm

IE

Beta =50


43/89

S olutionS olution

required)as biased(reverse

V27.1398.1571.2VVV)g

V71.201.27.0VVV)f

V01.2k 1m01.2R IR IV

OR

V01.297.1398.15VVV)e

V98.1502.420

k 2m01.220R IVV)d

V97.13

03.620k 1k 2m01.220

R R I-VVc)

m01.21.4050II b)

1.40k 1150k 430

7.020R 1R

V-V Ia)

CBBC

EBEB

ECEEE

CEEE

CCCCC

ECCCCCE

BC

EB

BECCB

!!!

!!!

!!$!

!!!

!!

!!

!

!!

!

!Q! F!

Q!! F

!


44/89

S aturation L eve lS aturation L eve l

The saturation current f or an emitter -bias con f iguration is :

R C

VCE =0 V+

-

VCC

IC satFig. 5 .16

+

-

R E

E C

CC C sat

E C C sat CC

E C sat C C sat CC

R RV I

R R I V

R I R I V

!

!!0

0


45/89

D etermine the saturation current f or the networ k of example 7.

S olution:S olution:

This value is a bout three times the level of ICQ

(2 .01 m A F=50 ) f or the example 7. Its indicate the parameter that been used in example 7 can be use in anal ysis of emitter bias networ k.

mA67.6k 3

20k 1k 2

20

R R VI

EC

CCCsat

!!!

!



46/89

The process to plot the load line as f ollows :

Step 1:Re f er to f ig. 5.13 , V CE =V CC IC(R C+ RE) (1)Choose IC=0 m A. Su btitute into (1), we get

V CE =V CC (2) located at X axis

Step 2:Choose V CE =0 V, su btitute into (1) gives

axisYatlocated(3) R R

VI 0VVCE

EC

CCC ! !

Load-Lin e Analysis


47/89

Step 3:J oining two points de f ined by (2 ) + (3), we get straight line that can

be drawn as Fig. 5.17 :IC

VCE(V)

VCC /(R C+R E)

VCC

IBQQ-point

Fig. 5.17: Load line f or the emitter-bias con f iguration

VCEQ

ICQ

Load-Lin e Analysis


48/89

Exam p le 9Exam p le 9F or the emitter-bias network for F ig.5.14 determine:a) Draw a load line in the graph on the characteristic.

b)I B c)I C d)V CE e)V C f)V E g)V B h)V BC i) Choose the operating point between cut off and saturation, determine

the resulting values I CQ and V CEQ

j) k) l) ICsat

Beta =50

15 V

30


49/89

Voltag e Divid e r BiasVoltag e Divid e r Bias

I CQ and V CEQ from the table is changing dependently the changing of F.

The voltage-divider bias configuration is designed to have a lessdependent or independent of the F.

If the circuit parameter are properly chosen, the resulting levels of I CQand V CEQ can be almost totally independent of F.

F IB(Q A) IC(m A) V CE (V )

50 40 .1 2 .01 13 .97100 3 .3 3 .6 3 9 .11


50/89

Two method for analyzed the voltage-divider bias configuration:- Exact method ( applied anywhere)- Approximate method (only if specified conditions are

satisfied)

Voltag e Divid e r BiasVoltag e Divid e r Bias


51/89

Exact AnalysisExact Analysis

Step 1 :

The input side of the network can be redrawn for DC analysis.Step 2 :

Analysis of Thevenin equivalent network to the left of baseterminal


52/89

Step 2(a) :

R eplaced the voltage sources with short-circuit equivalent and gives the value of R TH


21TH R R R !


53/89

Step 2(b ):

Determining the E TH by replaced back the voltage sources and open circuit Thevenin voltage. Then apply the voltage-divider rule.

21

CC22R T

R R

VR VE !!



54/89

Step 3 :

The Thevenin network is then redrawn and I BQ can bedetermined by KVL 0R IVR IE EEBETHBTH !

givesI1Iubtitute BE !

ETHBETH

B

R 1R

VEI

F!



55/89

Exam p leExam p leDetermine the DC bias voltage V CE and current I C for thevoltage-divider configuration of network below:

R C = 1 0 k o h m

VC C = 2 2 V

R 1 = 3 9 k o h m

R E = 1 . 5 k o h mR 2 = 3 . 9 k o h m

140! F


56/89

kohm3.55k 9.3k 39 k 9.3k 39

R R R 21TH

!!

!

V2

k 9.3k 3922k 9.3

R R VR

E21

CC2TH !!!

A05.6

k 5.11140k 55.37.02

R 1R VE

I ETHBETH

B

Q!!

F!

mA85.005.6140II BC !Q! F!

V22.12

k 5.1k 10m85.022

R R IVV ECCCCCE

!

!

!

S olutionS olution


57/89

F or the voltage-divider bias configuration, determine: I BQ , I CQ ,V CEQ , V C , V E and V B.

Exam p leExam p le

S l tiS l ti


58/89

kohm7.93k 1.9k 62

k 1.9k 62

R R R 21TH

!!

!

V05.2

k 1.9k 6216k 1.9

R R

VR E

21

CC2TH !!!

A4.21

k 68.0180k 93.77.005.2

R 1R VE

IETH

BETHBQ

Q!!

F!

mA712.14.2180II BCQ !Q! F!

V16.8

k 68.0k 9.3m712.116

R R IVV ECCCCCEQ

!!

!

V32.9k 9.3m712.116R IVV CCCCC

!!

!

V18.1

k 68.0m712.14.21

k 68.0II

R IV

CB

EEE

!

Q!

!

!

V88.1

7.018.1

VVV BEEB

!

!

!

S olutionS olution


59/89

App roximat e AnalysisApp roximat e AnalysisStep 1 :

FR E u 10 R 2 Step 2 :

The input section can be represented by the network of figure below and R

2 can be considered in series by assuming

I 1$ I 2 and I B= 0A .

E i

i

R R

I I R R

1

212

!

$u

F

R 1

R iR 2

Partial-bias circuit for calculating theapproximate base voltage, B

CC

I1

I2

IB

B

+

-

This eq n must b e satisfi e d. If not, a pp roximat e analysiscant b e us e d , and you ha ve to us e th e e xact analysis(Th eve nins m e thod )


60/89

21

CC2R 2B

R R

VR VV

:determined becanvoltage baseThe

!!

BEE

EBBE

E

V-VV

V-VV

:wellascalculated becanVleveland

B!

!

ECQ

E

EE IIand

R V

I

:determined becancurrentemitter theand

$! E E R R )1(R where

10R R

:approacheapproximat

definethat willCondition

i

2E

F F !!

u

App roximat e AnalysisApp roximat e AnalysisR1

RiR2

Partial-bias circuit for calculating theapproximate base voltage, V B

VCC

I1

I2

IB

VB

+

-

Step 3:


61/89

N P N Transistor S imulationN P N Transistor S imulation


62/89

R epeat the analysis of example 9 using the approximatetechnique and compare solution for I CQ and V CEQ .

Solution:

Exam p leExam p le

!satis f iedkohm39kohm210

k 9.310k 5.1140

R 10R

:tep1

2E

u

u

u F

dra n becancct bias partialthe:2tep


63/89

V2

k 9.3k 3922k 9.3

R R VR

V

:3Step

21

CC2B !!!

V3.17.02

VVV BEBE

!!

!

mA867.0k 5.1

3.1

R

VII

E

EECQ !!!$

V03.12

k 5.1k 10m867.022

R R IVV ECCCCCEQ

!

!

!

ICQ (m A) V CEQ (V )

Exact Anal ysis

0.8 5 12 .22

Approximate Anal ysis

0.86 7 12 .03

ICQ and V CEQ are certainl y close.

S olutionS olution

Exam p leExam p le


64/89

R epeat the exact analysis of example 9 if F is reduced to 70.Compare the solution for I CQ and V CEQ .

Solution:Solution: kohm3.55R TH !V2E TH !

A81.11k 5.1170k 55.3

7.02R 1R

VEI

ETH

BETHB

Q!! F

!

mA83.081.1170II BC !Q! F!

Exam p leExam p le

S olution (continu e d )S olution (continu e d )


65/89

V46.12k 5.1k 10m83.022

R R IVV ECCCCCE

!!

!

FICQ (m A) V CEQ (V )

140 0 .8 5 12 .22

70 0 .8 3 12 .46

Conclusion : Even though F is drasticall y hal f , the level ICQand V CEQ are essentiall y same.


Exam p leExam p le


66/89

D etermine the levels of ICQ and V CEQ f or the voltage -divider con f iguration using the exact and approximate anal ysis. Compare the solution.

R C . ohm

V CC 8 V

R 1 =8 oh m

R E =1.2 ohmR 2=22 ohm

ICQ

I Q

Exam p leExam p le

S olutionS olution


67/89

S olutionS olution

kohm35.71k 22k 82

k 22k 82

R R R

:AnalysisExact

21T

!!

!

V81.3

k 22k 8218k 22

R R VR

E21

CC2T

!!!

A6.39

k 2.1150k 35.177.081.3

R 1R VEI

ET

BET

BQ

Q!!

F!

mA98.16.3950II BCQ !Q! F!

V54.4

k 2.1k 6.5m98.118

R R IVV ECCCCCEQ

!

!

!



68/89

satis f ied)(not220kohm60kohm

k 2210k 2.150

R 10R

:AnalysiseA pproximat

2E

u

u

u F

V81.3

k 22k 8218k 22

R R VR

EV21

CC2TB !!!!

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ICQ (m A) %di ff erence V CEQ (V)

%di ff erence

Exact Anal ysis

1.9823 .5%

4.5417 %

Approximate Anal ysis

2.59 3 .88


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The saturation collector -emitter circuit f or the voltage -divider con f iguration has the same appearance as the emitter -biased

con f iguration as shown below.

EC

CCCsat

R R VI !


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Load Lin e AnalysisLoad Lin e Analysis

The similarities with the output circuit of the emitter -biasedcon f iguration result in the same intersections f or the load line of the voltage -divider con f iguration.

The load line there f ore have the same appearance with :

axisatlocate d R R

VI 0VVCE

EC

CCC ! !

axisXatlocate d VV 0m AICCCCE ! !


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Another wa y to improve the sta bility of a bias circuit is to add a f eed bac kpath f rom collector to base. In this bias circuit the Q -point is onl y slightl y

dependent on the transistor Beta F.

DC Bias with Voltag e Fee dbackDC Bias with Voltag e Fee dback


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Bas eBas e --Emitt e r Loo pEmitt e r Loo p Appl ying Kircho ffs voltage law : V CC IC

d R C IBR B V BE IERE = 0

Note : ICd = IC + IB -- but usuall y IB


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Coll e ctor Coll e ctor- -Emitt e r Loo pEmitt e r Loo p

Appl ying Kircho ffs voltage law : IE + V CE + ICd

RC V CC = 0

Since ICd $ IC and IC = FIB: IC(R C + R E) + V CE V CC =0

Solving f or V CE : V CE = V CC - IC(R C+ RE)

)( E C C CC CE R R I V V !


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Transistor S aturation L eve lTransistor S aturation L eve l

EC

CCCC

R R V

maxIsatI !!

Load Lin e AnalysisLoad Lin e Analysis

It is the same anal ysis as f or the voltage divider bias

and the emitter -biased circuits.

S imulation of a N P N ty pe commonS imulation of a N P N ty pe common- -e mitt e re mitt e r


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S imulation of a P ty pe commonS imulation of a P ty pe common e mitt e r e mitt e r transistor transistor


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M isc e llan e ous configurationM isc e llan e ous configuration


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De sign Ope ration

W e are able to design the transistor circuit using the ideas that we have learnt before during analyzing dc biasing circuit.How?

- Understand the Kirchoffs Law and other electric circuit law such as Ohms Law, Thevenin Laws etc - Identify the parameters given- Analyze into the input/output for the system and build a

loop using electric circuits law.


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De sign Ope rations

If the transistor and supplies are specified,the design process will simply determine therequired resistor for a particular design.Once the theoretical values of the resistorsare determined, the nearest standard commercial values are normally chosen and

any variations due to not using the exact resistance values are accepted as part of thedesign.

R unknown =V R /I R

e s gn o a as c rcu w an e m e r e s gn o a as c rcu w an e m e r


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f ee dback r e sistor f ee dback r e sistor

The emitter resistor is to 1/10 of the suppl y voltage

De sign of a bias circuit with anDe sign of a bias circuit with an


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R E and R C cannot proceed directly from theinformation just specified.R E to provide dc bias stabilization so that thechange of collector current due to leakage currentsin the transistor and the transistor beta would not cause a large shift in the operating point.

The R E cannot be unreasonably large because thevoltage across it limits the range of swing of thevoltage from collector to emitter.V E typically -1/10 from supply voltage

De sign of a bias circuit with anDe sign of a bias circuit with ane mitt e r f ee dback r e sistor e mitt e r f ee dback r e sistor


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Exam p le 3

Determine the resistor values for the network,for

the indicated operating point and supply voltage.

(b e ta ind epe nd e nt )(b e ta ind epe nd e nt )


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The emitter resistor is to 1/10of the suppl y voltageTo determine R1 and R2 use 10R 2 RE

( p )( p )

Transistor as switchingTransistor as switching


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Transistor as switchingTransistor as switchingn e tworksn e tworks

Transistor wor ks as an inverter in computer circuits.Operating point switch f rom cut -off to saturation along the load line f or proper inversion.In order to understand, we assume that ;

IC=ICEO =0 m AV CE =V sat =0 V

One must understand the transistor graph output and load -line anal ysis to descri be and discuss a bout the

transistor switching networ ks.

Transistor as switching n e tworksTransistor as switching n e tworks


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Tim e int e r val


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Tim e int e r val (continu e d )Tim e int e r val (continu e d )


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Troubl e shootingTroubl e shooting

How to define and encounter transistor circuit problem?


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Documents

4.DC1 Biasing - BJTs