MCU(Scan_start)MCU

1

I/OClk5050MIRstI

2 MCU

I/OScan_StartIMCUMCU_Tab_Addr[3:0]MCUIMCU_Tab_Dataw[7:0]MCUIMCU_Tab_Rd_nMCUIMCU_Tab_We_nMCUIState_Reg[7:0]OMCU_Tab_Datar[7:0]MCUO

3 RAM

I/OScan_RAM_Addr[7:0]RAMORAMScan_RAM_Dataw[7:0]RAMOScan_RAM_Datar[7:0]RAMISacn_CS_nRAMOScan_We_nRAMOScan_OERAMO

Next State Logic

Present State Register Logic

Output Logic

Combinational Logic

Combination Logic

Squential Logic

Clk

Next

State

Outputs

Inputs

State

Verilog HDL module fsm1 (clk,reset,MCU_tab_rd_n, MCU_tab_we_n,scan_start);reg [1:0] c_state;reg [1:0] n_state;parameter [1:0] IDLE = 2'b00, RW_TEST = 2'b01, DATA_TEST = 2'b10, ADDR_TEST = 2'b11;

Verilog HDL always @(posedge clk) beginif(reset==1)c_state

Verilog HDL n_state = IDLE;case (c_state)IDLE:beginif (MCU_tab_rd_n==0 || MCU_tab_we_0) n_state = RW_TEST;else ifscan_start==1_ n_state = DATA_TEST;end RD_TEST:begin

always alwaysassign

One-hotOne-Hot

Next State Logic

inputs

Present State

next

State & outputs

state

clk

Combinational logic

squential logic