- ISE ModelsimISE

- ISEImplement 3TranslateMapPlace & Route

- Xilinx XilinxPLD

- 5CLKRESETLAP_LOADMODESRTSTPHDLEDIFUCF 1Source Tabstopwatch 2ProjectNew SourceImplementation Constraints File 3 stopwatch.ucf Next 4stopwatchUCFUCFNextFinish

- XilinxISE 1wtut_edif.zip 2Zip9.1

- 3ISE ISimISim>ise PC->->Xilinx ISE Design Suite 11->ISE->Project Navigator

-4EDIF 1File->New Project 2EDIF_Flow 3EDIFtop_level SourceType() 4Next 5stopwatch.edf 6stopwatch.ucf 7Next

- 8 --Device Family : Spartan3a --Device : xc3s700a --Speed Grade : -4 --package : fg484 9 10Next 11Finish 12timer_preset.ngcEDIF_Flow Sourcestopwatch.edfstopwatch.ednimplement

- 1Source Tabstopwatch 2ProcessesImplement Design 3PropertiesProcesses PropertiesTranslateMapPlace and RouteTiming Report

- 49.1Advanced 5Place & Route Properies 6Place & Route Effort Level(Overall)High

-

- UCF 1Source TabStopwatch 2ProcessesUser Constraints 3Create Timing Constraints9.4

-

- ISEISEimplementImplement DesignNGDBuild 1NGD 2 3UCF

- Create Timing Constraints 1UCF 2 1NGDNative Generic Database NGDNCD (Native Circuit Description) 2UCF (User Constraint File) NGDUCFUCF

-

- 9.3UCFNGDBuildUCFNGDNGD stopwatch.ngd stopwatch.ucf PERIODOFFSET INOFFSET OUTTIMEGRP OFFSET INUCF9.6

- 1CLK 2Specify Time 3Time7.0

- 4ns 5 Time60

6ps 7OK50% 8Constraint Type treeTiming Constraints()Input 9Global OFFSET INclkOFFSET IN

-109.6Next

-119.7External setup time()(offset in)6ns

- 12Data Valid duration()6nsCLKGlobal OFFSET IN 13Finish . 14Constraint Type treeTiming Constraints()Output 15Global OFFSET OUTclkOFFSET OUT

- 169.8External clock to pad()(offset out)38 nsCLKGlobal OFFSET OUT 17OK

- 189.9Shift-Clicksf_dsf_d

- 19Create Time Group 20Create Time Group()display_grpOK 21if you would like to create an offset constraintoffsetOK

- 229.10External clock to pad(offset out)32ns

- 23OK 24File->Save 25File->Close

-PlanAheadI/O PlanAheadNGDPlanAheadUser Constraint File,UCFUCFPlanAheadDesign Rule Check,DRC,

-PlanAheadI/O UCFNGDIOB 1Sourcesstopwatch 2+User Constraints 39.11I/O Pin Planning (PlanAhead)-Post-Synthesis

-PlanAheadI/O

-PlanAheadI/O I/OI/OI/OPlanAhead PlanAheadISEPlanAhead

-PlanAheadI/O 9.12Welcome to PlanAheadPlanAhead 49.12ClosePlanAhead

-PlanAheadI/O

-PlanAheadI/O 59.13I/OScalar Portslcd_e,lcd_cs,lcd_rw

-PlanAheadI/O

-PlanAheadI/O 69.14lcd_e(Package view)AB4

-PlanAheadI/O 7LCD_RS: Y14LCD_RW: W13 9.15I/O Port Properities\Site

-PlanAheadI/O

-PlanAheadI/O 8I/OI/OLAP_LOAD T16RESET U15MODE T14STRTSTOP T15 9FileSave Projectstopwatch.ucf 10FileExitPlanAhead

- 1Sourcesstopwatch 2ProcessesMapRunMap

- CLBsIOBs 1CLBIOB 2

-

- 19.16Design Summary/Report

- 2Design Summary()Detailed Reports()Translation ReportMap report 3 4

-

- Post-Map Static Timing Report

- 50/50 50/50 50%10ns20ns

- PERIOD 1Processes+Map 2Generate Post-Map Static Timing 39.16Analyze Post-Map Static Timing Report

-

- 49.17timing constraintTS_dcm_inst_CLKX_BUF

- 88.0 12.0 5File Close

- PARPlace & Route 1 2 PAR

- PAR 1ProcessesPlace & Route 2+Place & Route 3Place & Route Report 9.2Pad ReportAsynchronous Delay Report

-

- 9.18

-FPGA Editor FPGA EditorFPGAFPGAsFPGANCDNMCPCFPhysical ConstraintsFPGA 1 2 3 4BitGenbitstream 5Integrated Logic Analyzer (ILA)

-FPGA Editor FPGA 1+Place & RouteView/Edit Routed Design (FPGA Editor)9.20

-FPGA Editor 29.21FPGAAll Nets

-FPGA Editor 39.22clk_262144K ()

- Post Layout Timing Report 1Generate Post-Place & Route Static Timing 2Analyze Post-Place & Route Static Timing ReportTiming AnalyzerDesign SummaryTiming ConstraintTiming Analyzer

- stopwatch Post-Place & Route Static Timing Report 1Post-Map timing 80%90%post-layout30%40% 2Post-layout50/50

- 3

-PlanAhead PlanAheadPlanAhead 19.23ProcessPlace & Route()Analyze Timing/Floorplan Design(PlanAhead)

-PlanAhead 29.24PlanAheadTiming ResultDeviceProperities

-PlanAhead

- ModelsimXilinx ISE

- 1HDLVHDLVerilog NetGen 2VHDLVerilog HDL 3

- 1Sources tab(xc3s700A-4fg484)Properties 2ISEProject NavigaterModelSimISENC-Sim VCSNetgenISEProject NavigatorISE SimulatorVHDL/VerilogModelsim

-ModelSim Xilinx ISE MentorModelSimISEModelSim ISEXilinx ISE ModelSimISE

- Modelsim 1Sourcessources forPost-Route Simulation 2stopwatch_tb 3ProcessesModelSim Simulator+

- ModelSimModelSimISEmodelsim.exe.ModelSimprocessesModelSim locationEdit>PreferencesISE General+ISEIntegrated ToolsModel Tech Simulatormodelsim.exec:\modeltech_xe\win32xoem\modelsim.exe

- 4Simulate Post-Place & Route ModelPropertiesSimulation Model Properties9.24NetGen

-

- Advancedglobal setting Display Properties ModelSimISE Simulation Properties 9.25ModelSimHelpSimulation PropertiesSimulation Run Time2000nsOKProcess Properties

-

- 5 Simulate Post-Place and Route ModelISENetGenISEModelSim 100HzDCM

- WaveISEsignalsignalstructure 1Signal/Object windowWave windows 2Signal/Object windowAdd > Wave >Selected Signals

-ModelSim6.0Undock1Structure/Instance windowuut+9.26Structure/InstanceStructure/Instance VerilogVHDL2Structure/InstanceEdit > Find

-3X_DCMEntity/Module4ModelSimX_DCMX_DCMsignal/objectsDCM5signal/objectsEdit > Find6CLKINExact7CLKINCLKINsignal/objectsWave8RSTCLKFXCLK0 LOCKEDsignal/objects

- CtrlAdd to Wave > Selected Signals

-ModelsimWaveDCM1Wave23WaveInsert > Divider4DCM Signals5CLKIN

- Tools > Options > Wave Preferences2OK 69.27

-ModelsimModelsimWaveWave

- 1Restart Simulation2RestartModelSimrun 2000nsEnter32000nsWaveDCM

-

-DCMCLK050MhzCLKFX26MhzLOCKEDDCMLOCKEDDCMModelsim CLK0

-1Add > Cursor2LOCKEDCLK034Find Next TransitionCLK052000050Mhztest benchDCM CLK06CLKFX3846226Mhz

-ModelSimWave1WaveFile > Save Format2Save Formatwave.dodcm_signal_tim.do3SavewaveFile > Load

ISim- ISE 1SourcesPost-Route Simulation 2test bench(stopwatch_tb) 3ProcessesXilinx ISE+ 4Simulate Post-Place & Route ModelProperties 5Simulation Model PropertiesNetGen 6Advanced

ISim- 7ISE Simulator Properties9.28

ISim-8Simulation PropertiesSimulation Run Time2000ns9OKProcess Properties

- ProcessesSimulate Post-Place and Route ModelProject NavigatorNetGenISE 100HzDCM

- ISEwaveformSim HierarchylDCM 1Instances and Processesstopwatch_tb>9.29 VHDLSim 2UUT> 39.29Inst_dcm1_DCM_SP_INST

-

- 4Object()lockedAdd to Wave Window 5SIM HierarchyX_DCM_SPRSTCLKFXCLK0CLKINCtrl

- 1waveform9.30

- ISEISEwaveformwaveformRestart SimulationSim Consolerun 2000nsEnter2000nsSimulationDCM

-DCMCLK050Mhz,CLKFX26MhzLOCKEDDCMISECLK0

-

1waveAdd Measure 2LOCKEDCLK03.31CLK0

-

- 320ns50Mhztest benchDCM CLK0 4CLKFX38.5ns26Mhz

1ISE2345ISE6Modelsim7