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第六章 CPU 设计. 6.1 CPU 的功能和组成 6.2 一个非常简单 CPU 的设计与实现 6.3 相对简单 CPU 的设计和实现 6.4 简单 CPU 的缺点 6.5 实例: 8085 微处理器的内部结构. 同济大学 软件学院. 6.1 CPU 的功能和组成. 6.1.1 CPU 的功能 CPU 有四个方面的功能: 1. 指令控制: 程序的顺序控制。 2. 操作控制: CPU 管理并产生由内存取出的每条指令 的操作信号,把各种操作信号送往相应的部件,控 制部件工作。 - PowerPoint PPT Presentation
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6.1 CPU6.2 CPU6.3 CPU6.4 CPU6.5 8085
CPU
6.1.1 CPU CPU 1. 2.CPU 3. 4.6.1 CPU
6.1.2 CPUCPU /ALU
1. CPU MAR MDR
2. / 3. I/O
(1) PC 1 (2) IR (3) IR
(4) (5)
6.1.3 1. 2. PC
3. 1CPU ADD R0(R1) ((R1)) ( R0)R0
((R1)) ( R0)R0(1) (PC)MARRead(2) (PC)1PC (3) MMDRIR (4)(R1)MARRead (5) MMDRY (6)(Y)(R0)Z (7)(Z)R01
JC D IF C1 THEN (PC)DPC (1)(PC)MARRead (2) (PC)1 PC PC1PC (3) MMDRIR IR (4) IF C1 THEN(PC)Y (5) YIR(D)Z (6)(Z)PC
2CPU ADD R0(R1)ALUFABADDFABSUB FA1INCFA1DECFAGBFGon
IDIRPCR0R1MARMDRTEMPYGIRBPCBR0BR1BFMARMARBTEMPBFYADDSUBAReadWriteR7R7BABUSDBUSINCDECBGonFTEMPFMDRFR7FR!FR0FPCFIRFBADD R0(R1)
(PC)MARRead PCBGonFMAR Read(2) (PC)1PC INC(3) MMDRIR MDRBGonFIR (4)(R1)MARRead R1BGonFMAR Read (5) MMDRY MDRBGonFY (6)(Y)(R0)R0 R0BADDFR0
3CPU ADD X(R1),(R2)+ ALUFABADDFABSUB FA1INCFA1DECFAGBFGonX :X+R1 R2R2+1 R2
(10) (R2)MARRaadR2)YR2BGonFMARReadFYR2Z(11) (Y)1R2INCFR2(R2)+1R2(12) MDRYMDRBGonFYY(13) (Y)+(TEMP)MDR (MDR)MEMWriteTEMPB ADDFMDR Write(14)
6.1.4 1 CPU
CPUCPUCPU
2
6.1.5 CPUCPU hardwired control microsequencer ()
1CPU CPU (CPU) CPU
CPU CPU
2CPU 3CPU
6.2.1 CPU 1648 6A[5..0] 8D[7..0] 2AC8 34
6.2 CPU
4 6ARA[5..0] 6PC 8DRD[5..0] 2IR
6.2.2 1. A[5..0] 2. CPUD[7..0]CPU
FETCH1: ARPC FETCH2: DRMPCPC1 FETCH3: IRDR[7..6]ARDR[5..0] PC1
6.2.3 CPU CPU
6.2.4 6.2.4.1 ADD CPU ADD1: DRM ADD2: ACACDR
6.2.4.2 AND AND1: DRM AND2: ACACDR6.2.4.3 JMP JMP1: PCDR[5..0] PCAR6.2.4.4 INC INC1: ACAC+1
CPU
6.2.5 CPU CPU FETCH1: ARPC FETCH2: DRMPCPC1 FETCH3: IRDR[7..6]ARDR[5..0] ADD1: DRM ADD2: ACACDR AND1: DRM AND2: ACACDR JMP1: PCDR[5..0] INC1: ACAC1
1 CPU2CPU
1. AR: ARPCARDR[5..0]PC: PCPC1PCDR[5..0]DR: DRMIR: IRDR[7..6]AC: ACACDRACACDRACAC1
2. (1) ARDRIR (2) PCAC 1
1. AR 2. IR IR 3. AC 4.88 62
5. ACACDRACDR CPU ALUCPU FETCH2: DRMPCPC1 FETCH3: IRDR[7..6]ARDR[5..0]
AR:ARPCARDR[5..0]PC:PCPC1PCDR[5..0]DR:DRMIR: IRDR[7..6]AC:ACACDRACACDRACAC1
6.2.6 ALU 1ALU 2 8 82 3
ALU
6.2.7
CPU94 4-16 7
1. FETCH10 CLR2. INC FETCH21 FETCH32 ADD1ADD2 AND1AND2
3. LD (1) LD
(2) IR 10IR[1..0] IR=001000 IR=011001
CPU
(4) ADD18AND1 9ADD2 ADD1ADD2 2 1IR[1..0]0 ADD1AND1JMP1INC1 8101214 ADD29 AND211
INCCLRLD FETCH1FETCH2 ADD1AND1INC CLR (ADD2AND2JMP1INC1) LDFETCH3
ARPCDRIRMALU ARFETCH1ARPC FETCH3ARDR[5..0] ORCPUARLD PCDRACIR PCLOAD = JMP1 PCINC = FETCH2
FETCH1: ARPCFETCH2: DRM PCPC1FETCH3: IRDR[7..6] A RDR[5..0]ADD1: DRMADD2: ACACDRAND1: DRMAND2: ACACDRJMP1: PCDR[5..0] INC1: ACAC1
DRLOAD = FETCH2 ADD1 AND1ACLOAD = ADD2 AND2ACINC = INC1IRLOAD = FETCH3 ALUALUSEL ALUSELAND2CPUADDANDALUAC ALUSEL0ALU ALUSEL1
DR FETCH3IRDR[7..6]ARDR[5..0] ADD2ACAC+DR AND2ACACDR JMP1PCDR[5..0] DRBUS
MEMBUS = FETCH2 ADD1 AND1 PCBUS = FETCH1 READ (CPU)READ = FETCH2 ADD1 AND1
6.2.8 1. 0: ADD 41: AND 52: INC3: JMP 04: 27H5: 39H
2. CPU ADD4: FETCH1FETCH2FETCH3ADD1ADD2 AND5: FETCH1FETCH2FETCH3AND1AND2 INC: FETCH1FETCH2FETCH3INC1 JMP0: FETCH1FETCH2FETCH3JMP13. 0
6.3.1 CPU 164K8 A[15..0] D[7..0] 2CPU 8AC 6.3 CPU
R8 CPU Z 3
4 16ARA[15..0] 16PC 8DRD[7..0] 8IR 8TR
6.3.2 FETCH1: ARPCFETCH2: DRMPCPC1FETCH3: IRDRARPC JMPZJPNZ
6.3.3 6.3.3.1 NOP NOP1: 6.3.3.2 LDAC LDAC
LDAC1: DRMPCPC1ARAR1 (LDAC LDAC2: TRDRDRMPCPC1 LDAC3: ARDRTR LDAC4: DRM LDAC5: ACDR
6.3.3.3 STAC STACLDAC STAC1: DRMPCPC1ARAR1 STAC2: TRDRDRMPCPC1 STAC3: ARDRTR STAC4: DRAC STAC5: MDR
6.3.3.4 MVACMOVRMVAC1: RACMOVR1: ACR6.3.3.5 JUMPJUMP1: DRMARAR+1JUMP2: TRDRDRMJUMP3: PCDRTR
6.3.3.6 JMPZJPNZJMPZ Z=1JMPZY1: DRMARAR1 JMPZY2: TRDRDRM JMPZY3: PCDRTR Z=0JMPZN1: PCPC1 JMPZN2: PCPC1
JPNZZ=0 JPNZY1: DRMARAR1 JPNZY2: TRDRDRM JPNZY3: PCDRTRZ=1 JPNZN1: PCPC1 JPNZN2: PCPC1
6.3.3.7 ADD1: ACACRIFACR0THEN Z1 ELSE Z0 SUB1: ACACRIFACR0THEN Z1 ELSE Z0 INAC1: ACAC1IFAC10THEN Z1 ELSE Z0 CLAC1: AC0, Z1 AND1: ACACRIFACR0THEN Z1 ELSE Z0 OR1: ACACRIFACR0THEN Z1 ELSE Z0 XOR1: ACACRIFACR0THEN Z1 ELSE Z0 NOT1: ACAC'IFAC'0THEN Z1 ELSE Z0 CPU
1. 2 AR: ARPCARAR1ARDRTR PC: PCPC1PCDRTR DR: DRMDRAC IR: IRDR R: RAC TR: TRDR6.3.4
AC: ACDRACRACACR ACACR ACAC1AC0 ACACRACACRACACR ACAC' Z: Z1Z0
3 ARPC DRIRRTR
AR: ARPC ARAR+1 ARDRTRPC: PCPC1 PCDRTR DR: DRM DRAC IR: IRDR R: RACTR: TRDRAC:Z:ACLOADREADWRITE
CPUALU ALUAC ACALU CPUALU0 Z 4 ARIR
AR: ARPC ARAR+1 ARDRTRPC: PCPC1 PCDRTR DR: DRM DRAC IR: IRDR R: RACTR: TRDRAC:Z:8[7..0]8[7..0]
D[7..0]
16 Z ALUNOR NORZ
5 FETCH3CPUIRDRARPC FETCH3: IRDRARPC DRIR IRDR IR
8[7..0]
LDAC2TRDRDRM LDAC2:TRDRDRMPCPC1 TRDRCPUDR TRTR
LDAC3DRTR DR15..8TR7..0 LDAC3: ARDRTR DR15..87..0
6.3.5 ALU 1ACLDAC5: ACDR MOVR1: ACR ADD1: ACACR SUB1:ACACRINAC1: ACAC1 CLAC1: AC0AND1: ACACR OR1:ACACRXOR1: ACACR NOT1:ACAC'
2 AC(1)
LDAC5: ACBUSMOVR1: ACBUSADD1: ACACBUSSUB1: ACACBUSINAC1: ACAC1CLAC1: AC0AC0BUS0AC0BUS0ACACBUS0ACACBUS1ACAC01AC000
AC0 ALU BUSBUS0 ALU
(2) 4 84 MUX ACBUSACBUSACBUSAC'3ALU AC
6.3.6 37 1 2 IR
0000 XXXX NOR 3CPU
4CPU FETCH1 T0 FETCH2 T1 FETCH3 T2
LDAC LDAC1 ILDAC T3 LDAC2 ILDAC T4 LDAC3 ILDAC T5 LDAC4 ILDAC T6 LDAC5 ILDAC T7
5CLRINC CLR CLR INC INC CLRINC6AR
7ALU ALUS1ADD1SUB1INAC1 ALUS4SUB1INAC16.3.7 RS-CPUWeb
6.4.1 CPU 6.4 CPU
SPARC
RISC CPU:: 1 : 48CPUCPU164
Intel Intel4004 8008808080856 80868 802868038680486 Pentium8 3216
Itaium4MB Itanium128 128 Pentium16Kcache 32K
CPU 6.4.2 CPU CPU
6.4.3
6.4.4 CPU AB
ABABAND CPUOR 6.4.5
Intel 8085
6.5 8085
1ALU 82 ABCDEH LSP ALU
3
I/O I/O