6금속공정_20111229151922 al, cu, au coreano

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  • 5/24/2018 6 _20111229151922 al, cu, au coreano

    1/61W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    1I. II. -III. IV. V. VI.VII.CMP

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    2

    I.

    1):contact, interconnection, connection to outside

    2) IC:yield, reliability

    3) system(1)(2)(3)

    1.

    2.1)

    (1):,,,

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    3

    (2):(3)(4):,(5) bondability :

    2)(1): Pt-Si, Al (2):(3)( 3,000 4,000 ppm/)

    Al Cu Au Mo Pt Ag Ta Ti W

    2.8 1.7 2.44 5.7 10.5 1.46 13.0 55 5.5

    3)(1) step coverage, electromigration

    (2) corrosion, oxidation,,

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    4

    1) Al : electromigration, corrosion 2) Al + 2% Si

    3) Al + 2% Si + 4% Cu

    4) Pt - Si

    5) Pt(700) : Si - Ti(1000) - Pt(2000) - Au(1mil)Pt(700)Pt-Si(sintering)Pt

    Ti

    (1000

    )Pt(2000)Au(1mil)

    6) Mo, Ta, W-Au, Cu-Au, Ti-Au,

    3.

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    properties Al Au Mo Pt Ta W

    deposition evap. evap. sputter or CVD from fluorides

    compatibility G - G G G G

    adherence G N G - G G

    delineation G N Y D D D

    bondability G G N N N N

    contact resistance G - H B H H

    conductivity 2.7 2.44 5.4 10.5 27 5.5

    surface coverage depends on deposition condition

    electromigration resistance F B G G G G

    corrosion resistance F B F G G Gstability G G G G G G

    process temperature() 500 - 800 - 800 800

    : G(good), N(no), Y(OK), D(difficult), H(high), B(best), F(fair)

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    6

    1.1) Schottky2) Ohmic:tunneling

    2.1) n

    II. -

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    7

    eV1.4qM

    eV95.0qox

    eV8EgeV15.4q

    Si

    eV5q s

    SiFE

    cE

    vE

    MFE

    aluminum silicon oxide silicon

    cE

    vE

    2) M-O-S

    < Na=21015/cm3pAl>

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    3) doping

    , Si : B : VR : N :

    BN?

    )V(Nq

    2

    C

    1

    V

    Nq

    2

    1

    WC

    RB

    Si

    2

    2

    1

    RB

    SiSi

    21

    RBSi

    qN

    )V(2W

    for step junction

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    9

    3.1) N

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    10

    (1) Schottky diodeI-V

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

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    < Al/n-Si SchottkyI-V>

    2) Schottky diodeI-V

    Schottky diode(IR=10-6A): Si step junction

    60%

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    12

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    2) 51017/cm3< N < 1019/cm3 :

    3) N>1019/cm3: tunneling currentOhmic contact(1):

    N1

    expW

    1exp

    dI

    dVAR

    0v

    c

    2) Al-silicon

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    III.1.(CVD)

    1) better uniformity, better step coverage2) Al: 6005003) 90CVD: W, Mo4) Al CVD

    2.1): filament, e-beam, RF, flash, sputtering(1)

    - : 1 torr 710-6cm (for N2) 10-3torr 5 cm (for N2) 0.5 (for electron)

    - - 10-6torr

    16

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

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    (2) filament, RF e-beam, flash

    (3) filament

    17

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

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    heater : W, Ta, Mo, Pt()heater

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    18

    tight beamdiffuse beam

    pure metalrefractory metalalloyx-ray

    (6)

    alloywire feeding,e-beam20%

    19

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    19

    2)(1)

    chamber step coverage(Ar 1-10 mtorr) cleaning

    (2):,(DC)

    20

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    20

    3.1) in-situ thickness monitor

    (1) crystal monitor

    (2) interferometer : laser

    DA

    MTDATDVM

    MK

    P

    K

    M

    fP

    M

    Kf

    ===

    =

    ===

    1

    1,

    f :M:K:P:D:T:A:

    21

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    21

    2)(1).(2).(3).(4).(5) 510-6torr.(6).(7).(8).(9).

    22

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    22

    3)(1):,,,,,

    grain, roughness,(2): stylus(3)

    : 4-point probe4) Na+: HTB C-V

    23

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    23

    IV. 1.

    1) grain size2) Al2O3: T>250,10-810-5 torr

    PTRG

    24

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    25

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    3) hillock(1):(2) hillock: edge, flat-topped, spike hillock(3):Alstressstrain

    stress: Si (3.3 ppm/), Al (23.6 ppm/)

    (Te)(Ta)strain

    26

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    26

    (4) hillockself-diffusion rate: Sn, Cd, Insite: Sihillock:

    Te(

    ) Ta(

    ) Dcycled(/cm2

    ) Duncycled (/cm2

    )23 430 8.7107 4.0 107200 430 1.5 106 5.0 105400 430 3.4 104 6.0 10327 223 6.0 106 3.2 106200 179 5.2 105 2.8 105400 237 0 0

    1) uncycled : RT Ta, 2) cycled : RT Ta

    27

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    2.1) : 10

    -5

    cm2

    /2525 m22) : 500, 10 min. 450, 30 min.3) : Al (2.65 cm), Al-Si (1%) (3.0 cm)4) > 0.002 ( 51019dopants/cm3) rectifying contact

    28

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    (cm) ( cm)Au 2.35 Al-Ni(1%) 2.75Al 2.65 Al-Si(1%) 3.0

    Mo 5.7 Al-Ti(1%) 5.53

    Pt 10.6 Al-Cr(1%) 5.78

    Ti 55.0 Al-Pt(1%) 2.9

    Cu 1.7 Au-Ni(10%) 10.2

    3.1) : O2, H2O, H2, N2, CH42) : H2O, O2

    2Al + 3O2 = 2Al2O3

    3) :3SiO2+ 2Al 2Al2O3+ 3Si (Alalloy)

    22322 H

    2

    3)OHOAl(

    2

    1OH2Al

    29

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    29

    oxide

    heat of formation(kcal/mole)

    oxideheat of formation

    (kcal/mole)

    Ta2O5 -500 WO3 -200

    Al2O3 -399 MoO3 -180

    V2O3 -290 Cu2O -40

    Cr2O3 -270 Ag2O -7

    TiO2 -218 Au2O3 +19

    SiO2 -205 - -

    30

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    4.Coverage1) shadowing : slope, geometric, self shadowing

    shadow:

    Dh)XL

    21( o=

    })X(0.5LD/{arctan o>

    31

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    2) shadowing deposition system

    biaxial planetary source source-substrate

    32

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    5. Adhesion1) SiO

    2

    2): tape(3M)

    materials shearing force (108dynes/cm2) adherence to SiO2

    FeSi 37 weak

    CoSi 120 strongCoSi2 70 intermediate

    PtSi2 170 very strong

    Al 170 very strong

    Ti 170 very strongAu - very weak

    Co 54 intermediate

    Mo 113 strong

    33

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    6.1):, low cost, high conductivity, good adhesion,

    easy patterning, low contact resistance

    Al-Si alloy, good bondability,.

    2): difficult CVD deposition,electromigration, corrosion, hillock formation

    Al-AuSi into Al grain boundary reliability

    siliconstress,

    34

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    V.1. Double metal

    35

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    (1) 1st metal

    Al, Al-Si, Al-Cu, Al-Si-Cu

    Al : e-beam, sputteringAl-Si : double gun e-beam, sputtering

    Al-Si-Cu : flash, sputtering(2) 1st insulator SiO2, Si3N4, Al2O3, Ta2O5, WO2, PSG: CVD, sputtering

    (3) 2nd metal

    Al1st metal(4) passivation

    PSG : 3%, 0.8~1m,85 /sec : 35 /sec for PSG : CVD()

    1)

    36

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    2)(1) sharp edge :

    1st &2nd metalshort 2nd metal crack reliability

    (2) hillock Al deposition(380) PSG deposition (200) , alloy (450)

    (3) SiO2: chamber, Al film.(4)(rework)

    37

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    (5) sharp edge

    : hard baking

    etch

    Al hillock:, Al-Si PECVD SiO2deposition :CVD systemSiO2contamination.

    (6) : polymide plasma etching

    38

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    2.1)

    2): (,,)(,)

    (,)

    39

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    3)(1):,

    5000(2):,,

    m(1Al 1.65Al2O3)

    4)

    40

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    (1):(2)

    (3)Faraday

    V:, :, F: 96500 C/mole, m=6, S:,H:

    M: mole, Q:, :,J:

    Fm

    MJ

    dt

    dH

    dt

    dQ

    Fm

    M

    dt

    dHS

    dt

    dV

    Fm

    MQV

    ==== ,,

    high voltage low voltage

    electrolyte 4 % H3PO4 4 % H2SO4operating voltage 133 20

    barrier layer thickness() 1,500 250

    41

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    VI.1.-

    1) eutectic point 5771.6%2) 3500.1%

    3)Al spike alignmentpackaging (111)(110)36

    42

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    4) spike(1): step coveragetrade off(2)Al(3) 200(4) barrier metal: Ti, W, Ta, Ti-W -trade off(5)(6) Al-2% Si

    43

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    2.1) : bipolar

    MOS2) :Na+

    barrier(Si3N4, Al2O3, PSG)

    44

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    3. Electromigration1)

    q :q* :: q* = 20 30q

    2)

    /kT)Wexp(DkT

    JNqNEF

    /kT]Wexp[DD

    q

    kT

    DE,J

    NENEX

    NDF

    s0

    *

    s0

    *

    ==

    =

    ==

    =+

    =

    AlintoAlofdiffusionself:

    45

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    3)(1): temperature gradient(2) diffusion: surface diffusion

    grain boundary diffusionbulk diffusion

    (3): grain,: D

    o, W

    s, J

    stepcurrent crowding4) ElectromigrationMTF

    (1) MTF

    )exp()exp()exp(MTFkT

    W/L

    Jn

    WT/L

    F

    A s=

    46

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    (2) MTF

    , W: AlT: Aln: 1 (contact)2~3()

    MTF Ws(eV)

    grain size: large (>3 m) 2 ~ 3 0.5 ~ 0.6small (

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    VII. CMP1.

    1)2) 1980,3), MOSFET4)

    48

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    2. CMP1)2)

    3) () ()

    4)nm

    planarization) Damascene)

    49

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    3. CMP1)

    :, :, : : :

    polishing pad

    slurrydispenser

    platen

    chuck

    wafer

    spindle

    CMP

    50

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    2)

    :um

    51

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    3):+:pH:: SiO2, Al2O3, CeO2CMP:+ Al2O3 CMP

    52

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    4) CMP:,,,:,,,, pore,

    5) CMP

    53

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    4. CMP1)

    ->

    SiO2: SiO2-> Si(OH)4 W: W -> WO3

    Cu: Cu -> Cu2O2)

    :::

    kp (), P (), v (), E (Young)

    1/ (2 )p pR k Pv k E= =

    54

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    5. CMP1)

    STISi3N4

    stopping layer)

    55

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    1) Trench Definition: Buffer Oxide Growth, Nitride Deposition,Isolation Lithography

    2) Trench Etch: Nitride Etch, Oxide Etch, Silicon Etch

    3) Photoresist Strip

    4) Thermal Oxidation

    5) CVD Oxide Fill

    6)Chemical Mechanical Polish

    7) Nitride Etch

    STI

    56

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    2)CMP: (contact)(via)(plug)CMP:CMP

    7

    57

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    W. Y. Choi, B.-G. Park, and J. D. Lee, Fundamentals of Silicon IC Processes

    6.1):

    ITRS 2010)Year 2010 2013 2016 2019 2022

    MPU/ASIC Metal 1 (1/2 pitch) 45 27 18.9 13.4 9.5

    Dielectric Constant (ILD) 2.3~2.5 2.1~2.3 1.9~2.1 1.7~1.9 1.5~1.7

    58

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    2) SiO2 (k > 2.7): (k < 2.7): tetramethoxysilane(TMOS)tetraethoxysilane(TEOS)-

    :(air gap)3)

    ,/,, , CMP,,,,,,

    59

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    7.1)

    :,,

    2):(1.7ucm),electromigration,,,

    :,, ,

    60

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    3):: via filling

    4) : via trench

    . ..(adhesion) (barrier) . .

    . CMP.

    61

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    . a), b),c), d), e)CMP