8 VHDL EDA
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8.1 8.1.1 ENTITY IS [GENERIC ( );] [PORT ( );]END ENTITY ;8.1.2
GENERIC GENERIC([ : [ : ] { ; : [ : ] } ) ;
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8-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY andn IS
GENERIC ( n : INTEGER ); -- PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO
0);-- c : OUT STD_LOGIC); END; ARCHITECTURE behav OF andn IS BEGIN
PROCESS (a) VARIABLE int : STD_LOGIC; BEGIN int := '1'; FOR i IN
a'LENGTH - 1 DOWNTO 0 LOOP IF a(i)='0' THEN int := '0'; END IF; END
LOOP; c 2) PORT MAP (a(0)=>d1,a(1)=>d2,c=>q1); u2: andn
GENERIC MAP (n =>5) -- n5 PORT MAP
(a(0)=>d3,a(1)=>d4,a(2)=>d5, a(3)=>d6,a(4)=>d7,
c=>q2); END;
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8.1.3 8.1 8-3LIBRARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL;USE
IEEE.STD_LOGIC_arith.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY
addern IS PORT (a, b: IN STD_LOGIC_VECTOR; result: out
STD_LOGIC_VECTOR);END addern; ARCHITECTURE behave OF addern IS
BEGIN result b, result => result); U2: addern PORT MAP
(a=>b(msb_operand downto msb_operand/2 +1),
b=>b(msb_operand/2 downto 0), result => a);END behave;
8-1 8-3
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8.1.4 PORT() 8.1 PORT ( : ; { : } ) ;
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8.2 1. ARCHITECTURE OF IS []BEGIN []END ARCHITECTURE ;
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8.2 2. 3.
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8.3 (SUBPROGRAM)8.3.1 FUNCTION
FUNCTION RETURN --FUNCTION RETURN IS -- [ ] BEGIN ; END FUNCTION
;
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8-4LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE packexp IS
-- FUNCTION max( a,b : IN STD_LOGIC_VECTOR) -- RETURN
STD_LOGIC_VECTOR ; FUNCTION func1 ( a,b,c : REAL ) -- RETURN REAL ;
FUNCTION "*" ( a ,b : INTEGER ) -- RETURN INTEGER ; FUNCTION as2
(SIGNAL in1 ,in2 : REAL ) -- RETURN REAL ; END ;PACKAGE BODY
packexp IS FUNCTION max( a,b : IN STD_LOGIC_VECTOR) -- RETURN
STD_LOGIC_VECTOR IS BEGIN IF a > b THEN RETURN a; ELSE RETURN b;
END IF; END FUNCTION max; --FUNCTION END; --PACKAGE BODY
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LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; USE
WORK.packexp.ALL ; ENTITY axamp IS PORT(dat1,dat2 : IN
STD_LOGIC_VECTOR(3 DOWNTO 0); dat3,dat4 : IN STD_LOGIC_VECTOR(3
DOWNTO 0); out1,out2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END;
ARCHITECTURE bhv OF axamp IS BEGIN out1 b THEN RETURN a; ELSE
RETURN b; END IF; END FUNCTION max; --FUNCTION FUNCTION max( a,b IN
BIT_VECTOR) -- RETURN BIT_VECTOR IS BEGIN IF a > b THEN RETURN
a; ELSE RETURN b; END IF; END FUNCTION max; --FUNCTION END;
--PACKAGE BODY -- max LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ;
USE WORK.packexp.ALL ENTITY axamp IS PORT(a1,b1 : IN
STD_LOGIC_VECTOR(3 DOWNTO 0); a2,b2 : IN BIT_VECTOR(4 DOWNTO 0);
a3,b3 : IN INTEGER RANGE 0 TO 15; c1 : OUT STD_LOGIC_VECTOR(3
DOWNTO 0); c2 : OUT BIT_VECTOR(4 DOWNTO 0); c3 : OUT INTEGER RANGE
0 TO 15); END;
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ARCHITECTURE bhv OF axamp IS BEGIN c1 value: "1111" ; END CASE ;
END PROCEDURE prg1 ;
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8-9 PROCEDURE comp ( a, r : IN REAL; m : IN INTEGER ; v1, v2:
OUT REAL) IS VARIABLE cnt : INTEGER ; BEGIN v1 := 1.6 * a ; -- v2
:= 1.0 ; -- Q1 : FOR cnt IN 1 TO m LOOP v2 := v2 * v1 ; EXIT Q1
WHEN v2 > v1; -- v2 > v1LOOP END LOOP Q1 ASSERT (v2 < v1 )
REPORT "OUT OF RANGE" -- SEVERITY ERROR ; END PROCEDURE comp ;
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8.3.4 (OVERLOADED PROCEDURE) 8.3 (SUBPROGRAM)8-10 PROCEDURE
calcu ( v1, v2 : IN REAL ; SIGNAL out1 : INOUT INTEGER) ; PROCEDURE
calcu ( v1, v2 : IN INTEGER ; SIGNAL out1 : INOUT REAL) ; ... calcu
(20.15, 1.42, signl) ; -- calcu calcu (23 320sign2 ) -- calcu
...
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1. IEEE
2. STD3. WORK
4. VITAL
8.4 VHDL 8.4.1 LIBRARY STD USE STD.STANDARD.ALL ;
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8.4.2 8.4 VHDL USE .. USE ..ALL LIBRARY IEEE ;USE
IEEE.STD_LOGIC_1164.STD_ULOGIC ;USE IEEE.STD_LOGIC_1164.RISING_EDGE
;
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8.5 VHDLVHDL PACKAGE IS -- END ; PACKAGE BODY IS -- END ;
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8-11 PACKAGE pacl IS -- TYPE byte IS RANGE 0 TO 255 ; -- byte
SUBTYPE nibble IS byte RANGE 0 TO 15 ; -- nibble CONSTANT byte_ff :
byte := 255 ; -- byte_ff SIGNAL addend : nibble ; -- addend
COMPONENT byte_adder -- PORT( a, b : IN byte ; c : OUT byte ;
overflow : OUT BOOLEAN ) ; END COMPONENT ; FUNCTION my_function (a
: IN byte) Return byte ; -- END pacl ; -- 8.5 VHDL
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8-12 PACKAGE seven IS SUBTYPE segments is BIT_VECTOR(0 TO 6) ;
TYPE bcd IS RANGE 0 TO 9 ; END seven ; USE WORK.seven.ALL ; -- WORK
ENTITY decoder IS PORT (input: bcd; drive : out segments) ; END
decoder ; ARCHITECTURE simple OF decoder IS BEGIN WITH input SELECT
drive INTCLK, LOAD => RSTALL, DIN=>B,QB=>QB);
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U3 : ANDARITH PORT MAP(ABIN => QB, DIN => A,DOUT =>
ANDSD);U4 : ADDER8B PORT MAP(CIN => GNDINT, A=>DTBOUT(15
DOWNTO 8),B=>ANDSD, S => DTBIN(7 DOWNTO 0), COUT =>
DTBIN(8) ); U5 : REG16B PORT MAP(CLK => INTCLK, CLR =>
RSTALL,D=>DTBIN, Q=>DTBOUT );END struc;
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(3) 1VHDLMAX+plusII87HF5H88-298-3 (4)
2No.182184316487658CLK7STARTSTART0
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(5) 3clock0clock0/0CLK88-28 (6) 48X816LPM (7) 8-248-298-323
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8-2 (1) 5-4(2)
38-303(8-5)TONETABA.VHDNOTETABS.VHDSPEAKER.VHDCPUMCUEDA
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8-5U1U2U38-5 18-5SPEAKERA5-4clk12MHzSPEAKERASPKOUTD
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1/2SPEAKERAclk11Tone[10..0] SPKOUTTone[10..0]
SPKOUTTONETABATone[10..0]=10363 28-5TONETABA
SPEAKERASPEAKERTONETABA 13NOTETABS
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clk4Hz13TONETABA 4Index[3..0]Index[3..0]
16TONETABAIndex[3..0]ToneIndex[3..0]NOTETABS 3NOTETABS
8138ROM4Hz0.2514NOTETABS VHDL34131036SPEAKERA 1NOTETABS
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4HzROM ROMToneIndex[3..0]TONETABA (3)
18-33NoteTabsROMmusicROM8-34ROM8-34(4) 2VHDLMAX+plusII
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(5) 3CLK12MHzclock912MHz12MHzclock9 12MHzCLK8Hz clock24HzClock2
4HzSPKOUTSpeakerCODE15HIGH1D5SOFNO.1(6) 4 18-34
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2NOTETABA 9512(7) 5ROM(8) 6NO.1(9) 18-31DelaySpkS (10) 2
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(11) 4VHDL 8-5 VHDL:
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8-30LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL;ENTITY Songer
IS PORT ( CLK12MHZ : IN STD_LOGIC; -- CLK8HZ : IN STD_LOGIC; --
CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);-- HIGH1 : OUT STD_LOGIC;
--8 SPKOUT : OUT STD_LOGIC );-- END;ARCHITECTURE one OF Songer IS
COMPONENT NoteTabs PORT ( clk : IN STD_LOGIC; ToneIndex : OUT
STD_LOGIC_VECTOR (3 DOWNTO 0) );
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END COMPONENT; COMPONENT ToneTaba PORT ( Index : IN
STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (3
DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tone : OUT STD_LOGIC_VECTOR (10
DOWNTO 0) ); END COMPONENT; COMPONENT Speakera PORT ( clk : IN
STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT
STD_LOGIC ); END COMPONENT; SIGNAL Tone : STD_LOGIC_VECTOR (10
DOWNTO 0); SIGNAL ToneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0);
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BEGINu1 : NoteTabs PORT MAP (clk=>CLK8HZ,
ToneIndex=>ToneIndex);u2 : ToneTaba PORT MAP
(Index=>ToneIndex,Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1);u3
: Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT
);END;
8-31LIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE
IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Speakera IS
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PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO
0); SpkS : OUT STD_LOGIC );END;ARCHITECTURE one OF Speakera IS
SIGNAL PreCLK, FullSpkS : STD_LOGIC;BEGIN DivideCLK : PROCESS(clk)
VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PreCLK 11
THEN PreCLK ToneIndex, inclock=>clk); END;
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8-34WIDTH = 4 ; --DEPTH = 256 ;ADDRESS_RADIX = DEC ;DATA_RADIX =
DEC ;CONTENT BEGIN -- 00: 3 ; 01: 3 ; 02: 3 ; 03: 3; 04: 5; 05: 5;
06: 5;07: 6; 08: 8; 09: 8; 10: 8 ; 11: 9 ; 12: 6 ; 13: 8; 14: 5;
15: 5; 16: 12;17: 12;18: 12; 19:15; 20:13 ; 21:12 ; 22:10 ; 23:12;
24: 9; 25: 9; 26: 9; 27: 9; 28: 9; 29: 9; 30: 9 ; 31: 0 ; 32: 9 ;
33: 9; 34: 9; 35:10; 36: 7; 37: 7; 38: 6; 39: 6; 40: 5 ; 41: 5 ;
42: 5 ; 43: 6; 44: 8; 45: 8; 46: 9; 47: 9; 48: 3; 49: 3; 50: 8 ;
51: 8 ; 52: 6 ; 53: 5; 54: 6; 55: 8; 56: 5; 57: 5; 58: 5; 59: 5;
60: 5 ; 61: 5 ; 62: 5 ; 63: 5; 64:10; 65:10; 66:10; 67:12; 68: 7;
69: 7; 70: 9 ; 71: 9 ; 72: 6 ; 73: 8; 74: 5; 75: 5; 76: 5; 77: 5;
78: 5; 79: 5; 80: 3 ; 81: 5 ; 82: 3 ; 83: 3; 84: 5; 85: 6; 86: 7;
87: 9; 88: 6; 89: 6; 90: 6 ; 91: 6 ; 92: 6 ; 93: 6; 94: 5; 95: 6;
96: 8; 97: 8; 98: 8; 99: 9;100:12 ;101:12 ;102:12 ;103:10;104:
9;105: 9;106:10;107: 9;108: 8;109: 8;110: 6 ;111: 5 ;112: 3 ;113:
3;114: 3;115: 3;116: 8;117: 8;118: 8;119: 8;120: 6 ;121: 8 ;122: 6
;123: 5;124: 3;125: 5;126: 6;127: 8;128: 5;129: 5;130: 5 ;131: 5
;132: 5 ;133: 5;134: 5;135: 5;136: 0;137: 0;138: 0;END ;
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8-3 8VHDLtennisMAX+PLUSIIballclkboard1cou4cou10mwaysound
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(1)
1VHDL8-35NO.3bainbbin81clr07clkclock24Hzsouclkclock51024Hzballout[7..0]8D1D2..D8countbh[3..0]countbl[3..0]76countah[3..0]countal[3..0]
32lamp7clock2speaker
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(2) 2NO.3clock51024Hzclock14Hz813/27/6 (3) 3VHDL:
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8-35LIBRARY IEEE; --use ieee.std_logic_1164.all;entity TENNIS
isport(bain,bbin,clr,clk,souclk:in std_logic;ballout:out
std_logic_vector(7 downto 0);countah,countal,countbh,countbl:out
std_logic_vector(3 downto 0);lamp,speaker:out
std_logic);end;architecture ful of TENNIS iscomponent sound port
(clk,sig,en:in std_logic;sout:out std_logic);end
component;component ballctrl
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port(clr,bain,bbin,serclka,serclkb,clk:in
std_logic;bdout,serve,serclk,ballclr,ballen:out std_logic);end
component;component ballport(clk,clr,way,en:in
std_logic;ballout:out std_logic_vector(7 downto 0));end
component;component board port (ball,net,bclk,serve:in
std_logic;couclk,serclk:out std_logic);end component;component
cou10 port(clk,clr:in std_logic;cout:out std_logic;qout:out
std_logic_vector(3 downto 0));
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end component;component cou4 port(clk,clr:in std_logic;cout:out
std_logic;qout:out std_logic_vector(3 downto 0));end
component;component mway port(servea,serveb:in std_logic;way:out
std_logic);end component;signal
net,couclkah,couclkal,couclkbh,couclkbl,cah,cbh:std_logic;signal
serve,serclka,serclkb,serclk,ballclr,bdout,way,ballen:std_logic;signal
bbll:std_logic_vector( 7 downto 0);beginnet"0010")THEN qqout
