A 60 GHz CMOS Power Amplifier Using Capacitive … 60 GHz CMOS Power Amplifier Using Capacitive Cross-Coupling ... Simulation result 0 5 10 15 20 25 30 35 40 ... manual auto 30 35

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of Technology



A 60 GHz CMOS Power Amplifier

Using Capacitive Cross-Coupling

Neutralization with 16% PAE

Hiroki Asada, Kenichi Okada,

and Akira Matsuzawa

Tokyo Institute of Technology, Japan

2





2011/10/11

Outline

• Back Ground

• Capacitive Cross-Coupling

Neutralization

• 3-stage Power Amplifier

• Measurement Result

• Conclusion

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2011/10/11

Motivation

60GHz CMOS direct-conversion transceiver

for multi-Gbps wireless communication

57.24GHz - 65.88GHz

2.16GHz/ch x 4channels

QPSK 3.5Gbps/ch

16QAM 7.0Gbps/ch

IEEE 802.15.3c specification

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2011/10/11

• Parasitic Capacitances causes low reverse isolation.

0

5

10

15

20

25

30

35

0 20 40 60 80 100 120M

ax

Ga

in[d

B]

Frequency[GHz]

Challenges for 60GHz PA

Parasitic Capacitance

lower MAG

j

YC

]Im[ 12GD

W=40um

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2011/10/11

Capacitive Cross Coupling[3]

• A cross-coupled capacitor between gate and drain of the opposite-side transistor works as negative capacitor.

– The reverse isolation is improved.

IN

OUTCx Cx

IN

OUT

-Cx -Cx

[3] W.L. Chan, et al., ISSCC 2010

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2011/10/11

Small signal equivalent circuit

Vi

CDBgmViCGS

Vo

CxCGD

RD

RD

CGD

CDBgmViCGS

Cx

-Vi -Vo

RG

RG

𝑘 =2Re 𝑌11 Re 𝑌22 − Re[𝑌12𝑌21]

|𝑌12𝑌21|=

2 + 𝜔2 𝐶𝐺𝐷 − 𝐶𝑋2𝑅𝐺𝑅𝐷

𝜔 𝐶𝐺𝐷 − 𝐶𝑋 𝑅𝐺𝑅𝐷 𝜔2 𝐶𝐺𝐷 − 𝐶𝑋2+ 𝑔𝑚

2

Stability

Maximum Available Gain

MAG =𝑌21𝑌12

(𝑘 − 𝑘2− 1) =𝜔2 𝐶𝐺𝐷 − 𝐶𝑋

2+ 𝑔𝑚2

𝜔 𝐶𝐺𝐷 − 𝐶𝑋(𝑘 − 𝑘2− 1)

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2011/10/11

Simulation result

0

5

10

15

20

25

30

35

40

0 20 40 60 80 100 120

MA

G,

MS

G[d

B]

Frequency [GHz]

w/ CCC

w/ CCC(calc.)

w/o CCC

0

1

2

3

4

5

0 20 40 60 80 100 120

Sta

bilit

yF

ac

tor

Frequency [GHz]

w/ CCC

w/ CCC(calc.)

w/o CCC

• Stability Factor is improved across entire frequency.

• The maximum available gain is improved about 5dB at 60GHz

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2011/10/11

Influence of TL

In actual layout, TL is needed to

connect 2 transistors.

10

12

14

16

18

20

0 2 4 6 8 10 12 14 16 18 20

Capacitance[fF]

Ma

x G

ain

[dB

] TL=50umTL=100umTL=150umTL=200um

Max Gain

0

1

2

3

4

5

0 2 4 6 8 10 12 14 16 18 20

Capacitance[fF]S

tab

Fa

ct.

TL=50umTL=100umTL=150umTL=200um

StabFact. (Sdd)

Tr.

Cap.

Tr.

TL

Vin+ Vin-

Vout+ Vout-

Cx

Cx

• The longer TL, The smaller capacitance

to cross-couple is needed.

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2011/10/11 9

Transmission line

• Low loss(0.8dB/mm)

• Dummy metals are

manually placed.

GND

dummy

signal(10mm)

gap(15mm) GND

M1&M2 shield

GND GND

0.0

0.5

1.0

1.5

2.0

2.5

0 10 20 30 40 50 60 70Frequency [GHz]

[dB

/mm

]

`

manual auto

30

35

40

45

50

55

60

65

70

0 10 20 30 40 50 60 70

Frequency [GHz]

Z0 [

oh

m]

manual auto

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2011/10/11 10

MIM Transmission Line

• De-coupling use

• Modeling accuracy

• Avoiding self-resonance of

parallel-plate capacitors

0123456789

10

0 10 20 30 40 50 60 70

Frequency [GHz]

Z0 [

Oh

m]

Measured

Model

GND

MIM TL

GND

GND

GND

TL

MIM capacitor

MIM transmission line

50W transmission line

[4] T. Suzuki, et al., ISSCC 2008

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2011/10/11

Schematic of PA

• 3-stage differential power amplifier.

• The capacitive cross-coupling neutralization is used.

• The guided micro-strip line is used for matching network.

• The de-coupling is implemented as MIM TL.

MIMTL MIMTL MIMTL

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2011/10/11

Die photo

• Core area: 1.0mmx0.6mm

INPUT OUTPUT

DC

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2011/10/11

Measurement result

• Power Gain: 23.2dB

• Psat: 14.6dBm

• P1dB: 10.0dBm

• Power Consumption: 135mW (Vdd=1.2V)

• Peak PAE: 16.3%

0

3

6

9

12

15

18

-5

0

5

10

15

20

25

PA

E[%

]

Ou

tpu

tP

ow

er

[dB

m]

Po

wer

Gain

[dB

]

Input Power [dBm]

Output Power

Power Gain

PAE0

5

10

15

20

25

30

40 45 50 55 60 65 70

Po

wer

Gain

[dB

]

Frequancy [GHz]

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2011/10/11

Performance comparison

Power

Gain [dB]

P1dB

[dBm]

Psat

[dBm]

Peak

PAE [%]

Power

[mW]

VDD [V]

ISSCC 2008[5] 5.5 9 12.3 8.8 - 1.0

ISSCC 2009[3] 16 2.5 11.5 11 43.5 1.0

ISSCC 2010[6] 20.6 18.2 19.9 14.2 - 1.2

ISSCC 2010[7] 19.2 14.1 17.7 11.1 480 1.0

ISSCC 2010[8] 14.3 11 16.6 4.9 732 1.2

ISSCC 2011[9] 20.3 15 18.6 15.1 - 1.0

This Work 23.2 10.0 14.6 16.3 135 1.2

[5] D. Chowdhury, ISSCC, 2008 [6] C. Y. Law, ISSCC, 2010

[7] J. Lai, ISSCC, 2010 [8] B. Martineau, ISSCC, 2010 [9] J.Chen, ISSCC, 2011

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2011/10/11

Conclusion

• A 60GHz power amplifier using the capacitive

cross-coupling neutralization with the low-loss

transmission line is presented.

• The 3-stage differential power amplifier in 65nm

CMOS achieves power gain of 23.2dB, output

power at 1-dB compression point of 10.0dBm,

saturated output power of 14.6dBm, peak PAE

of 16.3% and power consumption of 135mW.

Documents

A 60 GHz CMOS Power Amplifier Using Capacitive … 60 GHz CMOS Power Amplifier Using Capacitive Cross-Coupling ... Simulation result 0 5 10 15 20 25 30 35 40 ... manual auto 30 35