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A Faster Satisfiability Model and Algorithm for
Circuit Delay Computation鍾逸亭
• Outline
• Model introduction• Arrival time information– Example
• Modified arrival time• Comparasion with papers• Future work
• Model introduction (1/2)• Floating mode sensitization
– On-input can decide the final value of the gate.– On-input is the earliest controlling-value, or– On-input is the latest nc and side-inputs are nc.
• Viability mode sensitization – If a gate is stable no earlier than t (arrival t),≧– At least a fanin is stable no earlier than t-d, and– Either a fanin is stable no earlier than t-d or is nc.
• Two model have the same delay– Viability model has a simpler format
On-input of AND =Earliest 0, orLatest 1, other are 1
00
01
10
11
• Model introduction (2/2)• Viability model for circuit delay computation
– We want to check whether circuit delay D≧
– X is the TCF, X(p,D)=1 means arrival(p) D ≧– For a X, it can be compute recursively
3(2+k) clauses– In fact, we only need to build the positive X model:
1+k clauses
p
)(
,
)(
,, )(fFIg
dtg
fFIg
dtgtf ncg
POp
Dp,
Ex. Check D=2
g
a
a
a
ga
ga
b
g
gg
ga
ga
p
0,
1,
1,1,
1,1,
1,1,
2,
))()((
))((
)(
ab
)(
,
)(
,, )(fFIg
dtg
fFIg
dtgtf ncg
arrival t1 t2 t3 tmax
X( f, t)= 1 X(f,t2) X(f,t3) … 0
2
• Arrival time information Arrival = 4, 6X≦4 = 1 Arrival must 4≧X5 = X6 Arrival 5 means Arrival 6≧ ≧X>6 = 0 Arrival cannot > 6
24
• Example
A
B
1
1
1
1. Compute all arrival time
2
2
3
3,4
4,5
3,5,6
4,5,6,7
2. Construct TCF model for max delay=7
X7X6=0
X6X5
X5=0
X4=0
X4X3=1
X3=0
0
0
arrival t1 t2 t3 tmax
X( f, t)= 1 X(f,t2) X(f,t3) … 0
3. Apply SAT solver to make some XPO=1 #TCF = 4
• Example
A
B
1. Compute all arrival time2. Construct TCF model for max delay=7
)(
,,
)(
,,
)(
,
)(
,,
)()(
:
)(
fFIg
dtgtf
fFIg
dtgtf
fFIg
dtg
fFIg
dtgtf
ncg
Cnf
ncg
X7
X6X5X41
3. Apply SAT solver to make some XPO=1
=1
=1=1=1
0
1
0
11
1
1
0Conflict!
Reduce max delay
• Example1. Compute all arrival time2. Construct TCF model for max delay=6
A
B
1
1
1
2
2
3
3,4
4,5
3,5,6
4,5,6,7X6
X5
X5X4=1
X4=0
X4=0
X4X3=1
X3=0
0
0
arrival t1 t2 t3 tmax
X( f, t)= 1 X(f,t2) X(f,t3) … 0
3. Apply SAT solver to make some XPO=1 #TCF = 4
Two cases
• Example1. Compute all arrival time2. Construct TCF model for max delay=6
A
B
X6X5
X41
)(
,,
)(
,,
)(
,
)(
,,
)()(
:
)(
fFIg
dtgtf
fFIg
dtgtf
fFIg
dtg
fFIg
dtgtf
ncg
Cnf
ncg
3. Apply SAT solver to make some XPO=1
Case1:
=1
0
0
11
1
1
0Conflict!
=1
=1
• Example1. Compute all arrival time2. Construct TCF model for max delay=6
A
B
X6
X51
)(
,,
)(
,,
)(
,
)(
,,
)()(
:
)(
fFIg
dtgtf
fFIg
dtgtf
fFIg
dtg
fFIg
dtgtf
ncg
Cnf
ncg
3. Apply SAT solver to make some XPO=1
Case2:
=10
=1
1
1
1
1
0Conflict!
Reduce max delay
• Example1. Compute all arrival time2. Construct TCF model for max delay=5
A
B
1
1
1
2
2
3
3,4
4,5
3,5,6
4,5,6,7X5
X4=1
X4X3=1
X3=0
0
0
arrival t1 t2 t3 tmax
X( f, t)= 1 X(f,t2) X(f,t3) … 0
3. Apply SAT solver to make some XPO=1 #TCF = 2
• Example1. Compute all arrival time2. Construct TCF model for max delay=5
A
B
X51
X41
arrival t1 t2 t3 tmax
X( f, t)= 1 X(f,t2) X(f,t3) … 0
3. Apply SAT solver to make some XPO=1 Total # TCF = 10
=1
=1 or 0
0
01
SAT!
4. True delay = 5
True arrival time
• Modified arrival time
A
B
1
1
1
2 3
3, 4
4, 5
3, 5, 6
4, 5, 6, 70
0
1. There may be some false arrival time in the circuit. (Unit arrival time must be true, so we need not to check)
2. We can pick a cut of circuit and check the critical arrival time.3. Then we can propagate new arrival time information to PO.4. If X(PO, max delay) is UNSAT, repeat 2.
2
UNSATUNSAT
X5
X4=1
X4=00
0
01
SAT! Total # TCF is reduced form 10 to 3.
• Modified arrival time• Cut Strategy:
– Critical arrival time number <= cutLimit– Start from the level_num*ratio level– Offset
Circuit SAT time New SAT time
TCF New TCFFinal/total
cutLimit, offset, ratio
C7552 0.001 0 376 168/386 10, 1, 50
C6288 0.033995 0.033995 948 638/889 1,100,80
C18 0.247963 0.197971 7604 4203/8346 2,10,50
C19 0.525920 0.380944 54530 29028/44660 2,10,50
• Comparasion with papers
• Model – floating-mode sensitization
• # TCF vars• Run time
AND OR
[1]
[2]
Ours (Viability)
• Model-formulae
)( )( )(
,,, )()()(fFIg fFIh fFIh
dthdtgtf nchnchcg
)(
)(,0,0
)(
)(,1,1
fFIg
dtgtf
fFIg
dtgtf
)(
)(,0,0
)(
)(,1,1
fFIg
dtgtf
fFIg
dtgtf
)(
,
)(
,, )(fFIg
dtg
fFIg
dtgtf ncg
# Variables # Clauses
[1] K+5 7K+8
[2] 2 2(K+1)
Ours 1 K+1
• Model-cnfK-input gate
Circuit delay model # Clauses
[1] 1
[2] 2 * PO + 1
Ours 1
• Model-circuit delay
POf
tf ,
})1()0({ ,1,0
POf
tftf ff
tfarrivalPOf
tf
)(
,
• # VariablesVARS [1] [2] Ours
c1355 5176.9 1590.2 318.6
c1908 8846.8 2184.7 285.7
c2670 5534.5 1824.1 606.5
c3540 25317.9 5696.3 1890.4
c432 6040.1 1323.9 138.2
c499 8349.4 2152.1 88.2
c5315 13282.8 4413.6 1214.4
c6288 305594.9 63909.8 26109.2
c7552 23287.5 6499.3 1538
c880 3707.8 1114.6 145.9c1355c1908c2670c3540 c432 c499 c5315c6288c7552 c880
0
50000
100000
150000
200000
250000
300000
350000
[1][2]Ours
• Run time of SAT solverTime(s) [1] [2] Ours
c1355 0.05 0.02 0.002
c1908 0.14 0.04 0.001
c2670 0.05 0.02 0.003
c3540 0.27 0.05 0.006
c432 0.06 0.02 0
c499 0.1 0.03 0
c5315 0.17 0.05 0.006
c6288 7.16 1.3 0.226
c7552 0.35 0.06 0.008
c880 0.03 0.01 0c1355 c1908 c2670 c3540 c432 c499 c5315 c6288 c7552 c880
0
1
2
3
4
5
6
7
8
[1][2]Ours
• Future Work
• How to find a better cut or …• Find all true paths with delay >=
D.• Extend unit delay model to
continuous model.• Timing optimization needs what
information?
• Reference
[1] Satisfiability Models and Algorithms for Circuit Delay Computation. Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira and Karem A. Sakallah. Cadence European Laboratories
[2] Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. Yu-Min Kuo, Student Member, IEEE, Yue-Lung Chang, and Shih-Chieh Chang, Member, IEEE
