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A Successive Approximation ADC based on a new Segmented DAC
I
segmented current-mode DAC
successive approximation ADC bi-direction segmented
current-mode DAC DAC
INL 0.47 LSB DNL 0.154 LSB DAC 3V
8 2MS/s successive approximation ADC
TSMC 1P4M 0.35 m CMOS INL
0.82 LSB DNL 0.31 LSB ENOB 7 2.6mW
II
A Successive Approximation ADC based on a
new Segmented DAC
ABSTRACT
A successive approximation analog-to-digital converter (ADC) based on a new
segmented digital-to-analog converter (DAC) architecture is presented. A more
efficient method which is the bi-direction segmented current-mode approach is
proposed to implement the high-resolution and high speed DAC. This DAC has the
maximum integral nonlinearity (INL) error of 0.47 LSB, and the maximum differential
nonlinearity (DNL) error of 0.154 LSB. Based on this new DAC, a 3-V, 8-bit, 2-MS/s
ADC is realized. The whole circuit is implemented by the TSMC 1P4M 0.35 m
CMOS process. The experimental results show that the INL of ADC is less than 0.82
LSB. Meanwhile, the DNL is less than 0.31 LSB. The power consumption is only
2.6mW with the effective number of bits of 7.
III
IV
...........................................................................................................................I ABSTRACT..................................................................................................................... II
........................................................................................................................ III ........................................................................................................................ IV ........................................................................................................................VI .......................................................................................................................VII
Chapter 1 INTRODUCTION............................................................................................ 1 1.1 Motivation........................................................................................................... 1 1.2 Organization of the Dissertation ......................................................................... 2 1.3 SAR ADC versus other ADCs ............................................................................ 2
1.3.1 Pipelined Converter ................................................................................. 2 1.3.2 Flash Converter........................................................................................ 3 1.3.3 Sigma-Delta Converter ............................................................................ 4
1.4 Circuit Characteristic .......................................................................................... 4 Chapter 2 BASIC CONCEPTS......................................................................................... 5
2.1 Successive Approximation ADC Architecture.................................................... 5 2.2 Algorithm............................................................................................................ 6 2.3 SAR ADC Techniques ........................................................................................ 8
2.3.1 R-2R-Based Converter............................................................................. 8 2.3.2 Charge-Redistribution Converter............................................................. 9 2.3.3 Resistor-Capacitor Hybrid Converter .................................................... 10 2.3.4 Current-Mode Converter........................................................................ 10
Chapter 3 CIRCUIT DESIGN OF SAR ADC ................................................................ 12 3.1 Sample / Hold (S/H) Amplifier Architecture .................................................... 12
3.1.1 Clock Divider......................................................................................... 13 3.1.2 Simulation results of the S/H................................................................. 14
3.2 Comparator ....................................................................................................... 17 3.2.1 Comparator Circuit ................................................................................ 17 3.2.2 Clock of the Comparator........................................................................ 20
3.3 Segmented Current-Mode DAC ....................................................................... 21 3.3.1 3-way switch controller ......................................................................... 27 3.3.2 I-V Converter ......................................................................................... 30
3.3.2.1 Operational Amplifier ................................................................. 30 3.3.3 Simulation results of the DAC............................................................... 33
3.4 SAR Controller ................................................................................................. 34
V
Chapter 4 EXPERIMENTAL RESULTS........................................................................ 38 4.1 ADC Test........................................................................................................... 38 4.2 Layout Arrangement ......................................................................................... 40
Chapter 5 CONCLUSIONS & FUTURE WORKS........................................................ 43 5.1 Conclusions....................................................................................................... 43 5.2 Future Works..................................................................................................... 43
REFERENCES ............................................................................................................... 45 ........................................................................................................................ 47
VI
1 Size of the comparator ........................................................................................ 18 2 3 8 binary-to-thermometer decoder ............................................................... 28 3 P-channel (B7=0).................................................... 28 4 N-channel (B7=1)................................................... 29 5 OPA ............................................................................................ 32 6 8 SAR ................................................................ 36 7 Effective number of bits...................................................................................... 40 8 Experimental results of the proposed ADC ........................................................ 42 9 successive approximation ADC ................................................ 43
VII
1. 1 General Pipelined ADC architecture.................................................................... 3 1. 2 N-bit Flash ADC ..................................................................................... 3 2. 1 Successive approximation ADC ......................................................... 5 2. 2 Various values of the DAC output voltage .......................................................... 6 2. 3 N-bit successive approximation approach .......................................... 7 2. 4 4-bit successive approximation ADC conversion................................................ 8 2. 5 DAC.................................................................................................... 9 2. 6 Charge-redistribution converter ........................................................................... 9 2. 7 Resistor-Capacitor Hybrid converter ................................................................. 10 2. 8 Binary-weighted current-mode converter .......................................................... 11 3. 1 Double sampling S/H architecture. .................................................................... 12 3. 2 Execution period of the double sampling. ......................................................... 13 3. 3 Transmission Gate circuit .................................................................................. 13 3. 4 clock divider circuit ........................................................................................... 14 3. 5 clock .................................................................................................. 14 3. 6 Simulation result of the S/H circuit. .................................................................. 15 3. 7 Output power spectrum density of the S/H........................................................ 16 3. 8 Comparator ....................................................................................... 17 3. 9 Circuit design of the comparator........................................................................ 18 3. 10 Auto-zeroing circuit. ........................................................................................ 19 3. 11 Clock circuit of the comparator........................................................................ 20 3. 12 Simple RC model............................................................................................. 20 3. 13 Clock simulation of the comparator................................................................. 21 3. 14 Basic N-bit segmented D/A converter.............................................................. 22 3. 15 Non-monotonic behavior of the DAC. ............................................................ 23 3. 16 Monotonic N-bit segmented D/A converter..................................................... 23 3. 17 Monotonic behavior of the DAC ..................................................................... 23 3. 18 Segmented N-bit inherently monotonic current DAC ........................ 24 3. 19 N-bit bi-direction segmented DAC ..................................................... 25 3. 20 DAC P .................................................................... 26 3. 21 MOS ................................................................................................ 27 3. 22 2-way switches circuit ..................................................................................... 29 3. 23 Two-stage OPA ............................................................................... 31 3. 24 Two-stage OPA ............................................................................... 31 3. 25 Simulation result of the DAC .......................................................................... 33
VIII
3. 26 DAC INL .................................................................................. 34 3. 27 DAC DNL .................................................................................. 34 3. 28 N-bit SAR ..................................................................... 35 3. 29 N-bit SAR controller based on the non-redundant structure ........................... 35 3. 30 Nth ........................................................................................ 36 3. 31 D-latch ............................................................................................... 37 4. 1 ADC INL .................................................................................. 38 4. 2 ADC DNL ................................................................................ 39 4. 3 Output power spectrum density of the ADC...................................................... 39 4. 4 ENOB versus input frequency ........................................................................... 40 4. 5 Layout arrangement ........................................................................................... 41 4. 6 I/O PAD arrangement ........................................................................................ 41 4. 7 Layout view ....................................................................................................... 42
1
Chapter 1 INTRODUCTION
1.1 Motivation
Analog-to-Digital Converter ADC
Digital-to-Analog Converter DAC
(Bluetooth) ADC DAC
ADC
ADC successive approximation register (SAR) ADC
5MS/s (8~16 bits)
ADC successive approximation ADC
ADC DAC
successive approximation ADC
successive approximation ADC DAC
current-steering with resistance ladder [1] charge-redistribution with
capacitance array [2] successive
approximation ADC
2
current-mode
successive approximation ADC DAC segmented current-mode [3]
1.2 Organization of the Dissertation
ADC
successive approximation ADC
successive approximation ADC
1.3 SAR ADC versus other ADCs
ADC SAR ADC ADC SAR
ADC
1.3.1 Pipelined Converter
Pipelined ADC 1. 1 parallel (stage)
(conversion rate)
(Latency) Latency
ADC ADC
Pipelined ADC clock Latency successive
approximation ADC clock Latency Pipelined ADC
successive approximation ADC stage
3
OPA S/H
1. 1 General Pipelined ADC architecture
1.3.2 Flash Converter
Flash ADC 1. 2
wideband low-gain preamp(s) latch Flash ADC ADC
2n
Flash 10 12 ADC
successive approximation ADC
Flash
ADC
1. 2 N-bit Flash ADC
4
1.3.3 Sigma-Delta Converter
Sigma-Delta ( oversampling)
Sigma-Delta modulators ( )
(multi-bit) Sigma-Delta modulators
( 16 )
digital decimation filter
1.4 Circuit Characteristic
successive approximation ADC
1.
2.
3.
5
Chapter 2 BASIC CONCEPTS
2.1 Successive Approximation ADC Architecture
Successive approximation ADC 2. 1
(S/H) (Comparator) Successive
Approximation Register (SAR) N N
Successive approximation ADC N
2. 1 Successive approximation ADC
N successive approximation ADC
(Vin) Sample/Hold (S/H)
comparator N DAC SAR (binary
search) DAC comparator
(MSB) (LSB) N
register (D-latch)
successive approximation ADC
6
comparator DAC successive approximation ADC
comparator Vin VDAC
DAC ADC
1/2 LSB comparator DAC
2.2 Algorithm
Successive approximation ADC (
) N successive approximation ADC
DAC VFS (VFS DAC full-scale voltage)
Vin VD/A (DAC )
1 0 DAC
VFS /2 ( )
VD/A Vin
(Vin) N N (N cycles) (LSB)
4 successive approximation ADC DAC
2. 2
2. 2 Various values of the DAC output voltage
7
2. 3
i N
2. 3 N-bit successive approximation approach
4 successive approximation ADC 2.
4 Y DAC X
DAC 10002 Vin > VDAC B3
1 DAC 11002 Vin < VDAC
B2 0 DAC 10102
Vin > VDAC B1 1 DAC 10112
8
Vin < VDAC B0 0 10102
N successive approximation ADC N 4
successive approximation ADC
2. 4 4-bit successive approximation ADC conversion
2.3 SAR ADC Techniques
successive approximation ADC DAC
2.3.1 R-2R-Based Converter
DAC [1][4] 2. 5
binary-weighted ( )
DAC
MSBs thermometer
(Glitch)
(
) (Layout area)
9
2. 5 DAC
2.3.2 Charge-Redistribution Converter
[2] 2. 6 (
binary-weighted) DAC
SAR ADC S/H
[5]
[6]
2. 6 Charge-redistribution converter
10
2.3.3 Resistor-Capacitor Hybrid Converter
[7][8] 2. 7
binary-weighted
DAC DAC
binary-weighted
2. 7 Resistor-Capacitor Hybrid converter
2.3.4 Current-Mode Converter
[9] 2. 8
( binary-weighted)
11
DAC
segmented current-mode [3]
segmented current-mode
2. 8 Binary-weighted current-mode converter
12
Chapter 3 CIRCUIT DESIGN OF SAR ADC
3-V 8
16MHz data rate 2 MS/s 1V~2V successive
approximation ADC
successive approximation ADC
3.1 Sample / Hold (S/H) Amplifier Architecture
Clock
Double sampling
operational amplifiers (OPAs) Buffer 3. 1
S/H 3. 2
Clock (Sample) (Hold)
Clock (Hold)
(Sample) Double sampling
3. 1 Double sampling S/H architecture.
13
3. 2 Execution period of the double sampling.
Sample-and-Hold circuit Charge
Injection Clock Feedthrough Transmission Gate ( 3. 3 )
MOS Charge Injection PMOS NMOS
CLK CLK PMOS NMOS channel channel
q1 q2 MOS gate-source overlap
capacitance Charge Injection
OPAs Offset Error Sample-and-Hold circuit OPAs
Offset
3. 3 Transmission Gate circuit
3.1.1 Clock Divider
S/H D
D 2 16MHz 16
14
4 D 1MHz 3. 4
3. 5 D
3. 4 clock divider circuit
3. 5 clock
3.1.2 Simulation results of the S/H
3. 6 S/H 1-VPP
62.5KHz S/H 1MHz S/H
tracking
15
3. 6 Simulation result of the S/H circuit.
8
S/H 1MHz 1-VPP 62.5KHz
32 1024 (FFT)
3. 7
500fF Signal-to-(Noise + distortion)
Ratio(SNDR) 59.35dB S/H
8-bit
16
−120
−100
−80
−60
−40
−20
3. 7 Output power spectrum density of the S/H.
49.76dB (8-bit )
(3.1)[10]
2)(rmsnVTKC (3.1)
Vn(rms) 1/4 VLSB(=1mV) K Boltzmann�s constant
( 1.38 10-23JK-1 ) T 300¢K 4.14fF
500fF S/H
17
3.2 Comparator
successive approximation ADC
16MHz
1/2 LSB Latch Latch
Latch
( 0V~3V) -1mV +1mV 63.5dB
Latch Latch
3. 8 Comparator
3. 8 Differential
preamplifier Latch
preamplifier
3.2.1 Comparator Circuit
3. 9 ph2 high M1 M2 M3 M4 M7
Differential Preamplifier ph2 low M3 M4 M5 M6
M7 Bistable Multivibrator [11]
18
3. 9 Circuit design of the comparator.
ph1 ph2 ph3 high preamplifier
C1 C2 VcVIN DIN VV ph1 low C1 C2
node C D ph3 low C1 C2 Vin-
Vin+ node A B ph2
low Multivibrator latch BA VV
highVVV OUTININ 0
1 Size of the comparator
(W/L)M1 (1.1/1) M2 (1.1/1) M3 (7.5/1)*2 M4 (7.5/1)*2 M5 0.9/0.35 M6 0.9/0.35 M7 (7.6/1)*2 S1 0.9/0.35 S2 0.9/0.35
19
50 A
(3.2) (3.3)[12] Channel-Length modulation
Latch
1
multiple fingers
2)(
21
THGSoxnD VVL
WCI (3.2)
2)(
21
THGSoxpD VVL
WCI (3.3)
208 W 2mV ( 1/2
LSB) (Offset)
3. 10 node A B
Auto-zeroing
3. 10 Auto-zeroing circuit.
20
3.2.2 Clock of the Comparator
clock delay
3. 11
3. 11 Clock circuit of the comparator.
RC
3. 12 Rp Rn PMOS NMOS
CL Cgs Cgd (3.4) (3.5)
L RC
L i td (3.6)
3. 12 Simple RC model.
21
)(
1
THGSoxp
p
VVL
WCR (3.4)
)(
1
THGSoxn
n
VVLWC
R (3.5)
i
iid CRt (3.6)
3. 13 CLK 16MHz ph1 ph3 3.2ns
ph2 ph3 12.5ns
3. 13 Clock simulation of the comparator.
3.3 Segmented Current-Mode DAC
successive approximation ADC DAC
ADC DAC successive
approximation ADC DAC segmented
CLK
ph1
ph2
ph3
22
current-mode [3][13][14] DAC
Current Switching Matrix [11] 3. 14 N-bit
segmented D/A converter m coarse current source (Iu)
(coarse current source) (Im) current divider (fine
currents) Iout
3. 14 Basic N-bit segmented D/A converter.
DAC ( MSBs )
thermometer (monotonicity) thermometer
( MSBs ) current
divider ( LSBs )
VLSB DAC
(monotonic) 3.
15 DAC
( VLSB ) (Non-monotonic)
(three-way switch)
3. 16
23
3. 15 Non-monotonic behavior of the DAC.
3. 16 Monotonic N-bit segmented D/A converter
3. 17 Monotonic behavior of the DAC
24
I1 ~ Im-1
Im fine current divider
3. 17
DAC
Im
(segment current) Iseg
3. 18 N C MSBs
F LSBs
3. 18 Segmented N-bit inherently monotonic current DAC
MSBs Binary-to-Thermometer thermometer
LSBs
8 MSBs 4 LSBs 4
24 current divider 24
Iout (=Iout(coarse)+Iout(fine)) (I-V converter)
Vref
25
Vref Vref OPA
VDS
3. 19
P-channel
N-channel
Rout
3. 19 N-bit bi-direction segmented DAC
8 3V 1V~2V
8 1 (sign bit) 3 (coarse) 4 (fine)
3 ( MSBs)
3 8 binary-to-thermometer 4
( LSBs) (2-way)
26
P-channel ( Iout(coarse)+
Iout(fine)+) 1~Vref N-channel ( Iout(coarse)
-
Iout(fine)-) Vref ~2V Vref VDD/2(
) 8 ( )
P-channel N-channel 3 MSBs
thermometer m-1 Iout(coarse) (
Iout(coarse) MSBs
) m binary-weighted current divider
(Iseg) binary-weighted current divider binary-weighted LSBs
binary-weighted
Iout(fine) DAC Iout Iout(coarse) Iout(fine)
(Idump) Vref
3. 20
3. 20 DAC P
27
Ma1~Ma8 P-channel Mb1~Mb24
Mc1~Mc16
Md1~Md5 current divider DAC N
P-channel N-channel
P-channel
N-channel Integral nonlinearity (INL)
error (current mirror) 3. 21
MOS VDS VGS DAC
3. 21 MOS
3.3.1 3-way switch controller
segmented DAC
MSBs binary-to-thermometer thermometer
2N-1 2N
N 2N
N 3 2
28
2 3 8 binary-to-thermometer decoder
Binary Code Thermometer Code
B3 B2 B1 T7 T6 T5 T4 T3 T2 T1
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 1
0 1 1 0 0 0 0 1 1 1
1 0 0 0 0 0 1 1 1 1
1 0 1 0 0 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
thermometer
1. Differential nonlinearity (DNL) error
2. (monotonicity)
3. Glitch
4 16
binary -to- thermometer
3 4 P-channel
PMOS N-channel
NMOS
3 P-channel (B7=0)
B6 B5 B4 Sw8 Sw7 � Sw2 Sw1
0 0 0 1 1 0 1 0 1 � 1 0 1 1 0 1
0 0 1 0 1 1 1 1 0 � 1 0 1 1 0 1
0 1 0 0 1 1 0 1 1 � 1 0 1 1 0 1
0 1 1 0 1 1 0 1 1 � 1 0 1 1 0 1
1 0 0 0 1 1 0 1 1 � 1 0 1 1 0 1
1 0 1 0 1 1 0 1 1 � 1 0 1 1 0 1
1 1 0 0 1 1 0 1 1 � 1 1 0 1 0 1
1 1 1 0 1 1 0 1 1 � 0 1 1 1 1 0
29
4 N-channel (B7=1)
B6 B5 B4 Sw16 Sw15 � Sw10 Sw9
0 0 0 1 0 0 1 0 0 � 1 0 0 0 0 1
0 0 1 1 0 0 1 0 0 � 0 0 1 0 1 0
0 1 0 1 0 0 1 0 0 � 0 1 0 0 1 0
0 1 1 1 0 0 1 0 0 � 0 1 0 0 1 0
1 0 0 1 0 0 1 0 0 � 0 1 0 0 1 0
1 0 1 1 0 0 1 0 0 � 0 1 0 0 1 0
1 1 0 1 0 0 0 0 1 � 0 1 0 0 1 0
1 1 1 0 0 1 0 1 0 � 0 1 0 0 1 0
Idump Iout Iseg
2N*3(N ) 48
LSBs 3. 22 Iseg
Binary-weighted current divider
VDS Binary-weighted current
divider
3. 22 2-way switches circuit
30
3.3.2 I-V Converter
DAC
OPA
OPA ( ) Vref 1.5V
(3.7)
IINrangeOutput
R unitout2
_ (3.7)
Output_range Iunit
I N DAC Iunit
I HSPICE
( N, Output_range, Iunit, I ) = ( 8, 1V, 1 A, 23nA ) Rout
3.83k
3.3.2.1 Operational Amplifier
OPA
OPA
OPA two -
stage
3. 23
31
3. 23 Two-stage OPA
OPA DAC S/H DAC
(Bandwidth) slew
rate (DC gain) Phase Margin ( )
(3.8)
)1()( tstepout eVtV (3.8)
Vstep Vout(t)
Vstep 1V 0.999V( 1/4 LSB) DAC
(16MHz) 7 OPA
112 MHz 60dB Phase Margin 65 slew rate
3. 24
3. 24 Two-stage OPA
32
PMOS Slew Rate Unity-gain frequency
Flicker
(3.9)[10]
5
6
4
7
)/()/(2
)/()/(
LWLW
LWLW
(3.9)
OPA 200MHz DC gain 65.2dB Phase Margin
61.3 2mV ADC OPA
OPA DAC
DAC OPA S/H Buffer
705 W
5
5 OPA
M1 8.1/1
M2 8.1/1
M3 4.2/1
M4 4.2/1
M5 (10/1)*2
M6 (10/1)*6
M7 (4.2/1)*6
M8 0.9/1
33
3.3.3 Simulation results of the DAC
3. 25 Simulation result of the DAC
3. 25 DAC 8 000000002 ~ 111111112
1V~2V 1 A
16 A ADC
INL 3. 26 0.47 LSB
DNL 3. 27 0.154 LSB
34
3. 26 DAC INL
3. 27 DAC DNL
3.4 SAR Controller
N SAR
[15] 3. 28 (memory register)
(shift register) non
- redundant successive approximation register [16] 3. 29
N 2N Flip-Flop(FF) N FF FF
finite state machine (FSM)
35
3. 28 N-bit SAR
3. 29 N-bit SAR controller based on the non-redundant structure
SAR start low
MSB 1 0 DAC 1.5V(1/2 full scale)
low MSB 0
high MSB
1 high
comparator high low 8 8 6
36
8 LSB
1 MSB
6 8 SAR
Conversion step D/A converter input Comparator output0 1 0 0 0 0 0 0 0 B7 1 B7 1 0 0 0 0 0 0 B6 2 B7 B6 1 0 0 0 0 0 B5 3 B7 B6 B5 1 0 0 0 0 B4 4 B7 B6 B5 B4 1 0 0 0 B3 5 B7 B6 B5 B4 B3 1 0 0 B2 6 B7 B6 B5 B4 B3 B2 1 0 B1 7 B7 B6 B5 B4 B3 B2 B1 1 B0
Result B7 B6 B5 B4 B3 B2 B1 B0 -
8 non-redundant structure SAR 8 (CU)
3. 30 D-FF
shift register load data hold data
(3.10)
BitNHoldLoadBitNHoldShiftBitNHoldBitN next)( (3.10)
3. 30 Nth
37
1. ( )
2.
3. ( OR � 1 � )
3. 29 D-latch
D-latch D-latch 3. 31
6 clk high Vin Vout clk
low Vout
3. 31 D-latch
38
Chapter 4 EXPERIMENTAL RESULTS
TSMC 1P4M 0.35 m CMOS
3V
2.6mW 2MS/s
4.1 ADC Test
Static test
ADC ADC 1V~2V ramp
1. Integral Nonlinearity Error (INL)
best-fit line INL 4. 1 INL
0.82 LSB
4. 1 ADC INL
2. Differential Nonlinearity Error (DNL)
DNL 0.5 LSB ADC monotonic
39
DNL 0.31 LSB 4. 2
4. 2 ADC DNL
Dynamic test
ADC ADC 1Vpp
62.5kHz 32 32 1024
MATLAB 1024 Fast Fourier transform (FFT) 4. 3
signal-to-(noise and distortion) ratio (SNDR) 43.4dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
4. 3 Output power spectrum density of the ADC
40
Effective number of bits (ENOB) 7
ENOB 4. 4 post layout simulation
7 Effective number of bits
SNDR ENOB
31.25kHz 44.01dB 7
62.5kHz 43.4dB 6.9
125kHz 42.82dB 6.8
250kHz 42.9dB 6.8
4. 4 ENOB versus input frequency
4.2 Layout Arrangement
poly Guard ring
41
(Poly-Metal1-Metal2)
Guard ring 4. 5
4. 5 Layout arrangement
I/O PAD 4. 6
4. 6 I/O PAD arrangement
Layout view ( I/O PAD) 4. 7
42
350 *430 I/O PAD
4. 7 Layout view
8-bit successive approximation ADC 8
8 Experimental results of the proposed ADC
Supply voltage 3V Total power dissipation < 2.6mW
Technology 0.35 m CMOSSampling rate 2MS/s
Resolution 8 bits Input swing 1V
INL < 0.82 LSB DNL < 0.31 LSB
SNDR@ fin = 62.5KHz 43.4 dB ENOB@ fin = 62.5KHz 6.9 bits
Active area < 0.15mm2
43
Chapter 5
CONCLUSIONS & FUTURE WORKS
5.1 Conclusions
segmented current-mode DAC
segmented current-mode DAC 3V 8-bit 2MS/s successive
approximation ADC 2.6mW offset 2mV
ENOB 7-bit ADC
ADC successive approximation ADC 9
9 successive approximation ADC
Process Resolution Sampling rate Supply voltage Power consumption Active area
1.2um[1] 8-bit 50kS/s 1V 0.34mW 3.24mm2
3um [8] 8-bit 1.3MS/s 5V 70mW 3750mil2
3um [9] 8-bit 5MS/s N/A 50mW 0.903mm2
*0.35um 8-bit 2MS/s 3V 2.6mW 0.15mm2
* ADC
5.2 Future Works
1. Low voltage design ( VVDD 1 )
44
2.
3. BIST (Built-In Self-Test)
4. Programmable resolution
45
REFERENCES
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2002 VLSI Design/CAD symposium accepted, �A Successive Approximation ADC
based on a new segmented DAC,� June, 2002.
