A VHDL nyelv alapjai n VHDL nyelvi elvonatkoztatások n Tervezési hierarchiák – szerkezeti leírás

A VHDL nyelv alapjai

AA VHDL VHDL nyelv alapjainyelv alapjai

VHDL VHDL nyelvi elvonatkoztatásoknyelvi elvonatkoztatások Tervezési hierarchiákTervezési hierarchiák – – szerkezeti leírásszerkezeti leírás


VHDL VHDL nyelvi elemeknyelvi elemek

VHDL is composed of language VHDL is composed of language building blocks building blocks that consist that consist of more than of more than 75 75 reserved words reserved words and about 200 and about 200 descriptive descriptive

wordswords or or wordword combinationscombinations


FoglaltFoglalt VHDL k VHDL kulcsszavakulcsszavak

VARIABLE

WAITWHENWHILEWITH

XNORXOR

RETURN

SELECTSEVERITYSIGNALSHAREDSLASLLSRASRLSUBTYPE

THENTOTRANSPORTTYPE

UNAFFECTEDUNITSUNTILUSE

OFONOPENOROTHERSOUT

PACKAGEPORTPOSTPONEDPROCEDUREPROCESSPURE

RANGERECORDREGISTERREMREPORTROLROR

ININERTIALINOUTIS

LABELLIBRARYLINKAGELITERALLOOP

MAPMOD NANDNEWNEXTNORNOTNULL

DISCONNECTDOWNTO

ELSEELSIFENDENTITYEXIT

FILEFORFUNCTION

GENERATEGENERICGROUPGUARDED

IFIMPURE

ABSACCESSAFTERALIASALLANDARCHITECTUREARRAYASSERTATTRIBUTE

BEGINBLOCKBODYBUFFERBUS

CASECOMPONENTCONFIGURATION CONSTANT


Tervleírási módszerekTervleírási módszerek

Szerkezeti leírási módszerSzerkezeti leírási módszer Viselkedési leírási módszerViselkedési leírási módszer Adatáramlási leírási módszerAdatáramlási leírási módszer

These two are similar in that both use a process to describe These two are similar in that both use a process to describe

the functionality of a circuitthe functionality of a circuit

Kapcsolási rajz


VHDL VHDL nyelvi elvonatkoztatásoknyelvi elvonatkoztatások

VHDL is rich in language abstractions, in addition to which the VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, language can be used to describe different abstraction levels, from functions right down to a gate descriptionfrom functions right down to a gate description

Abstraction levels are a means of concealing detailsAbstraction levels are a means of concealing details


Elvonatkoztatási szintekElvonatkoztatási szintek Functional (system) levelFunctional (system) level + architecture => + architecture => Behavioral levelBehavioral level + resource handler => + resource handler => RTL (dataflow) levelRTL (dataflow) level + construction data => + construction data => Structural levelStructural level + technology data => + technology data => Logic (gate) level Logic (gate) level + electrical specification+ electrical specification => => Electrical levelElectrical level + layout requirements => + layout requirements => Layout levelLayout level

A fő témánk


Szerkezeti leírási módszerSzerkezeti leírási módszer:: expresses the design as an arrangement expresses the design as an arrangement of interconnected componentsof interconnected components– It is basically schematicIt is basically schematic

Viselkedési leírási módszerViselkedési leírási módszer:: describes the functional behavior of a describes the functional behavior of a hardware design in terms of circuits and signal responses to hardware design in terms of circuits and signal responses to various stimulivarious stimuli– The hardware behavior is described algorithmicallyThe hardware behavior is described algorithmically

Adatáramlási leírási módszerAdatáramlási leírási módszer:: is similar to a register-transfer is similar to a register-transfer languagelanguage– This method describes the function of a design by defining the flow This method describes the function of a design by defining the flow

of information from one input or register to another register or output of information from one input or register to another register or output

A leírási módszerek meghatározásaiA leírási módszerek meghatározásai


FeladatköriFeladatköri ( (rendszer-rendszer-) ) szintszint

Algorithms can be describe at this levelAlgorithms can be describe at this level E.g. a controller algorithm can be described and simulated on E.g. a controller algorithm can be described and simulated on

the computerthe computer An algorithm does not need to contain any time informationAn algorithm does not need to contain any time information Specifications written in VHDL will be able to be simulatedSpecifications written in VHDL will be able to be simulated


Viselkedési szintViselkedési szint

Behavior and time are described at this levelBehavior and time are described at this level No architecture is required hereNo architecture is required here The advantage of models at this level is that models for The advantage of models at this level is that models for

simulation can be built simulation can be built quicklyquickly A behavioral model can be described as functional modules and A behavioral model can be described as functional modules and

an interface interface between theman interface interface between them The modules contain one or more functions and time relationsThe modules contain one or more functions and time relations In certain cases the architecture can be definedIn certain cases the architecture can be defined


AA Behavioral DescriptionBehavioral Description uses a small number of processes uses a small number of processes where each process performs a number of sequential signal where each process performs a number of sequential signal assignments to multiple signalsassignments to multiple signals

In contrast, a In contrast, a Data-Flow DescriptionData-Flow Description uses a large number of uses a large number of concurrent signal assignment statementsconcurrent signal assignment statements

A concurrent statement executes asynchronously with respect A concurrent statement executes asynchronously with respect to other concurrent statementsto other concurrent statements

Concurrent statements used in Concurrent statements used in Data-Flow DescriptionData-Flow Description include:include:- block statement (used to group one or more concurrent - block statement (used to group one or more concurrent statements) statements)- concurrent procedure call- concurrent procedure call- concurrent assertion statement- concurrent assertion statement- concurrent signal assignment statement - concurrent signal assignment statement

Leírási módszerek összehasonlításaLeírási módszerek összehasonlítása


RTL = RegisRTL = Regiszzter ter átviteli szintátviteli szint

It consists of a language which describes behavior inIt consists of a language which describes behavior in– asynchronous and synchronous state machinesasynchronous and synchronous state machines

– data pathsdata paths

– operators (+,*,<,>,...)operators (+,*,<,>,...)

– registersregisters


Elektromos szintElektromos szint

Other name is: transistor levelOther name is: transistor level There are models ofThere are models of

– transistorstransistors

– capacitancescapacitances

– resistancesresistances This is not supported in VHDLThis is not supported in VHDL


Layout Layout szintszint

At layout level models are made of the physical processAt layout level models are made of the physical process This is not supported in VHDLThis is not supported in VHDL


SSzintéziszintézis = = NövekvőNövekvő összetettségösszetettség

Synthesis is done between each levelSynthesis is done between each level The volume of information increases between the various The volume of information increases between the various

abstraction levelsabstraction levels– E.g. technology information is required to synthesize from RT to E.g. technology information is required to synthesize from RT to

gate levelgate level

– Each transition (synthesis) generates more informationEach transition (synthesis) generates more information In order to implement a function in an ASIC, are required the In order to implement a function in an ASIC, are required the

followings:followings:– technology informationtechnology information

– wiring informationwiring information

– gate informationgate information

– set-up timesset-up times


Miért használnak különböző Miért használnak különböző elvonatkoztatási szinteket?elvonatkoztatási szinteket?

It is usually the requirements that determine the abstraction It is usually the requirements that determine the abstraction level at which the information is to be describedlevel at which the information is to be described

If a short development time is required, a high abstraction level If a short development time is required, a high abstraction level should be chosen as the description languageshould be chosen as the description language

In practice RT level (and parts of behavioral) can be In practice RT level (and parts of behavioral) can be synthesized automatically to gate levelsynthesized automatically to gate level


Különböző alkalmazásokKülönböző alkalmazások

ASICASIC = Application Specific Integrated Circuit = Application Specific Integrated Circuit– Usually includes FPGA, gate array, standard cell and full custom Usually includes FPGA, gate array, standard cell and full custom

designs.designs. PCBPCB = Printed Circuit Board design = Printed Circuit Board design

– On a circuit board there are usually several ASICs together with a On a circuit board there are usually several ASICs together with a microprocessor and its infrastructuremicroprocessor and its infrastructure

SystemSystem = a number of PCBs = a number of PCBs


ModelModell kiértékelésl kiértékelés The code for VHDL component can be verified The code for VHDL component can be verified

functionally in a simulatorfunctionally in a simulator The simulator simulates (“executes”) the VHDL code The simulator simulates (“executes”) the VHDL code

with input signals and produces a signal diagram and with input signals and produces a signal diagram and error messages on the basis of the componentserror messages on the basis of the components

The input signals are defined either in VHDL or in the The input signals are defined either in VHDL or in the simulator’s languagesimulator’s language

When the VHDL code is simulated, functional When the VHDL code is simulated, functional verification takes placeverification takes place

At a later stage, time verification of the design is also At a later stage, time verification of the design is also possiblepossible


SSzimulációzimuláció

Simulating models is an effective way of Simulating models is an effective way of verifying the designverifying the design

The model in the computer is only a time-discrete The model in the computer is only a time-discrete model, however, while reality is continuousmodel, however, while reality is continuous

The computer model is more or less like realityThe computer model is more or less like reality It is least like reality at a high abstraction level It is least like reality at a high abstraction level

(behavioral) and most like it at the lowest level (behavioral) and most like it at the lowest level (layout)(layout)


Egyéb elektronikai leíró nyelvekEgyéb elektronikai leíró nyelvek

There are several languages which are used to describe There are several languages which are used to describe electronic designselectronic designs

One popular language is called VERILOGOne popular language is called VERILOG It is used from RT level downIt is used from RT level down In some other languages there are no hierarchies, which causes In some other languages there are no hierarchies, which causes

major problems when working on complex assignmentsmajor problems when working on complex assignments There languages are developed by universities and research There languages are developed by universities and research

centerscenters


Other HDL languagesOther HDL languages There are several other language extensions built to either aid in RTL construction There are several other language extensions built to either aid in RTL construction

or assist in modeling:or assist in modeling:

– ParaCore - ParaCore - http://www.dilloneng.com/paracore.shtmlhttp://www.dilloneng.com/paracore.shtml

– RubyHDL - RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtmlhttp://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml

– MyHDL - MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtmlhttp://jandecaluwe.com/Tools/MyHDL/Overview.shtml

– JHDL - JHDL - http://www.jhdl.org/http://www.jhdl.org/

– Lava - Lava - http://www.xilinx.com/labs/lava/http://www.xilinx.com/labs/lava/

– HDLmaker - HDLmaker - http://www.polybus.com/hdlmaker/users_guide/http://www.polybus.com/hdlmaker/users_guide/

– SystemC SystemC

– AHDLAHDL – – http://www.altera.comhttp://www.altera.com» It It is goodis good for Altera-made chips only, which limits its usefulnessfor Altera-made chips only, which limits its usefulness

» But iBut it is easy to pick up andt is easy to pick up and use successfullyuse successfully The main purpose of a language -- programming, hdl, or otherwise -- is to ease the The main purpose of a language -- programming, hdl, or otherwise -- is to ease the

expression of designexpression of design


A SystemCA SystemC

C++ könyvtár rendszerszintű modellezésreC++ könyvtár rendszerszintű modellezésre Különböző elvonatkoztatási szinteket támogatKülönböző elvonatkoztatási szinteket támogat

– Feladatköri leírástól RTL szintűigFeladatköri leírástól RTL szintűig Használható gyors, hatékony tervekhezHasználható gyors, hatékony tervekhez IgazoláshozIgazoláshoz ( (verificationverification))


Miért nem csak C++?Miért nem csak C++?

C++: sorrendi programozás, nem alkalmas párhuzamos események C++: sorrendi programozás, nem alkalmas párhuzamos események modellezéséremodellezésére

A hardver modellben kell késleltetés, időA hardver modellben kell késleltetés, idő A hardver modellek közlési csatornái (port, signal) különböznek a szoftver A hardver modellek közlési csatornái (port, signal) különböznek a szoftver

modellekben használtaktólmodellekben használtaktól C++ adattípusai túl távol állnak a hardver megvalósításoktólC++ adattípusai túl távol állnak a hardver megvalósításoktól

C++ önmagában nem elég leírni egy bonyolult rendszertC++ önmagában nem elég leírni egy bonyolult rendszert


SystemC adattípusokSystemC adattípusok

Adattípusokat határoz meg a hardver modellezéshezAdattípusokat határoz meg a hardver modellezéshez– bit (‘0’, ‘1’)bit (‘0’, ‘1’)

– bitvector (‘0101’)bitvector (‘0101’)

– logic (‘0’, ‘1’, ‘Z’, ‘X’)logic (‘0’, ‘1’, ‘Z’, ‘X’)

– logicvector (’01XZ’)logicvector (’01XZ’) Használhatók az alap C++ adattípusok isHasználhatók az alap C++ adattípusok is

– fixedfixed

– floatfloat

– signed, unsigned, stb.signed, unsigned, stb.


VerilogVerilog Verifying Logic Phil Moorby from Gateway Design Automation in 1984 to 1987

– Absorbed by Cadence» Cadence's ownership of Verilog => others support VHDL

Verilog-XL simulator from GDA in 1986 Synopsis Synthesis Tool in 1988 In 1990 became open language

– OVI: Open Verilog International IEEE Standard in 1995

– IEEE Std-1364-1995 Last revision in 2001

– IEEE Std-1364-2001 Ongoing work for adding

– Mixed-signal constructs: Verilog-AMS– System-level constructs: SystemVerilog


VHDL vs. VerilogVHDL vs. VerilogVHDLVHDL VerilogVerilog

All abstraction levelsAll abstraction levels All abstraction levelsAll abstraction levels

Complex grammarComplex grammar Easy languageEasy language

Describe a system (everything)Describe a system (everything) Describe a digital systemDescribe a digital system

Lots of data typesLots of data types Few data typesFew data types

User-defined package & libraryUser-defined package & library No user-defined packagesNo user-defined packages

Full design parameterizationFull design parameterization Simple parameterizationSimple parameterization

Easier to handle large designsEasier to handle large designs

VVery consistent language. Code written and ery consistent language. Code written and simulated in one simulator will behave simulated in one simulator will behave exactly the same in another simulator.exactly the same in another simulator. E.g. E.g. strong typing rules.strong typing rules.

LLess consistent language. If you don't ess consistent language. If you don't follow some adhoc methodology for coding follow some adhoc methodology for coding styles, you will not get it right.styles, you will not get it right.

IItt executes differently on different platforms executes differently on different platforms unlessunless you follow some adhoc coding rules.you follow some adhoc coding rules.


VHDL vs. Verilog (Cont.)VHDL vs. Verilog (Cont.) It does seem that It does seem that VerilogVerilog is easier for designing at the is easier for designing at the

gate-level, but that people who do higher level simulations express a gate-level, but that people who do higher level simulations express a preference for preference for VHDLVHDL

VHDL places constraints on evaluation order that limit theVHDL places constraints on evaluation order that limit theoptimizations that can be performedoptimizations that can be performed

– Verilog allows the simulatorVerilog allows the simulator greater freedomgreater freedom

– For example, multiple levels of zero-delay gatesFor example, multiple levels of zero-delay gates can be collapsed into a can be collapsed into a single super-gate evaluation in Verilogsingle super-gate evaluation in Verilog

– VHDL requires preserving the original number of delta cycles of delayVHDL requires preserving the original number of delta cycles of delayin propagating through those levelsin propagating through those levels

VHDLVHDL VerilogVerilog

In Europe the VHDL is the most popular In Europe the VHDL is the most popular languagelanguage

Based on Pascal languageBased on Pascal language Based on C languageBased on C language

Most FPGA design in VHDLMost FPGA design in VHDL Most Most ASIC design in VerilogASIC design in Verilog


VHDL vs. Verilog: Process blockVHDL vs. Verilog: Process block VHDL:

process (siga, sigb)

begin

…...

end;

Verilog:always @ (siga or sigb)

begin

….

end


VHDL vs. Verilog:VHDL vs. Verilog:Concurrent Signal AssignmentConcurrent Signal Assignment

VHDL:c <= a and b;

Verilog:assign c = a & b ;


VHDL vs. Verilog: Signal DelaysVHDL vs. Verilog: Signal Delays

VHDL:a <= transport b after 1 ns;

Verilog:#1 assign a = b;

» ‘a’ output is delayed by 1 time unit

» The ‘# ‘ operator is the delay operator

» # N will delay for N simulation units

» Delays can assigned to both inputs and outputs#1 assign a = #1 b;

» ‘b’ is delayed by 1 unit, then assigned to ‘a’, which is then delayed by 1 time unit


VHDL vs. Verilog: Clock GeneratorVHDL vs. Verilog: Clock Generator

VHDL:signal clk : std_logic := ‘0’;

process

begin

clk <= not (clk) after clkperiod/2;

wait on clk;

end;

Verilog:initial clk = 0;

always #(clkperiod/2) clk = ~ clk;


Verilog WeaknessVerilog Weakness

Not well suited for complex, high level modeling– No user defined type definition

– No concept of libraries, packages, configurations

– No ‘generate’ statement - can’t build parameterized structural models

– No complex types above a two-dimensional array


VHDL vs. Verilog:VHDL vs. Verilog:Managing Large designsManaging Large designs

VHDLVHDL::– Configuration, generate, generic and package statements all help Configuration, generate, generic and package statements all help

manage large design structuresmanage large design structures VerilogVerilog::

– There are no statements in Verilog that help manage large designsThere are no statements in Verilog that help manage large designs


VHDL vs. Verilog:VHDL vs. Verilog:Procedures and TasksProcedures and Tasks

VHDLVHDL::– allows concurrent procedure callsallows concurrent procedure calls

VerilogVerilog::– does not allow concurrent task callsdoes not allow concurrent task calls


VHDL vs. Verilog:VHDL vs. Verilog:Structural ReplicationStructural Replication

VHDLVHDL::– The The generate generate statement replicates a number of statement replicates a number of

instances of the same design-unit or some sub part instances of the same design-unit or some sub part of a design, and connects it appropriately of a design, and connects it appropriately

VerilogVerilog::– There is no equivalent to the There is no equivalent to the generate generate statement in statement in

Verilog.Verilog.


Languages “under development”Languages “under development”

SystemVerilogSystemVerilog– Extending Verilog to higher levels of abstraction for architectural Extending Verilog to higher levels of abstraction for architectural

and algorithm design and advanced verificationand algorithm design and advanced verification VHDL 200xVHDL 200x

– Goal of VHDL Analysis and Standards Group (VASG):Goal of VHDL Analysis and Standards Group (VASG):» Enhance/update VHDL for to improve performance, modeling Enhance/update VHDL for to improve performance, modeling

capability, ease of use, simulation control, and the type systemcapability, ease of use, simulation control, and the type system e.g.: e.g.: Data types and abstractions:Data types and abstractions:

– variant recordsvariant records

– interfacesinterfaces


Az összetettség csökkentésének Az összetettség csökkentésének módszereimódszerei

Language abstractionsLanguage abstractions use the language to describe use the language to describe complex matters without having to describe small complex matters without having to describe small detailsdetails– Functions and procedures are important parts of the Functions and procedures are important parts of the

language in order to handle complexitylanguage in order to handle complexity

Design hierarchyDesign hierarchy uses components in order to conceal uses components in order to conceal details - the black box principledetails - the black box principle– The term black box means that only inputs/outputs of a The term black box means that only inputs/outputs of a

component are visible at a certain levelcomponent are visible at a certain level

– It is the designer who decides how many different It is the designer who decides how many different hierarchies there are to be in the designhierarchies there are to be in the design


Fő sajátságokFő sajátságok VHDL uses the concept of delta delay to keep track of VHDL uses the concept of delta delay to keep track of

processes that should occur at a given time step, but processes that should occur at a given time step, but are actually evaluated in different machine cyclesare actually evaluated in different machine cycles

A delta delay is a unit of time as far as the simulator A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time hardware is concerned, but in the simulation itself time has no advancehas no advance


VHDL VHDL összetevőkösszetevők Components are a central concept in VHDLComponents are a central concept in VHDL Components are used, among other things, to build up Components are used, among other things, to build up

component libraries, e.g.:component libraries, e.g.:– microprocessorsmicroprocessors

– special user circuitsspecial user circuits

– other standard circuitsother standard circuits If a “good” component has been designed, it can be saved in a If a “good” component has been designed, it can be saved in a

component library, enabling it to be copied as many times as component library, enabling it to be copied as many times as required, i.e. components are reusablerequired, i.e. components are reusable– this is called creating instances, i.e. creating the component in a this is called creating instances, i.e. creating the component in a

schematic or in the text fileschematic or in the text file


Objektum alapú nyelvObjektum alapú nyelv

Staying with computer science a while longer, VHDL Staying with computer science a while longer, VHDL is an object-based language, i.e. what separates VHDL is an object-based language, i.e. what separates VHDL from object-oriented languages is that the language from object-oriented languages is that the language does not have inheritancedoes not have inheritance

Generic components and instantiation are typical for Generic components and instantiation are typical for object-based languagesobject-based languages

Generic components are components which can be Generic components are components which can be modified before instantiation, e.g. a generic modified before instantiation, e.g. a generic component which copes with different width for the component which copes with different width for the input and output signalsinput and output signals


Feketedoboz használataFeketedoboz használata The internal structure can be concealed from the designer - The internal structure can be concealed from the designer -

the black box principlethe black box principle In some cases there is no need to know how to component In some cases there is no need to know how to component

is structuredis structured The designer is usually only interested inThe designer is usually only interested in

– inputs and outputsinputs and outputs

– a specification function anda specification function and

– access timesaccess times The majority of hardware designers are used to working The majority of hardware designers are used to working

with black boxes such as the 74LSXX circuit family, for with black boxes such as the 74LSXX circuit family, for exampleexample


Fő nyelvi szerkezetekFő nyelvi szerkezetek

Tervezési egyedTervezési egyed-It is the basic unit of hardware descriptionIt is the basic unit of hardware description

- = egyed bejelentés + építmény= egyed bejelentés + építményEgyed bejelentésEgyed bejelentés:: fekete doboz modellfekete doboz modellÉpítményÉpítmény:: It describes the relationship between the It describes the relationship between the design design entityentity inputs and outputs inputs and outputs

Each Each architecturearchitecture consists of consists of concurrent statementsconcurrent statements denoted denoted by by CSCS


Concurrent statementsConcurrent statements define interconnected processes define interconnected processes and blocks that together describe a design’s overall behavior or and blocks that together describe a design’s overall behavior or structurestructure

They can be grouped using block statement. Groups of They can be grouped using block statement. Groups of blocks can also be partitioned into other blocksblocks can also be partitioned into other blocks

At this same level, a VHDL component (CP) can be At this same level, a VHDL component (CP) can be connected to define signals within the blocksconnected to define signals within the blocks

It is a reference to an entity It is a reference to an entity A process can be a single signal assignment statement or A process can be a single signal assignment statement or a series of sequential statements (SS)a series of sequential statements (SS)

Within a process, procedures and functions can partition Within a process, procedures and functions can partition

the sequential statementsthe sequential statements

Egyidejű és sorrendi utasításokEgyidejű és sorrendi utasítások


Elsődleges nyelvi elvonatkoztatásElsődleges nyelvi elvonatkoztatás

Tervezési egyed

Építmény

Egyed bejelentés

The primary abstraction level of a VHDL hardware model is the Design Entity. The Design Entity can represent a cell, chip, board, or subsystem

A Design Entity is composed of two main parts:

1) An Entity Declaration

2) An Architecture


An An Entity DeclarationEntity Declaration defines the defines the interface between the interface between the Design EntityDesign Entity and the and the environment outside of the environment outside of the Design EntityDesign Entity

An An ArchitectureArchitecture describes the describes the relationships between the relationships between the Design EntityDesign Entity inputs inputs and outputsand outputs

Elsődleges nyelvi elvonatkoztatás Elsődleges nyelvi elvonatkoztatás (folyt.)(folyt.)


ENTITYENTITY and2 and2 ISIS PORTPORT (a, b: (a, b: ININ bit; bit;

q: q: OUTOUT bit); bit);ENDEND and2; and2;

ARCHITECTUREARCHITECTURE example example OFOF and2and2 ISIS-- declaration here-- declaration here

BEGINBEGIN-- statement here-- statement here

ENDEND example; example;

Példa az egyedbejelentésre és az Példa az egyedbejelentésre és az építményreépítményre

The entity name in the Architecture has to be the same as the identifier of the corresponding Entity Declaration


Egyedbejelentés és építményEgyedbejelentés és építmény

A component is made up of two main parts:A component is made up of two main parts:– Entity:Entity: Port declaration for inputs and outputs Port declaration for inputs and outputs

– Architecture:Architecture: structural of behavioural description structural of behavioural description

Behaviour is defined as a collective name for Behaviour is defined as a collective name for functions, operations, behaviour and relationsfunctions, operations, behaviour and relations

Behaviour can also be a structural description, i.e. the Behaviour can also be a structural description, i.e. the component consists of other componentscomponent consists of other components

The entity can be regarded as a black box with inputs The entity can be regarded as a black box with inputs and outputsand outputs


Példák egyedbejelentésrePéldák egyedbejelentésre

eentityntity vhdlvhdl__component1component1 isis

portport ( ( aa : : inin std_logic; std_logic;

bb : : outout std_logic); std_logic);

endend vhdlvhdl__component1component1;;

entityentity vhdl_component vhdl_component22 isis

portport ( ( signalsignal a_in: a_in: inin std_logic; -- input std_logic; -- input

signalsignal b_out:b_out: outout std_logic); std_logic); -- output -- output

endend vhdl_component vhdl_component22;;


Egy építmény példakódjaEgy építmény példakódja

aarchitecturerchitecture vhdlvhdl__codecode ofof vhdlvhdl__component1component1 isis

beginbegin

B <= B <= notnot A; A;

........

endend vhdlvhdl__codecode;;

Two names are specified in the declaration of the Two names are specified in the declaration of the architecture: the component name which describes architecture: the component name which describes which entity the architecture belongs to, and which entity the architecture belongs to, and vhdl_code, which is the name of the architecturevhdl_code, which is the name of the architecture


Az egyedbejelentés jelölésmódjaAz egyedbejelentés jelölésmódja

entityentity <identifier_name> <identifier_name> isis

portport( [( [signalsignal] <identifier>:[<mode>] <type_indication>;] <identifier>:[<mode>] <type_indication>;

......

[[signalsignal] <identifier>:[<mode>] <type_indication>);] <identifier>:[<mode>] <type_indication>);

endend [ [entityentity] [<identifier_name>];] [<identifier_name>];

The word “entity” in the last line is not supported before the The word “entity” in the last line is not supported before the VHDL-93 standardVHDL-93 standard


A kapcsok üzemmódjaiA kapcsok üzemmódjai<mode> = <mode> = in, out, inout, buffer, linkagein, out, inout, buffer, linkage

inin: Component only read the signal: Component only read the signal

outout: Component only write to the signal: Component only write to the signal

inoutinout: Component read or write to the signal (bidirectional : Component read or write to the signal (bidirectional signals)signals)

bufferbuffer: Component write and read back the signal (no : Component write and read back the signal (no bidirectional signals, the signal is going out from the bidirectional signals, the signal is going out from the component)component)

linkagelinkage: Used only in the documentation: Used only in the documentation


Inout Inout vagyvagy Buffer Buffer

Mode inout should only be used in the case of bidirectional Mode inout should only be used in the case of bidirectional signalssignals

If the signal has to be reread, either mode buffer or an internal If the signal has to be reread, either mode buffer or an internal dummy signal should be useddummy signal should be used

The word signal is normally left out of the port declaration, as it The word signal is normally left out of the port declaration, as it does not add any informationdoes not add any information

Mode Mode inin and the name of the and the name of the entityentity after after endend can also be left can also be left outout


Példa az egyszerűsítésrePélda az egyszerűsítésre

entityentity gate1 gate1 isis

portport( ( signalsignal a,b: a,b: inin std_logic; std_logic;

signalsignal c: c: outout std_logic); std_logic);

endend entity entity gate1;gate1;

entityentity gate1 gate1 is -- is -- Identical with the above exampleIdentical with the above example

portport( a,b: ( a,b: std_logic; std_logic;

c: c: outout std_logic); std_logic);

endend;;


ÉpítményÉpítmény

An An architecturearchitecture defines a body for a component entity defines a body for a component entity An architecture specifies a behavior between inputs and outputsAn architecture specifies a behavior between inputs and outputs The architecture name is not the same as the component name: The architecture name is not the same as the component name:

instead an instead an architecturearchitecture is tied to an is tied to an entityentity


Az építmény jelölésmódjaAz építmény jelölésmódja

architecturearchitecture <architecture_name> <architecture_name> ofof <entity_identifier> <entity_identifier> isis

[<architecture_declarative_part>][<architecture_declarative_part>]

beginbegin

<architecture_statement_part> -- The body of the arch.<architecture_statement_part> -- The body of the arch.

endend [ [architecturearchitecture] [<architecture_name>];] [<architecture_name>];


MegjegyzésekMegjegyzések

The architecture declaration part must be defined before first The architecture declaration part must be defined before first beginbegin and can consist of, for example: and can consist of, for example:– typestypes

– subprogramssubprograms

– componentscomponents

– signal declarationssignal declarations


Egy inverter építményeEgy inverter építménye

architecturearchitecture dtfdtf ofof circir isis

beginbegin

b_out <= b_out <= notnot a_in; a_in;

endend dtfdtf;;


Fontos megjegyzésekFontos megjegyzések

An entity can be linked to several architectures such as An entity can be linked to several architectures such as behavioral and RTL descriptions, for examplebehavioral and RTL descriptions, for example

Note that VHDL does not differentiate between upper-case and Note that VHDL does not differentiate between upper-case and lower-case letterslower-case letters

The double dash “--” indicates that the rest of the line is The double dash “--” indicates that the rest of the line is commentarycommentary


A VHDL-benA VHDL-ben meghatározott logikai meghatározott logikai operátorokoperátorok

NOTNOT ANDAND NANDNAND OROR NORNOR XORXOR EXOREXOR


Példa a logikai operátorokraPélda a logikai operátorokra

architecturearchitecture rtl rtl ofof circir isis

signalsignal int: std_logic; -- Internal signal declaration int: std_logic; -- Internal signal declaration

beginbegin

int <= int <= notnot (((a (((a nandnand b) b) nornor (c (c oror d)) d)) xorxor e); e);

aOutaOut <= int <= int andand f; f;

endend;;


MegjegyzésekMegjegyzések

Comments follow two hyphens '--' and instruct the analyzer to Comments follow two hyphens '--' and instruct the analyzer to ignore the rest of the line ignore the rest of the line

There are no multiline comments in VHDLThere are no multiline comments in VHDL

Tabs improve readability, but it is best not to rely on a tab as a Tabs improve readability, but it is best not to rely on a tab as a space in case the tabs are lost or deleted in conversion space in case the tabs are lost or deleted in conversion

You should thus write code that is still legal if all tabs are You should thus write code that is still legal if all tabs are deleted (use spaces as tabs!)deleted (use spaces as tabs!)


SzövegelemekSzövegelemek, , pl.pl. rögzített értékű tételekrögzített értékű tételek Sokféle alakú szövegelem létezik a VHDL-benSokféle alakú szövegelem létezik a VHDL-ben A következő kódok néhány példát mutatnak be:A következő kódok néhány példát mutatnak be:

entityentity lliterals1 iterals1 isis endend;;

architecturearchitecture bhvbhv ofof lliterals1 iterals1 isis

begin processbegin process

variablevariable I1 : integer; I1 : integer;

variablevariable R1 : real; R1 : real;

variablevariable C1 : C1 : charactercharacter;;

variablevariable S16 : S16 : stringstring(1 (1 toto 16); 16);

variablevariable BV4 : BV4 : bitbit__vectorvector(0 (0 toto 3); 3);




SzövegelemekSzövegelemek ( (folytfolyt.).)

beginbegin

-- Abstract literals are decimal or based literalsAbstract literals are decimal or based literals

-- Decimal literals are integer or real literals-- Decimal literals are integer or real literals

-- Integer literal examples (each of these is the same):-- Integer literal examples (each of these is the same):

I1 := 120000; I1 := 12e4; I1 := 120_000;I1 := 120000; I1 := 12e4; I1 := 120_000;

-- -- Based literal examples (each of these is the same):Based literal examples (each of these is the same):

I1 := 2#1111_1111#; I1 := 16#FF#; I1 := 2#1111_1111#; I1 := 16#FF#;

-- -- Base must be an integer from 2 to 16:Base must be an integer from 2 to 16:

I1 := 16:FFFF:; -- you may use a : instead of # I1 := 16:FFFF:; -- you may use a : instead of #

-- -- Real literal examples (each of these is the same):Real literal examples (each of these is the same):

R1 := 120000.0; R1 := 1.2e5; R1 := 12.0E4; R1 := 120000.0; R1 := 1.2e5; R1 := 12.0E4;

-- -- Character literal must be one of the 191 graphic charactersCharacter literal must be one of the 191 graphic characters

-- 65 of the 256 ISO Latin-1 set are non-printing control-- 65 of the 256 ISO Latin-1 set are non-printing control

-- characters-- characters

C1 := 'A'; C1 := 'a'; -- C1 := 'A'; C1 := 'a'; -- these are different!these are different!


SzövegelemekSzövegelemek ( (folytfolyt.).)

-- -- String literal examples:String literal examples:

S16 := " string" & " literal"; -- S16 := " string" & " literal"; -- concatenate long stringsconcatenate long strings

S16 := """Hello,"" I said!"; S16 := """Hello,"" I said!"; -- -- doubled quotesdoubled quotes

S16 := %string literal%; S16 := %string literal%; -- -- can use % instead of "can use % instead of "

S16 := %Sale: 50%% off!!!%; S16 := %Sale: 50%% off!!!%; -- -- doubled %doubled %

-- -- Bit-string literal examples:Bit-string literal examples:

BV4 := B"1100";BV4 := B"1100"; -- -- binary bit-string literalbinary bit-string literal

BV12 := O"7777";BV12 := O"7777"; -- -- octal bit-string literaloctal bit-string literal

BV16 := X"FFFF";BV16 := X"FFFF"; -- -- hex bit-string literalhex bit-string literal

wait;wait;

end processend process; -- ; -- the wait prevents an endless loopthe wait prevents an endless loop

endend; ;


Pl.Pl.: : két bemenet és egy kimenetkét bemenet és egy kimenet

entity halfAdder is

port (x, y : in bit := '0'; sum, cOut : out bit); -- formals

end;

– Matching the parts of this code with the constructs you can see that the Matching the parts of this code with the constructs you can see that the identifieridentifier is is hhalfAdderalfAdder and that and that

x, y: in bit := '0'; sum, cOut: out bit

corresponds tocorresponds to

port_interface_listport_interface_list

– The portsThe ports x, y, sum, and and cOut are formal ports, or formals are formal ports, or formals

– This particular entity This particular entity hhalfalfAAdderdder does not use any of the other optional does not use any of the other optional constructs that are legal in an entity declarationconstructs that are legal in an entity declaration


Példa egy félösszeadóraPélda egy félösszeadóra

The following architecture body (we shall just call it an architecture from now on) The following architecture body (we shall just call it an architecture from now on) describes the contents of the entity describes the contents of the entity hhalfAdderalfAdder::

architecture architecture dtfdtf of of hhalfAdderalfAdder is is

beginbegin

ssumum <= <= xx xor xor yy;;

cOcOutut <= <= xx and and yy;;

end end dtfdtf;;


ÉpítményÉpítmény

We use the same signal names, the formals: We use the same signal names, the formals: ssumum , , xx , , yy , and , and cOcOutut, in the , in the architecture as we use in the entityarchitecture as we use in the entity

– we say the signals of the "parent" entity are visible inside the we say the signals of the "parent" entity are visible inside the architecture "child"architecture "child"

An architecture can refer to other entity-architecture pairs (i.e., we can nest An architecture can refer to other entity-architecture pairs (i.e., we can nest black boxes)black boxes)

We shall often refer to an entity-architecture pair as We shall often refer to an entity-architecture pair as entity(architecture)entity(architecture)

For example, the architecture For example, the architecture bbhvhv of the entity of the entity hhalfAdder alfAdder is is hhalfAdder(alfAdder(bbhv)hv)


Kérdés-válasz az építményrőlKérdés-válasz az építményről

Q:Q: Why would we want to describe the outside Why would we want to describe the outside of a black box (an entity) separately from the of a black box (an entity) separately from the description of its contents (its architecture)?description of its contents (its architecture)?

A:A: Separating the two makes it easier to move Separating the two makes it easier to move between different architectures for an entity between different architectures for an entity (there must be at least one).(there must be at least one).

For example, one architecture may model an For example, one architecture may model an entity at a behavioral level, while another entity at a behavioral level, while another architecture may be a structural model.architecture may be a structural model.

Documents

A VHDL nyelv alapjai n VHDL nyelvi elvonatkoztatások n Tervezési hierarchiák – szerkezeti leírás