ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Final projectFinal project

Speaker:Aeag (柯鴻洋 )

Advisor: Prof. Andy Wu

2003/05/29

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Use fig. 8.30 as an example to design your 1-bit Edge-triggered DFF. Cascade four DFF’s to form a 4-bit Data register.

Cascade four 1-bit Full-adder(from Hw3) to form a 4-bit Ripple adder.

Use the 4-bit Ripple Adder and 4-bit Register to design an accumulator that can calculate

The serial input are 1,2,3,4,5 one data at a clock.

GoalGoal

5

1

15k

k

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Block diagramBlock diagram

4-bit full-adder D-FF

clk

reset

Input sum

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Ex1 for D-FF circuitEx1 for D-FF circuit

Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Ex1 for D-FF circuit cont.Ex1 for D-FF circuit cont.

Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Ex2 for D-FF circuitEx2 for D-FF circuit

Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Waveform for D-FFWaveform for D-FF

Ref [1]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Ex for 1-bit AccumulatorEx for 1-bit Accumulator

Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Expected WaveformExpected Waveform

Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Spice simulationSpice simulation

Ref [2]

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Hand inHand in

Using spice simulation to verify the function of 4-bit Ripple adder and 4-bit data register respectively.

A plot of the layout for 4-bit Ripple adder and 4-bit data register respectively.

Try to estimate the fasting clock rate. Use SPICE to simulate the speed of your circuit.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Hand in cont.Hand in cont.

What would be the critical path of the accumulator design? Please discuss.

According requirement (3) to combine the circuit of (1) and (2) to form an accumulator, you need to hand in the accumulator layout. And the accumulator or the design flow from (layout=>DRC=>LVS) must be verified correctly. (DRC and LVS’s report should be no errors, and result should been contained in your final report)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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ReferenceReference [1] “CMOS Integrated Circuits: Analysis and Design,” 3rd Ed., by Sun

g-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.

[2] http://www-unix.ecs.umass.edu/~alaffely/ECE658/2Lab/l2.html

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Good luck!

Thank you!