ADPCM-HCO_PB_1_5_2

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  • 8/6/2019 ADPCM-HCO_PB_1_5_2

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    ADPCM-HCO PSPSPSPS-IPIPIPIP

    Product Brief

    ________________________________________________________________________

    Page 1 of 2 ____________________________________________________________________________________________________________ Rev. 1.59/04 Copyright 2001 Pinpoint Solutions, Inc ADPCM-HCO

    ADPCM Voice Compression logic Core(HCO) High Channel-count optimizedDescription Block Diagram

    The Pinpoint Solutions Inc, ADPCM-HCO is ahardware optimized CMOS soft logic core,designed to perform the task of large-scale voicecompression as a co-processing system element.The design is a unique realization of the G.726algorithm that allows for a very high channelcount up to 672 full duplex channels may be

    processed by the core. The product supports theADPCM standard for digital voice compressionas defined in the ITU-T G.726 specification. Thetrue benefit of using the core is to significantly

    reduce transport or storage bandwidthrequirements. The core is designed to offload theinternal voice processing tasks from RISC or DSP centric architectures. Flexibility is key tothe usage of this core for final implementation asan ASIC, FPGA or element in a SOC design.

    Product features:

    Processes 1 to 672 full duplex, 1344 half duplex

    voice channels.

    Simple synchronous bus interface.

    No register based configuration or core setup isrequired.

    Sequential channel processing, addressed channel

    operation.

    Channel by channel, frame by frame

    encode/decode, and code format.

    Implements ITU-T G.726 specification.

    (32, 24, 16 fixed rate codes)

    A-law, -law, Linear code format selection on a

    per channel basis.

    Single cycle encoding/decoding of voice samples

    ADPCM-HCOASIC/FPGA

    ExampleImplementation

    RAM1

    Data In

    RAM2

    RAM3

    RAM4

    RAM5

    RAM6

    ENCODEREngine

    DECODEREngine

    COMPRESSIONDECOMPRESSIONSTATE MACHINE

    I/OInterfaceControl

    HOSTINTERFACE

    LOGIC

    PCM to ADPCMADPCM to PCM

    Data Out

    Encode/Decode

    Nx6x24

    Nx6x24

    Nx6x24

    Nx6x24

    Nx6x24

    Nx6x24

    SD_out [13:0]

    S_in [13:0]

    CH # SELchannel [10:0]

    enable

    law [1:0]decode

    clk

    algo_reset

    timer [2:0]

    "State" RAMInterface

    Note: PSI does not supply the RAM "IP" elements.See memory requirements in the data sheet.

    I/OCOMMAND

    & CONTROL

    code[2:0]

    reset_n

    Key Benefits of Implementation: FPGA or ASIC Implementation.

    Lower power consumption.

    Scaleable channel count design.

    Reduced board space.

    Cost reduction (per channel associated cost).

    DSP/CPU Task offloading.

    Applications: (IAD) Integrated Access Devices.

    Voice/Data multiplexers.Channel Bank Voice Concentrators.

    Voice over IP/DSL (Packet/Cell/Frame) Voice Storage (selected record and playback). Wireless: DECT and Cellular. Voice Gateways.

    Videoconferencing. (SOHO) Small Office Home Office.

    DSL Modems.Cable Modem.

    (CO) Central office equipment.DSLAM.Cable Modem Head End equipment.Large scale Voice Concentrators.

    Computer Telephony Integration.Voice mail.WAN voice processing.

    PBX (Private Branch Exchange).

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    ADPCM-HCO PSPSPSPS-IPIPIPIP

    Product Brief

    ________________________________________________________________________

    Page 2 of 2 ____________________________________________________________________________________________________________ Rev. 1.59/04 Copyright 2001 Pinpoint Solutions, Inc ADPCM-HCO

    Specifications:

    Host Interface: Synchronous parallelInternal Ram requirements per channel:

    Nx6x24 bits per half-duplex channel

    Operating frequency:

    43.008MHz processing 672 channels (336 full-duplex)86.016MHz processing 1344 channels (672 full-duplex)

    Standards compliance: ITU-T G.726, (Optional G.727)

    Compression code rates: 32, 24, 16Kbs

    Deliverables Test bench for the logic core, and

    control scripts to run Verilogsimulations to exercise the ITU standardvectors for the all G.726 rates.

    Primetime script/shell for verifyingtiming of the core.

    Synthesis script/shell to assist insynthesis of the core.

    Test bench core coverage analysisdocument.

    Verilog RTL soft-logic core.

    HEW LETTPACKARD

    Integrated Access Device (Voice / Data Multiplexer)Using the ADPCM-HCO

    HEW LETTPACKARD

    WAN Services(Frame-Relay)

    (ATM)(Channelized)

    T3 (45Mbs)

    T3 (45Mbs)

    DATA Resources

    1 2 3

    4 5 67 8 9

    * 8 #

    Voice Resources

    672 VoiceChannels

    22.5MbsData pipe

    Location A

    1 2 34 5 67 8 9

    * 8 #

    DATA Resources

    Location B

    672 VoiceChannels

    22.5MbsData pipe

    Voice Resources

    *Note: Application based on 32Kbps voice algorithm.

    PSI Reference Documents

    ADPCM-HCO Data sheetApplication notesWhite papers

    Options core include: Scalable encoding/decoding channel

    counts. Auto-channel Processing mode. Logic BIST

    Custom Interface options. FPGA specific targeting. Asynchronous bus interface. VHDL testbench. ITU-T G.727 support.

    Product InformationUpon request, PSI will provide complete quotationfor this product including: pricing, deliverables list,and licensing agreements.

    Pinpoint Solutions. Inc.5171 Eldorado Springs DriveBoulder, CO 80303Tel: 303.543.0050

    Fax: 303.494.5769HTTP:\\ www.asic-design.com

    Product Information Requests:mailto:[email protected]