An mK×nK bouwblok CCD image sensor family. I. Design

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002 361

An mK nK BouwblokCCD ImageSensor Family Part I: Design

Greg Kreider and Jan T. Bosiers, Member, IEEE

Abstract—This paper presents abouwblok family of [Author:Please define CCD] CCD image sensors, a set of devices of varyingsize built with a single pixel design from one mask set. It describesthe original design goals and how they led to dividing the layoutinto smaller blocks that could be stitched together to form a com-plete sensor. The architecture is traditional for large-area scientificdevices. The pixel design is optimized for large charge packets, an-tiblooming and low dark current, the horizontal register for bin-ning, and the output amplifier for fast pixel rates. The paper de-scribes how the design is split and modified to cover all possibleconfigurations and how to minimize the effects of stitching.

Index Terms—Charge transfer devices, charge transfer imagesensors, image sensors.

I. INTRODUCTION

SENSORS have an upper bound on their size. Traditionally,that has been the field of view of the lithographic equip-

ment used during processing. In the early 1990s, a single expo-sure magnifying stepper could expose 2–3 cm. Building sen-sors larger than this would require a new approach: split the de-sign into smaller pieces and expose each at the correct positionwithin the device, stitching the pieces together into a completeimager. If one sensor is divided, then the question follows: Can ageneral set of blocks be found to build “any” device? The familyof sensors built from these blocks would share the pixel and am-plifier designs and would have the same performance optimized,for example, for a large charge handling capacity, antibloomingprotection, low dark current, and fast readout.

Such a family has been created using a block of 10241024( K K) pixels. These sensors, meant for medical, sci-entific, and digital photography applications, use a fairly simpletechnology. The two challenges this work presented were di-viding the layout for the generalK K case and minimizingthe effects of stitching.

This paper describes the sensor family and stitching tech-nology. A companion paper [1] will characterize several sensorsmade in this technology.

II. DESIGN SPECIFICATION

The original specifications for the Frame Transfer Tech-nology, Full-Frame Sensor (FTF2020, 2.0 K2.0 K), the firstsensor in the family, had as key points the following:

Manuscript received October 31, 2001; revised February 2, 2002. The reviewof this paper was arranged by Editor J. Hynecek.

The authors are with the Philips Semiconductors Image Sensors, 5656 AAEindhoven, The Netherlands (e-mail: [email protected]).

G. Kreider is with Cypress Semiconductor, Nashua, NH 03063 USA.Publisher Item Identifier S 0018-9383(02)01558-7.

— Size: 2048 2048 active pixels, progressive scan;— Speed: 8 frames/s with a maximum horizontal fre-

quency of 36 MHz and a vertical frequency of 200kHz;

— (charge handling): 250 000 e in the pixel, 500000 e at the output;

— Conversion Factor: 5V/e;— Modulation Transfer Function: 57% at 42 lp/mm

(Nyquist);— Quantum Efficiency: 15% at 550 nm;— Dark Current: 1.2 nA/cmat 60 C.Note that these figures are not the actual performance figures,

as will be shown in the second paper, but are the values forjudging the success of the design. They also explain a numberof decisions made during design.

Initial calculations showed that a 12m 12 m pixel wasneeded to meet the specification. This created a problem:2048 pixels would form a square 2.52.5 cm , too big for thefield of view of the steppers (ASML PAS2500). The sensorwould have to bestitched, built from separate exposures ofsmaller blocks that merge in resist to form a single layer. Thetechnique in the vertical direction was already known fromthe Philips HDTV sensor, but no horizontal stitching had beendone.

In comparison to the 2 K 2 K sensors then on the market,the FTF2020 offered a high-speed (the competitors were limitedto 20 MHz pixel clocks), anti-blooming (not available in anysensor), a large SNR and a large dynamic range [2].

Originally, only the 2 K 2 K sensor was planned and thefirst design studies focused on the question of how to build it. Asthe studies progressed, the possibility and advantages of makinga family of sensors with this performance became clear; thatthese design goals are also competitive in many large area ap-plications is an important justification for extending the designto be able to offer products in new markets.

III. D ESIGN MOTIVATION

The design proposal for the FTF2020 called for the layoutto be divided into quadrants. Each quadrant would containa 1 K 1 K block of pixels, an output register, an amplifierand clock connections. Each quadrant would just fit into thestepper’s field of view, which is limited to 14 14 mm . Eachlayer (lithography specification for each fabrication step) wouldtherefore be split over four reticles and each would require fourexposures. There would be just two stitch lines through theactive area, one running horizontally and one vertically throughthe middle of the image section.

0018–9383/02$17.00 © 2002 IEEE

362 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002

Fig. 1. EEV (left) and Philips (right) stitching technologies. A and B are the vertical clocks, and C and D the horizontal register clocks.

Splitting devices into smaller parts and pasting them togetherin lithography was not a new idea. EEV was the first to exploitthis technique in their P88000 series of sensors. They split animager horizontally into two pieces, as shown in Fig. 1 [3], [4].The one piece contained clock routing, the output amplifier andsections of the horizontal register and pixel array (298 columnsin total) from the left end of the sensor. It also contained the same“terminating” structures for the right side, without any columnsfrom the pixel array, placed back-to-back with the first set. Inother words, this piece was centered on the scribe lane and hadparts of sensors from either side. The second piece containedonly columns and register cells—the middle of a sensor. An im-ager could be built by stitching two copies of the first piece to-gether and inserting copies of the second block to lengthen thedevice (in multiples of 470 columns). EEV chose this design be-cause their stepper’s optical field size was too small to fabricatea 1152 770 imager. They also extended the technique to longlinear arrays.

Philips’ HDTV sensor, the FT8, also had too large an imagingarea and had to be stitched Fig. 1 [5]. The design was dividedvertically into an image and a storage section and stitched alongthe edge of the light shield. The position and orientation of thestitching minimized distortions to images.

A generalbouwblok(trans.: “building block”) design, onecapable of building a family of sensors in multiples of someblock size, combines both these approaches. The key techniqueneeded is the ability to stitch both horizontally and vertically.How to divide a layout into blocks (smaller units that are assem-bled into a complete sensor) is a question involving a trade-offbetween mask costs and fabrication time, but the basic principleremains. It is a technology that is used to make other very largeintegrated devices, such as flat panel displays [6] and amor-phous silicon circuits. One can draw a parallel between stitchingand the organization of a sensor’s design during chip layout. Ina layout, one builds a hierarchy of cells, beginning with a pixeland a serial register element, adding “transition” cells to connectto clock lines or the output stage, combining these into largerunits representing the image array, the storage, or the readoutCCD and finally placing everything together in the final design.

Stitching stops this process mid-way, setting partially assem-bled blocks onto reticles (masks, or plates with the layout thatare used to pattern the structures on the layer) that are then com-bined into a whole during lithography.

The cost trade-off favors abouwblokdesign that uses blocksthat are as big as possible and as flexible as possible. Considerthe 2 K 2 K division first proposed. Each layer would be splitinto quadrants, with each quadrant filling a reticle. Each fabri-cation step would then require four reticles and four exposures.Another layout split into nine separate but smaller blocks wouldpack better onto the masks. Only 1.5 reticles per layer wouldbe needed (note that different layers can in principle be com-bined on a single reticle; such mask layouts may or may notbe desirable for production purposes, depending on productionvolume). The number of exposures would increase, however, to16. Depending on the anticipated production volume, the incre-mental costs of the extra lithography steps may be greater thanthe savings in masks. Extend this argument now to anK Kfamily of sensor, which requires 13 blocks. The first design,which combines a pixel array with peripheral structures, woulduse 13 reticles per layer and exposures. The second, with13 smaller blocks, can pack them onto 2.5 reticles per layer butrequires exposures. The savings in mask costsare significantly greater than the extra lithography time over theproduct’s lifetime. Now consider a mask set based on blocks of512 pixels. The general solution would require 17 blocks, whichwould fit on two reticles. exposures wouldbe needed and in this case the mask savings are not enough tocover the extra stepper time. Therefore, the design of thebouw-blok family is based on a flexible set of “smaller” blocks thateach are as large as possible for the reticle (that is, based on1 K 1 K pixels).

IV. A RCHITECTURE

The architecture of this sensor family helps to easily split thedesign into blocks. It is a typical organization for large-area sci-entific sensors (Fig. 2). There are four output amplifiers, one in

KREIDER AND BOSIERS: K K BOUWBLOKCCD IMAGE SENSOR FAMILY PART I 363

Fig. 2. Architecture of eachbouwbloksensor, showing the major components,split clock lines, and readout possibilities (arrows).

each corner of the chip, each with its own set of supply volt-ages and fed from two serial registers that lie above and belowthe image section. All CCD clock lines are divided along thecenter lines of the imager. The six sets of clocks (the left andright sides of the vertical CCDs are connected in polysilicon)can be driven to read the imager through one, two, or four out-puts. The divided image clock lines, although they complicatethe layout of the generalbouwblokmask set, also make a simpleframe transfer sensor possible by adding a light shield over halfthe image array. The sensors have extra pixels too: dummy reg-ister cells, dark reference columns, active timing columns, anddark lines that must be placed in the periphery of the device.Each end of the output registers before the output gate has anextra gate: the summing gate for horizontal binning (combiningpixels in the horizontal direction). Vertical binning is done di-rectly in the horizontal register. For the 2 K2 K imager, theseconsiderations imply three natural stitch lines in each direction.One crosses the center of the chip, one bounds the upper/leftedge of the image array (separating the periphery from the pixelmatrix) and one the lower/right edge. In total, the design is splitinto 16 blocks.

V. SENSORDESIGN

A standard Philips pixel for frame transfer imagers was usedas the basis cell for thebouwbloksensors (see, for example,[7], but without metal strapping). The pixel uses four clockphases in a two-layer polysilicon process to maximize chargehandling and yield (Fig. 3). The gates do not overlap to minimizecapacitanceandarethicktominimizeresistance.ThisreducesRCeffects and leads to higher clocking frequencies. The fabricationprocess does not permit metal strapping, so the total resistance

will remain relatively large. There is an antiblooming regionalong the center of the channel, a thinnedwell under the

channel that forms a smaller barrier to the substrate. Anopening is made between the gates above the channel stopto form a “window” to the bare silicon. This improves bluesensitivity. The cell is passivated to strongly reduce the darkcurrent.

The simulations of the design focused on the pixel’s chargehandling ability and transport of large packets. The modelsincluded RC effects on clock waveforms, process simulationsfor the doping profile within the pixel, three-dimensional (3-D)electrostatic simulations of the pixel and serial register cell andtwo-dimensional (2-D) electrodynamic studies of transport intothe horizontal register and out of the summing gate.

The conditions on the inter-pixel voltages follow [8]. Theyspecify the antiblooming barrier during integration and trans-port, the separation of the packet from the silicon-silicon dioxideinterface, the pixel-pixel separation, and charge reset (electronicshuttering) state. The 3-D off-state calculations made to checkthese conditions used the layout of the pixel and a simulation ofthe fabrication process (implantations and drive-ins). One result,for example, is that a 0.4 V antiblooming barrier during integra-tion is present with a 0.8 V barrier to neighboring pixels, a 1.4V separation to the interface, and inversion under the blockinggate. Another result is that ke at the start of trans-port, with a 0.6 V antiblooming barrier, 1.8 V pixel-pixel sepa-ration, and 1.4 V to the interface. Such simulations fix not onlythe pixel layout but also the process.

The horizontal register uses a third polysilicon layer to forma three-phase CCD. There is no antiblooming protection andonly a deep region. Each gate connects directly to a widealuminum bus bar to minimize RC effects at high frequencies.Each cell measures 1250 m . Two-dimensional (2-D) elec-trostatic simulations showed that the cell could store two fullpackets. The serial CCD ends in a separately driven, larger sum-ming gate for horizontal binning. The size of this gate was ex-pected to be one of the critical parameters in the sensor’s de-sign. At 36 MHz, the pixel rate needed to reach eight frames/s,clocking over a long distance could become a problem if thedriving electrical fields are not large enough. Simulations in-cluded not only 2-D off-state models to check that four completepackets could fit under the gate, but also 2-D transient calcula-tions. The result showed that charge can be transported over adistance of more than 8m at 36 MHz, with the right drivingvoltages.

Another critical point in the design is the contacting to thechannel stops. Such contacts must be made between everycolumn and the upper and lower serial registers block accessfrom outside the image array. The contact is placed in thesecond dark line, whose layout is changed in compensation.This required extra simulations to ensure that no charge wouldbe trapped behind the contact and that transport would notdegrade. No problems were found.

A pixel clock frequency of 36 MHz demands a careful layoutof the output amplifier, since the bandwidth will need to beabove 110 MHz. The circuit used in the family is based on theFT8 HDTV design [5]. It has three source follower stages, withon-chip adjustable current sources for the first two. Each of the


Fig. 3. Pixel cell and midcell voltage profiles under three driving conditions.

four outputs is independent of the others, as is true for all volt-ages except the and substrates and the horizontal linking ofthe vertical clocks.

VI. BOUWBLOKDESIGN

The goals for the FTF2020 and later, for the family of sen-sors, demand small design rules to reach a high full well capacity(including binning), low dark current, high sensitivity and highspeed. For example, the channel stop must be as small as pos-sible to maximize the channel volume and to minimize the deadarea under the windows and the adjacent gate technology meanscontrolling the position of all polysilicon exposures to within0.2 m. The ASML PAS2500 lithography equipment which canreach these tolerances, with its 5projection, has a limitedfield of view. A large design must therefore be split into smallerpieces. The exact division for the generalK K solution isnot as simple as proposed above and suffers from complicationsthat arise from the nonsymmetrical aspects of the design. Thereare three: clock routing, the layout of bond pads in the cornersand the three-phase horizontal clocks.

A. Clock Routing

Where the split in the clock lines comes to lie depends on thesize of the imager. If there are an even number of blocks, thenthe division falls on a stitch line and the break straddles the line.This split creates two 1 K blocks, one with each half of the break,that are placed side-by-side. An odd number of blocks means thedivision lies in the middle of a 1 K block. This requires a single1 K block with one break. Sensors larger than 2 K also have afourth case, a block without a split. In total the clock routingdemands four separate blocks per side (Fig. 4).

Fortunately these effects can be limited to one layer. Thesplits do not affect any of the implantations, only the polysil-icon, contact and metal layers. The CCD’s are divided per blockinto two sets of 512 pixels, with breaks at either end and in themiddle. The metal layer is used to connect the gates as neededand takes up all the complications of the asymmetry. That is,although the underlying polysilicon and contact layers are di-vided into two sets per block, if the aluminum bus bars are notsplit then the CCD clocks are the same throughout the block. Forclock routing, for every layer except interconnect, thebouwblokdesign requires only four blocks, one on each side of the image

section. The metal layer uses sixteen blocks, one for each pos-sibility on each side.

The actual design splits the vertical clocks into yet smallergroups of 128 pixels. This gives more freedom in placing thelight shield; a small storage section for subsampled real-timeoutput [9] could be added to a sensor for digital photographyto give a real-time sample mode. A split-frame sensor is notpossible, however, because there is no way to rout image clocksfrom the center of the chip to the bond pads.

B. Bond Pads

Bond pads, which must lie next to the amplifier on both thehorizontal and vertical sides of the sensor, present a similar sym-metry problem. A 1 K 1 K device will have one block withtwo sets of pads at either end (Fig. 5). 2 K2 K devices needon one edge one block with bond pads at one end and one blockwith pads at the other. Larger devices need not only these two,but also 1 K spacers without any bond pads. The problem here isnot just the existence of the pads, but connecting them appropri-ately. This case can also be confined to just the metal layer. Thepresence of extra pads poses no risks, so the mask set containsonly two blocks for all other layers: one with the 1 K layout andone without bond pads. The interconnect will contain four op-tions, two where half of the bond pads are connected to actualstructures on the CCD and where the other half are tied to thesubstrate, one with connections on both sides (the 1 K setup)and one without bond pads.

C. Horizontal Clocks

These solutions for bond pads and clock routing seek to max-imize symmetry within the block by changing the layout at themidline and both ends. This is necessary because “stepping andrepeating” is inherently not a symmetrical process and reflectsonly the underlying design. For example, there is a fundamentaldifference between the left and right sides of the sensor, causedby the three-phase serial register. The clocks waveforms on ei-ther side are not identical (two phases must be swapped) andthe summing gates are in different polysilicon layers. All dif-ferences in the layout can be confined to the amplifier blocks,which are unique in each corner.

All told, the nonmetal layers need 13 distinct blocks for thegeneral layout.

1) Image block containing a 1024 1024 array of pixels.


Fig. 4. (Top) Routing complications and (bottom) the solution that confines the effects to the metal layer.

2) Register blockorhorizontal block containing a 1024 el-ement serial register, clock routing split into two halves of512 connected gates, and six (dark) lines of 1024 pixels.There are two copies, top and under, of two versions, onewith a double set of bond pads and one without.

3) Clocking block or vertical block containing 24 columns(20 dark and four timing) of 1024 pixels and clock routingsplit into eight sets of 128 pixels. There are two copies,left and right, of two versions, one with a double set ofbond pads and one without.

4) Amplifier block containing 24 6 dark pixels, 31 reg-ister cells (including seven dummy), vertical and hori-zontal clock routing, a summing gate, the amplifier, andtwo bond pads. There are four versions, one for eachcorner, named W, X, Y, and Z.

The aluminum layer contains 41 blocks. Of the 64 total per-mutations of the side blocks (4 sides4 routing options 4bond pad options), 28 represent impossible combinations. Forexample, the clock lines in the 1 K sensor split only in themiddle, so the two end cases are unnecessary. With four ampli-fier blocks and one light shield, the total number of interconnectblocks rises to 41.

Fig. 6 shows how some of these pieces assemble into differentconfigurations.

VII. STITCHING

Frame transfer (FT) sensors provide an interesting exampleof the flexibility of the “step and repeat” procedure. Addinga storage section to an imager with an odd number of blocksrequires a double exposure. Aluminum is a light field expo-sure, where the lithography step defines the space between pat-terns (what is etched). The exposures for a frame transfer sensortherefore define the active area. In a sensor with an odd numberof blocks, this region includes a half block and possibly severalfull blocks. A 3 K imager, for example, needs a 1.5 K line ac-tive area. Exposing two 1 K blocks with an offset of 512 linesinstead of 1024 correctly defines this area. The middle third isdoubly exposed, but this has no effect on etching. The final pat-tern is the sum of the two exposures. This same principle, ofshifting two exposures to generate an effect without requiringextra masks, also can be used to generate true dark lines. AnFT imager normally has an extra set of rows between the activearea and storage section that are also covered by a light shield.They serve as dark lines, pixels that integrate at the same timeas the image array to measure the offset dark current. Thebouw-blok design has no such rows. The image section butts directlyagainst the light shield. However, shifting the active area ex-posures by a few lines away from the split in the clock lines,


Fig. 5. (Top) Complications in the bond pads and (bottom) the solution that confines the effects to the metal layer.

thereby shrinking the number of extra rows on the opposite sideof the image section, creates the longer light shield.

For light field layers such as metal, a double exposure, a log-ical OR of the two exposed patterns, applies to the removal ofmaterial. Only areas that are not exposed in either of the twosteps remain after etching. For dark field layers (implantationsand contacts) a double exposure OR’s the patterns themselves.

These observations are one of the basic ideas behind stitching.But stitching is not just exposing two blocks next to each otherand ensuring the correct patterns develop. It must also minimizethe effects of any errors in the positioning. These include lateralshifts in the relative positions of the blocks, rotations, opticaldistortions during projection and changes in the exposure level.Even though the total alignment error is less than 0.2m acrossa 1 K 1 K block, when the stitch lines run through the imagearray, small deviations between pixels create visual defects. Forexample, a 0.1 m shift gives an 0.8% change in area, whichcan be seen on a monitor. A new technique must be found tominimize these errors.

The design solves the problem in three ways. First, the hor-izontal and vertical edges are made to run through insensitiveparts of the pixel: the blocking gate during integration and thechannel stop. This fixes the active size of all pixels within one

block so that any misalignments will have a smaller effect onthe image quality. For example, electrical differences from avarying channel stop width, created by stitching through thestopper implantation, are smaller than changes in the pitch,which would be created by stitching between the implantations.Second, small patterns are placed along the stitch line to smoothany discontinuities. Finally, the position of the blocks on thereticle is important, as pattern distortions created during maskwriting or exposure need to be minimized.

The effects of stitching are generally small: block-scalepatterns are more noticeable than local deviations. There are noproblems with transport over stitch lines (CTE measurementsare presented in the second paper). This includes the hori-zontal shift register at 36 MHz. The global effects of stitchingincluding shading in dark current, different values,different sensitivities between blocks and threshold offsets inthe amplifiers. At the stitch line itself there can be a small(0.5%) offset, brighter or darker, and a grid mask is used in acolor process to remove all artifacts.

The source of the deviations is known and can be attributedto the steppers. Locally, the patterns that compensate for mis-alignments are not perfect. Light field traces become wider andthe stitch line and dark field structures narrower. Along the ver-


Fig. 6. Block configuration in three different layouts. The stippled boxes show the exposures needed to remove the light shield for frame transfer devices.

tical shift line this leads to a variable window size and differentsensitivity. The 0.5% offset is the best (on average) that can beachieved. The horizontal stitch line has an even smaller offset.Stitch effects are somewhat sensitive to color, with a greater bluevariation across the vertical line and greater red variation overthe horizontal. Globally, small changes in the exposure param-eters, including focussing and wafer positioning, cause gradi-ents over the block. Such effects typically appear as a roundedcorner in the response of the block. They appear in the localdark current (extra shading term) and sensitivity (step of 1% be-

tween blocks, decreasing toward 0 in the center). One can, withan extra “grid” mask which places a ring of aluminum aroundthe edge of each pixel, better define the light-sensitive area andreduce these effects. Any stitch effects can be corrected by gainand offset correction.

VIII. T HE BOUWBLOKFAMILY

More than ten different configurations of sensors from thefamily have been fabricated. The smallest device was a 1 K1


TABLE ISUMMARY OF BOUWBLOKDEVICE CHARACTERISTICS

K (14.5 26.5 mm ) frame transfer sensor. The largest was a7 K 9K (88.2 112.5 mm) full frame device [10]. It has adiagonal length of 143 mm, the largest that could be made on a6" (150 mm) wafer. The large majority of these sensors workedin all four quadrants, even though the amplifiers lay only 4 mmfrom the wafer’s edge.

IX. DEVICE CHARACTERIZATION

A second paper [1] presents a complete description ofthe performance of this family. Table I highlights the mostimportant values. The most important goal and the one that hasrequired the most optimization (including process tuning andtesting different stitching structures) is the optical performanceat the stitch line, described above. The linear dynamic rangeis much higher than expected, due to the large charge packetsand much lower dark current; the first arises from the layoutand clocking of the CCD, the second from ongoing processimprovements in the fab. In general, the design reaches thegoals set for the first FTF2020 device.

X. CONCLUSION

The bouwblokfamily is a set of large-area K K im-agers built from smaller blocks for the medical, scientific anddigital photography markets. Each family member has the same12 m 12 m pixel and architecture and, within the limits

of scaling effects, the same performance. The layout organiza-tion into quadrants, with clock lines split along the horizontaland vertical edges, is flexible enough to accommodate frametransfer and full frame clock schemes, color and monochrome.The four amplifiers can be driven at 36 MHz data rates and aredesigned to handle binned packets. Stitching effects are small,less than 0.5%, and the inherent block-to-block variation (atmost 1%) can be corrected. The process of building sensors fromblocks trades the variable cost of stepper time with a lower fixedcost for design and reticles. It has proven successful with morethan 10 imagers fabricated, including a 6" wafer-scale device.

ACKNOWLEDGMENT

The authors would like to thank the efforts of the LithographyGroup within FABWAG under G. de Rooij, including P. Klerkxand R. Pellens, and the Technologists under H. Peek, includingJ. van der Heijden, M. Beenhakkers, and J. Maas. They wouldalso like to thank A. Theuwissen and B. Dillen for their help indefining thebouwblokconcept, as well as the people mentionedin the second article.

REFERENCES

[1] G. Kreider, B. Dillen, H. Heyns, L. Korthout, and E. Roks, “AnmK�nKBouwblokCCD image sensor family—Part II: Characterization,”IEEETrans. Electron Devices, vol. 49, pp. 370–376, Mar. 2002.


[2] “Data Sheets From the Manufacturer for the Following Devices EG&GReticon RA2000J (Preliminary Specification),” Kodak KAF-4200,Tektronix TK2048M and Thomson THX 7897M, Loral CCD441 andCCD442.

[3] P. Pool, W. Suske, J. Ashton, and S. Bowring, “Design aspects and char-acterization of EEV large area CCDs for scientific and medical applica-tions,” Proc. SPIE, vol. 1242, pp. 17–25, 1990.

[4] P. Pool, U.K. Patent Appl. 8 902 844.3, Feb. 9, 1989.[5] A. Theuwissenet al., “A 2.2 Mpixel FT-CCD imager, according to the

Eureka HDTV-standard,” inIEDM Tech. Dig., 1991, pp. 167–170.[6] S. Lee, R. Stewart, A. Ipri, D. Jose, and S. Lipp, “A 5� 9 inch polysil-

icon gray-scale color head down display chip,” inISSCC Dig. Tech. Pa-pers, 1990, pp. 220–221.

[7] H. Peek, A. Theuwissen, A. Kokshoorn, and E. Daemen, “Groove-fillof tungsten and poly-Si membrane technology for high performance(HDTV) FT-CCD imagers,” inIEDM Tech. Dig., 1993, pp. 567–570.

[8] M. van de Steeg, “A frame-transfer CCD color imager with vertical an-tiblooming,” IEEE Trans. Electron Devices, vol. ED-32, p. 1430, Aug.1985.

[9] J. Bosiers, “A 2/3" 2-M pixel progressive scan FT-CCD for digital stillcamera applications,” inIEDM Tech. Dig., 1998, pp. 37–40.

[10] M. Lesser, D. Ouellette, A. Theuwissen, G. Kreider, and H. Michaelis,“Packaging and operation of Philips 7 K� 9 K CCD’s,” in Proc. 1997IEEE Workshop on Charge-Coupled Devices and Advanced Image Sen-sors, Bruges, France, June 1997.

Greg Kreider received the Ph.D. degree electrical engineering from the Uni-versity of Pennsylvania, Philadelphia, in 1993, writing his dissertation on thedevelopment of a spatially variant CCD and its application in robotics.

He joined Philips Semiconductors Image Sensors, Eindhoven, the Nether-lands, in 1993, where he worked on very large area devices for the pro-sumermarket, including thebouwblokfamily. In 2001, he moved to Cypress Semicon-ductor, Nashua, NH.

Jan T. Bosiers(M’81) was born in Mortsel, Belgiumin 1956. He received the electronic engineeringdegree from Catholic University of Leuven, Leuven,Belgium, in 1980.

From 1980 to 1984, he was a Research Scientistwith the ESAT Laboratory, Department of ElectronicEngineering, University of Leuven, where he de-veloped high-resolution linear CCD imagers. From1985 to 1986, he was a Consulting Engineer withthe U.S. Naval Research Laboratory, Washington,DC, working on research and development of

deep-depletion, backside-illuminated CCDs for detection of UV and X-Rayradiation. Since October 1986, he has been with Philips, Eindhoven, TheNetherlands, in what is now the Image Sensors Group of Philips Semiconduc-tors. He has worked on the research, development, and project management ofCCD imagers for consumer and medical applications. He has contributed toseveral CCD papers presented at IEDM meetings and been published in IEEETRANSACTION ON ELECTRON DEVICES.

Dr. Bosiers received the first Walter Kosonocky Award honoring the bestpaper on electronic imaging for the years 1998–1999, for his 1998 IEDM con-tribution on FT-CCDs for digital camera applications.

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An mK×nK bouwblok CCD image sensor family. I. Design