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MIT Lincoln Laboratory

APS-2 Status

Vyshi Suntharalingam, Tony Soares, Rich D’Onofrio

May 30, 2008

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Status Items

• Diode capacitance and leakage extraction

• Plan for SOI FET noise testing

• New test board for 3D APS-2 imager chip testing (Tony)– We will send a pdf of schematic separately

• Overview of MIT-LL APS-2 testing hardware and software (Rich)

• Deliver packaged Back Illuminated imagers (no quartz)– MB21B wafer 9 R5C6– MB21B wafer 9 R4C3– MB21A wafer 3 R2C3– None of these were tested at MIT-LL

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Pixel Capacitance and Leakage ExtractionBack Illuminated APS2 Imager

• New measurements with Keithley 4200-SCS (better software and hardware control)

• Imager tested after Back Illumination (thinned to 50µm) and pad sputter

– Test Area=4160 pixels * (24m)2

– Substrate: n-type 3000 ohm-cm ~1.5e12 cm-3

• Full depletion not detectable– Dominated by lateral capacitance to

Channel Stops– At 10V: 11.5fF/pixel, 70fA/pixel

Scupper Pixels (p+) (VSCP)4 pixels wide

Substrate Contact (n+) Ring (VPDBIAS)4 pixels wide

256 x 256 pixel array

(p+ side of each diode connected to Tier-2

SOI circuit)

C-meter

Cu

rren

t(p

A/p

ix)

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Insight from Simulation (7/27/07)

Pixel #3

(p+)n-CS n-CS

n-3000 ohm-cm(3e12 /cm3)

50 u

m D

epth

n-substrate contact

5 x 24 um Width

Doping Profiles

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Two-Dimensional Simulation of 5 PixelsPotential Contours Show Effect of Varying Substrate Bias

Vsub=0V Vsub=2V Vsub=5V

Vsub=10V Vsub=14V0V

2V

5V

10V

Vsub=14V

Pot

entia

l (V

)Potential profile at center of pixel-3 (vertical “cut-line”)

Depth into Si

“cut

-line

”

(filename error)

50

50

10

50

10

For Vsub=10V, 15V: E-field is vertical from ~25 to 50 um depth into silicon. Nearer to the frontside we observe the lateral influence of the Channel Stops

From 7/27/07

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Reverse Bias of 15V

Vsub=15V (at backside)

15V 15V0V

8.5 um

18

Mic

ron

s

0V0V

From 7/27/07

Clateral

Csubstrate