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ARM architecture

Speaker: 陳 育 麟

Advisor: 陳 中 平 教授

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Outline

Features Core Interface Signals 3-stage pipeline organization Programmer’s Mode Conditional execution A basic ARM memory system ARM instruction set

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Features

RISC core Pipelined execution Load-store architecture Large uniform register file (R0 ~ R14) Fixed-length instruction field Conditional execution of all instructions

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Core Interface Signals

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3-stage pipeline organization

multiply

data out register

instruction

decode

&

control

incrementer

registerbank

address register

barrelshifter

A[31:0]

D[31:0]

data in register

ALU

control

PC

PC

ALU bus

A bus

B bus

register

CPU

PC instruction memory

data memory

address

data

address

data

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3-stage pipeline organization

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3-stage pipeline organization

fetch ADD decode execute

time

1

fetch STR decode calc. addr.

fetch ADD decode execute

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3

data xfer

fetch ADD decode execute4

5 fetch ADD decode execute

instruction

structural hazard!

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Programmer’s Mode

Visible registers

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Programmer’s Mode

T = 0: ARM executionT = 1: Thumb execution

Negative, Zero, Carry and oVerflow

I = 1: disable IRQ interruptF = 1: disable FIQ interrupt

CPSR

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Programmer’s Mode

Exception Vector Address

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Priorities

2

4

3

5

66

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Conditional execution

LOOP: … …

BNE LOOP;

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A basic ARM memory system

data memory

instruction memory

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A basic ARM memory system

4-way low order interleaving

Main memory

A9 ~ A2

Bank 3

A1A0 = 11

Bank 2

A1A0 = 10

Bank 1

A1A0 = 01

Bank 0

A1A0 = 00

00000000 [3] [2] [1] [0]

00000001 [7] [6] [5] [4]

00000010 [11] [10] [9] [8]

00000011 [15] [14] [13] [12]

00000100 [19] [18] [17] [16]

00000101 [23] [22] [21] [20]

00000110 [27] [26] [25] [24]

00000111 [31] [30] [29] [28]

11111111 [1023] [1022] [1021] [1020]

Size = 1KB

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ARM instruction set

Branch Data processing Status register transferring Load/Store Coprocessor Exception generating (SWI, BKPT)

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ARM instruction set

B, BL

SyntaxB{L}{<cond>} <target_address>

BL: the return address is stored in R14.

224 = 16MB ±8MB ±32MBsigned 2-bit interleaving

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ARM instruction set

BL usage

…CMP R0, #5; if R0 < 5 ; (flag: N,Z,C and V)BLLT SUB1; then call SUB1BLGE SUB2; then call SUB2 …

…

BL SUB; branch… ; return to here

…

SUB: … ; subroutine entry

…

MOV PC, R14; return

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Thank you!