I HC THI NGUYN I HC CNG NGH THNG TIN V TRUYN THNG KHOA CNG NGH T NG HA --------------

BO CO Mn: THC TP NGH BAN U Ti:TM HIU CU LNH CASE TRONG LP TRNH PHN CNG VHDL

Gio vin hng dn: Bi Vn Tng Nhm SV thc hin: Nguyn nh Hiu Trn Lai Thnh Nguyn Chin Huy

MC LCCHNG I: GII THIU BORAD DE2 CA ALTERA ............................................................................ I. Gii thiu ................................................................................................................................................. II. Thnh phn ............................................................................................................................................. III. Mt vi ng dng ca board DE2 ......................................................................................................... CHNG II: CU TRC MODULE ........................................................................................................... I. Khai bo modules .................................................................................................................................... II. Ch nh lin tip: ................................................................................................................................... III. Module instantiations: ........................................................................................................................... CHNG III: CC KIU D LIU ............................................................................................................ I. Cc kiu lit k (ENUMERATION) .......................................................................................................... II. Kiu nguyn ........................................................................................................................................... III. Cc kiu d liu tin nh ngha trong VHDL ...................................................................................... IV. Kiu mng............................................................................................................................................. V. Kiu Record ........................................................................................................................................... VI. Cc kiu STD_LOGIC ......................................................................................................................... VII. Cc kiu d liu c du v khng du ................................................................................................. VIII. Cc kiu con ....................................................................................................................................... CHNG IV: KHAI BO CNG VO/RA ................................................................................................ I. Cc cng c bn....................................................................................................................................... II. Cng buf, not .......................................................................................................................................... CHNG V: KHAI BO BIN.................................................................................................................... I. t gi tr ................................................................................................................................................. II. Wire ........................................................................................................................................................ III. Reg: ....................................................................................................................................................... IV. Integer (S nguyn) .............................................................................................................................. CHNG VI: KHI LNH CASE ............................................................................................................... CHNG VII: MT S V D .................................................................................................................... KT LUN......

GII THIU Verilog l mt trong hai ngn ng m t phn cng chnh (gm VHDL v Verilog HDL) c ngi thit k phn cng s dng m t, thit k cc h thng s, v d nh my tnh hay linh kin in t. Verilog d hc v d s dng hn VHDL. Verilog c chun ho theo chun IEEE vo nm 1995 v 2001. Verilog rt ging ngn ng C v c gii chuyn mn nghin cu, s dng nhiu. Verilog HDL c th c s dng thit k h thng s nhiu mc khc nhau, v d mc cao nh cc m hnh c trng n cc mc thp nh m hnh b tr dy, in tr, transistor trn mt mch tch hp; m t cc cng logic, flip_flop trong h thng s; m t thanh ghi v s di chuyn d liu gia cc thanh ghi (RTL - Register Transfer Level).

Ti sao s dng Verilog HDL ?H thng s l mt h thng phc tp bc cao. cp chi tit nht, chng c th bao gm hng nghn thnh phn nh: cc transistor hoc cc cng logic, cho nn vi h thng s ln, thit k mc cng khng cn s dng na. Qua nhiu thp k, gin logic ca cc thit k logic cng khng cn nhiu na. Ngy nay, s phc tp ca phn cng tng ln mt mc m gin ca cng logic hu nh v ch khi n ch biu din mt mng li phc tp cc lin kt khng theo chc nng ca thit k. T nhng nm 1970, cc k s in v my tnh i hng theo ngn ng m t phn cng (HDL). Hai ngn ng m t phn cng ni bt trong k thut l Verilog v VHDL nhng nhng nh thit k cng ngh thch s dng Verilog hn. Verilog cho php cc nh thit k logic thit k v m t h thng s nhiu mc khc nhau v c s h tr t cc cng c thit k bng my tnh gip cho vic x l thit k nhng mc khc nhau. Cch s dng c bn ca Verilog HDL trong thit k mch tch hp l m phng thit k v to mu trn FPGA trc khi chuyn sang sn xut. Mc tiu ca Verilog khng phi to ra nhng chip VLSI m s dng Verilog m t mt cch chnh xc chc nng ca bt k h thng s no v np chng trnh to mu ln FPGA, v d nh my tnh, cc b vi x l, tuy tc chm v lng ph din tch hn. Nhng thit k mc thp hn trong Verilog c thc hin trn VLSI t n tc cc i v c din tch cc tiu. Tuy nhin s dng thit k dng Verilog trn FPGA s tit kim chi ph v thi gian thit k. Vi nhng ng dng rng ri nh trn, thit ngh victhit kt mchsvi HDL v nhng ng dng ca n l rt cn thit.Do thi gian v s hiu bit c hn, chc chn trong qu trnh thc hin,chng em cng c nhiu thiu st, mong cc thy c v cc bn chn thnh gp . Chng em xin chn thnh cm n thy gio Th.S Bi Vn Tng hng dn, quan tm, ch bo tn tnh chng em hon thnh ti thc tp chuyn ngnh ny.

CHNG I: GII THIU BORAD DE2 CA ALTERA I. Gii thiuBoard DE2 l board mch phc v cho vic nghin cu v pht trin v cc lnh vc lun l s hc (digital logic), t chc my tnh (computer organization) v FPGA.

Hnh 1.Board DE2 II. Thnh phn Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht trin, di y l thng tin chi tit ca mt board DE2: FPGA: - Vi mch FPGA Altera Cyclone II 2C35. - Vi mch Altera Serial Configuration EPCS16. Cc thit b xut nhp: - USB Blaster cho lp trnh v iu khin API ca ngi dng; h tr c 2 ch lp trnh JTAG v AS. - B iu khin Cng 10/100 Ethernet. - Cng VGA-out. - B gii m TV v cng ni TV-in. - B iu khin USB Host/Slave vi cng USB kiu A v kiu B. - Cng ni PS/2 chut/bn phm.

- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in, line-out, v microphone. - 2 Header m rng 40-pin vi lp bo v diode. - Cng giao tip RS-232 v cng ni 9-pin. - Cng giao tip hng ngoi. B nh: - SRAM 512-Kbyte. - SDRAM 8-Mbyte. - B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte). - Khe SD card. Switch, cc n led, LCD, xung clock - 4 nt nhn, 18 nt gt. - 18 LED , 9 LED xanh, 8 Led 7 on - LCD 16x2 - B dao ng 50-MHz v 27-MHz cho ng h ngun. III. Mt vi ng dng ca board DE2 ng dng lm TV box

Hnh 2. TV Box

Chng trnh v bng chut USB (paintbrush)

Hnh 3. Chng trnh v (paintbrush) My ht Karaoke v my chi nhc SD

Hnh 4. My ht Karaoke v my chi nhc t card SD

CHNG II: CU TRC MODULE I. Khai bo modules Mt module l bn thit k ch yu tn ti trong Verilog. Dngu tin ca khai bo module ch r danh sch tn v port (cc is). Nhng dng k tip ch r dng I/O (input, output, hoc inout)v chiu rng ca mi port. Mcnh chiu rng port l 1 bit. Sau , nhng bin port phi c khai bo wire, wand, , reg.Mc nh l wire. Nhng ng vo c trng l wire khi d liu c cht bean ngoi module. Cc ng ra l dng reg nu nhngtn hiu ca chng c cha trong khi always hoc initial. 1. C php: Moduletn module (danh sch port); Input[msb:lsb] danh sch port ng vo; Output[msb:lsb] danh sch port ng ra; Inout[ msb:lsb ] danh sch port vo_ ra; cc lnh Endmodule 2. V d: Moduleadd_sub(add, in1, in2, out); Wire, reg, v tham s: Input[7:0 ] in1, in2; Wirein1, in2; Output[7:0] out; Regout; cc lnh khc Endmodule II. Ch nh lin tip: Cc ch nh lin tip c dng gn mt gi tr ln trn mtwire trong mt module. l cc ch nh thng thng bn ngoi khi always hoc khi initial. Cc ch nh lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s ch nh mt gi tr n mt wire trong lc khai bo. Ch rng, cc lnh ch nh lin tip th tn ti v c chy lin tc trong sut qu trnh m phng. Th t cc lnh gn khng quan trng. Mi thay i bn phi ca bt c ng vo s lp tc thay i bn tri ca cc ng ra.

1. C php: Wire bin wire = gi tr; Assignbin wire = biu thc;

2. V d: Wire[ 1:0 ] a = 2b 01; Assignb = c &d; Assignd = x | y; III. Module instantiations: Nhng khai bo module l nhngkhun mu m n c to nn t cc i tng thc t ( instantiation). Cc module n c bntrong cc module khc, v mi dn chng to mt i tng cnht t khun mu. Ngoi tr l module mc trn l nhng dnchng t chnh chng. Cc port ca module v d phi tha nhng nh ngha trong khun mu. y l mt l thuyt: bng tn, s dng du chm(.) .tn port khun mu ( tn ca wire kt ni n port). Bng v tr, t nhng port nhng v tr ging nhau trong danh sch port ca c khun mu ln instance.1. C php: Tn instance1 (danh sch kt ni port ); Tn instance2 (danh sch kt ni port); 2. V d: // nh ngha module Moduleand4(a,b,c); Input[3:0]a,b; Output[3:0]c; Assignc = a&b; Endmodule // module instantiations Wire[3:0] in1, in2; Wire[3:0] o1, o2; // t v tr and4 C1(in1, in2,o1); // tn and4 C2(.c(o2), .a(in1), .b(in2));

CHNG III: CC KIU D LIU Tt c cc i tng d liu trong VHDL cn phi c nh ngha vi mt kiud liu. Mt khai bo kiu phi ch ra tn v di ca kiu . Khai bo kiu d liuchng c php khai bo trong phn khai bo cc ng gi, trong phn khai boEntity, trong phn khai bo kin trc, trong phn khai bo cc chng trnh con vtrong phn khai bo cc Process. Cc kiu d liu bao gm cc kiu sau:- Kiu lit k. - Kiu nguyn. - Cc kiu d liu tin nh ngha. - Kiu mng. - Kiu bn ghi. - Kiu d liu chun logic. - Kiu d liu c du v khng du. - Cc kiu ph. I. Cc kiu lit k (ENUMERATION) Mt kiu lit k c ch ra bi vic lit k cc gi tr cho php ca kiu . Tt ccc gi tr c nh ngha bi ngi dng c th l cc tn nh danh, hoc c c kiu ch k t. Tn nh danh thc cht l mt tn do ngi dng t r a , chng hn nh blue, ball, monday. Kiu ch k t l kiu ca cc k t c kmtheo du nhy n, chng hn nh 'x', ' 0'... C php khai bo ca chng nh sau: Type type_name is (enumerattion_literal {, enumeration_literal}); Vi type_name l mt tn nh danh v mi enumerattion_literal hoc l mt tnnh danh hoc l mt ch k t. V d: Type COLOR is(RED,ORANGE YELLOW,GREEN, B L U E , PURPLE); type DAY is (MONDAY,TUESDAY,WEDNESDAY,THURDAY,FRIDAY); type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_'); Mi mt nh danh trong mt kiu u c mt v tr nht nh trong kiu, chngc xc nh bi th t xut hin ca chng trong kiu . Trong v d trn, mcnh RED c v tr 0,ORANGE s c v tr 1.... Nu chng ta khai bo mt it n g d l i u v i k i u l C O L O R v k h n g n h n g h a g i t r k h i t o t h i tng d liu s c khi to mc nh v tr u tin ca kiu lit k (v trkhng), trong trng hp ny COLOR s nhn gi tr RED. II. Kiu nguyn Kiu nguyn l cc kiu s nguyn, chng c dng cho cc php tnh, cc chs, cc iu khin s vng lp. Trong hu ht cc kiu thc thi trong VHDL c dit - 2,147,483,647 n + 2,147,483,647. C php ca chng c khai bo

nhsau: type type_name is range - 2,147,483,647 to + 2, 147, 483,647; V d: type INTEGER is range - 2,147,483,647 to + 2, 147, 483,647; type COUNT is range 0 to 10; III. Cc kiu d liu tin nh ngha trong VHDL IEEE nh ngha hai gi d liu STANDARD v TEXTIO trong th vin STD.Mi mt gi d liu ny c cha mt lot cc kiu v cc php tnh chun . Diy l cc kiu d liu c nh ngha trong gi STANDARD: - BOOLEAN:Mt kiu lit k vi hai gi tr True v False, cc thao tc Logic vcc php ton quan h s tr v gi tr Boolean. - BIT:Mt kiu lit k vi hai gi tr '0' v '1', cc php tnh logic c th ly v trv gi tr kiu BIT. - CHARACTER:Kiu lit k ca cc m ASCII. - INTEGER:c dng miu t cc s m v dng. Di hot ng ca chngc n nh t - 2,147,438,647 n 2,147,438,647. Cc hm ton hc nh cng,tr, nhn, chia c h tr kiu nguyn. - NATURE:Cc kiu con ca kiu nguyn c dng miu t cc s kiu tnhin (khng m). - POSITIVE:Cc kiu con ca kiu nguyn c dng miu t cc s dng. - BIT_VECTOR:c dng miu t mt mng cc gi tr kiu BIT. - STRING:Mt mng cc k t, mt gi tr kiu chui c i km bi du nhykp. - REAL:c dng m t cc kiu s thc, di hot ng t -1.0E+38 n+1.0E+38. - Kiu thi gian vt l:M t cc gi tr thi gian c dng trong m phng.C mt vi kiu d liu c nh ngha trong gi STANDARD nh sau: Type BOOLEAN is ( fase, true); Type BIT is ( '0', '1' ); Type SEVERITY_LEVEL is (note, warning, error, failure ); Type INTEGER is range -2,147,483,648 to 2,147,483,648; Type REAL is Range -1.0E38 to 1.0E38; Type CHARACTER is (nul, soh, stx, eot, enq, ack, bel,............); IV. Kiu mng Kiu mng l kiu ca nhm cc phn t c cng kiu ging nhau. C hai kiumng nh sau:- Kiu mng c gn kiu. - Kiu mng khng b gn kiu. Kiu mng b gn kiu l kiu m cc ch s mng ca chng c nh nghatng minh.C php ca chng nh sau: type array_type_name is array (discrete_range) of subtype_indication; y array_type_name l tn ca kiu mng c p kiu, discrete_rangekiu ph ca

kiu nguyn khc hoc kiu lit k, subtype_indication chnh l kiuca mi phn t ca mng. Kiu mng khng b gn kiu l kiu m ch s mng ca chng khng b ch ra,nhng cc kiu ch s ca chng phi c ch ra. C php ca chng c ch ranh sau: T y p e a r r a y _ t y p e _ n a m e i s a r r a y ( t y p e _ n a m e r a n g e < > ) o f subtype_indication; V d: type A1 is array ( 0 to 31) of INTEGER; type Bit_Vector is arrray (NATURAL range ) of BIT; type STRING is array (POSITIVE range ) of CHARACTER; A1 l mt mng gm ba hai phn t m trong mi phn t l mt kiu nguyn.Mt v d khc ch ra kiu Bit_vector v kiu String c to ra trong chun ccgi STANDARD. V d: subtype B1 is BIT_VECTOR ( 3 downto 0); variable B2 : BIT_VECTOR (0 to 10); Di ch s xc nh s phn t trong mng v hng ca chng (low to high | highto low). VHDL cho php khai bo cc mng nhiu chiu c th dng khai bo ccmu RAM v ROM.Xem v d di y: type Mat is array (0 to 7, 0 to 3) of constant ROM : MAT : = (( '0', '1', '0', '1'), ('1', '1', '0', '1' ), ('0', '1', '1', '1' ), ('0', '1' , '0', '0' ), ('0', '0' ,'0' ,'0'), ('1', '1' , '0', '0' ), ('1', '1' , '1', '1' ), ('1', '1' , '0', '0' )); X := ROM (4,3); Bin X s ly gi tr '0'. V. Kiu Record Kiu record l mt nhm c nhiu hn mt phn t c cc kiu khc nhau. Phn tca Record bao gm cc phn t ca bt c kiu no, n c th l cc kiu mnghoc kiu Record. V d: type DATE_TYPE is ( SUN, MON, TUE , WED , THR , FRI , SAT) ; type HOLIDAY isrecord YEAR : INTEGER range 1900 to 1999; MONTH : INTEGER range 1 to 12 ; DAY : INTEGER range 1 to 31; DATE : DATE_TYPE;

end record ; signal S : HOLIDAY; variable T1: integer range 1900 to 1999; variable T2 : DATE_TYPE; T1: = S.YEAR; T2:= S.DATE; S.DAY . When others s qut ht tt c cc gi tr c th ca n expression m cha c lit k ra trn (tng ng vi cc t kha default trong ngn ng lp trnh C). Dng 1. Process Begin (...)

Case ( selector When ... =>

expression ) is

Sequential statements; When ... => Sequential statements; When ... => Sequential statements; End case; ... End process; Dng 2. Process Begin Case ( selector When ... => Sequential statements; ... When others => Sequential statements; End case; ... End process; expression ) is (...)

CHNG II. MT S V D V LNH CASE VD1. DFF vi tn hiu reset khng ng b

5

1 0

1 5

20

25

30

35

40

45

50

55

60

65

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75

80

ns

rst d clk q

Hnh 1. Kt qu m phng

LIBRARY ieee; -- Unnecessary declaration, -- because USE ieee.std_logic_1164.all; -- BIT was used instead of -- STD_LOGIC ENTITY dff IS PORT (d, clk, rst: IN BIT; q: OUT BIT); END dff; ARCHITECTURE dff3 OF dff IS BEGIN PROCESS (clk, rst) BEGIN CASE rst IS WHEN '1' => q

IF (clk'EVENT AND clk='1') THEN q NULL;-- Unnecessary,rst is of -- type BIT END CASE; END PROCESS; END dff3;

VD2. { Lnh case gn gi tr cho u ra . Thit lp trang thi tip theo }PROCESS (input, pr_state) BEGIN CASE pr_state IS WHEN state0 => IF (input = ...) THEN output