Báo cáo thí nghiệm kĩ thuật số

7/22/2019 Bo co th nghim k thut s

1/28

pg

Bi Bo Co

Mn Th Ngim K Thut S

Trng i hc Bch Khoa TP HCM

TP.HCM --- 2013

Nhm 3

Khoa: in-in T

Thnh vin nhm:

H V Tn: MSSV

1. Tn Tht Nguyn Phong411025552. L Quang Sn......41102924

Bi th nghim 1Switches, Lights, Multiplexers

1.Thnghim1.1:

Thc hin mch th nghim c ng vo l 10 cng tc SW90, v ng ra l 10 n LED mu

LEDR90 dng c trng thi ca cc ng vo.

Cc bccn thchin:1. To project mi.2. Vit chng trnh Verilog cho bi TN3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch. Chng trnh ca nhm:

module TN1_1 (SW, LEDR);

input [9:0] SW;

output [9:0] LEDR;

assign LEDR = SW;

endmodule


2/28

pg

3 m

m

2.Thnghim1.2:

Cho mch multiplexer 2 sang 1 nh hnh 2 vi ng vo chn knh s. Nu s = 0 ng ra msbng ng vo x, v nu s = 1 th ng ra m = y.

x

m

s

y

a) Smch

s

s m

0 x x 0 m

1 y y 1

b) Bng s tht c) K hiu

Hnh 2. Mch multiplexer 2

sang 1.Mch c th m t dng mVerilog nh sau:

assign m = ( s&x) (s& y);

Dng 4 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 2 sang 1 - 4 bit nhhnh 3a. Mch c 2 ng vo nh phn 4 bit X v Y, v ng ra 4 bit M. Nu s = 0 th M = X ,cn s = 1 th M = Y.

s

x3 0 m3y3 1

X 02 s

Y3 1

x0 00

y0 1

4

X 0 4M

Y 1

4


3/28


4/28

pg. 4

3.Thnghim1.3:

Dng 3 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 4 sang 1nh hnh 4a.

Mch c 4 ng vo u, v, w v x; 1 ng ra m; 2 ng vo chn knh s1 s0

Tng t dng 2 mch multiplexer 41 nh hnh 4a thc hin mch

multiplexer 41-2bit nh hnh 5

s1

s0

u 0

v 10

1 m

w 0x 1

a) s mch

s1 s0 m

0 0 u0 1 v

1 0 w1 1 x

s1

s0

uxv 00

01

w 10 m11

x

b)bng s tht c) k hiuHnh 4. Mch multiplexer 4 sang 1

Cc bccn thchin:1. To project mi.2. Vit chng trnh Verilog vi:

s1 s0 = SW9-8 v ni vi LEDR9-8

U-X = SW7-0 v ni vi LEDR7-0M = LEDG1-0

3. Gn chn

4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .


5/28

pg. 5

Chng trnh ca nhm:module TN1_3(SW,LEDR,LEDG);

input [9:0]SW;

output [9:0]LEDR;

output [1:0]LEDG;

assign LEDR=SW;

Mux41(SW[8],SW[9],SW[0],SW[2],SW[4],SW[6],LEDG[0]);

Mux41(SW[8],SW[9],SW[1],SW[3],SW[5],SW[7],LEDG[1]);

endmodule

module Mux41(S0,S1,U,V,W,X,M);

input S0,S1,U,V,W,X;

output M;

wire t1,t0;

Mux21(S0,U,V,t0);

Mux21(S0,W,X,t1);

Mux21(S1,t0,t1,M);

endmodule

module Mux21(S,X,Y,M);

input S,X,Y;

output M;

assign M=(~S&X)|(S&Y);

endmodule


6/28

pg. 6

4.Thnghim1.4:

Thc hin b gii m c 2 ng vo c1 c0 v 7 ng ra t 0 n 6 dng hin th cc k ttrn b hin th7on nh hnh 6.Bng 1 lit k cc k t cn hin th(gm H,E,L v k t O) tng ng vicc ng vo c1 c0 . Cc ng ra tch cc mc logic 0.

c17-segment

decoderc0

0

56

1

4 2

3

Hnh 6. B gii m7 on

c1 c0 K t

0 0 H

0 1 E

1 0 L

1 1 O

Bng 1. Bng m ch Cc bccn thchin:

1. To project mi.

2. Vit chng trnh Verilog vi:

o Cc ng vo c1 c0 ni vi cc cng tc SW1-0

o Cc ng ra 06 ni vi HEX00, HEX01..HEX06

3. Gn chn

4. Bin dch project.

5. Np project vo kit TN.

6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.


7/28

pg. 7

Chng trnh ca nhm:module TN1_4(SW,HEX0);

input [1:0]SW;

output [6:0]HEX0;

reg [6:0] HEX0;

always @ (SW[1:0])

begin

case (SW[1:0])

2'b00: HEX0= 7'b0001001;

2'b01: HEX0= 7'b0000110;

2'b10: HEX0= 7'b1000111;

2'b11: HEX0= 7'b1000000;

default: HEX0= 7'b1111111;

endcase

end

endmodule


8/28

pg. 8

2

2

2

5.Thnghim1.5:

Thc hin mch in hin thch xoay nh hnh 7 hot ng theobng 2.Cc cng tc SW70 dng to k t v SW98 dng chn k t hin th.

SW9

SW8

SW7 62 0

SW5 4

SW3 2

SW1 0

0 00 1 2 7-segment1 0 decoder

75

61

4 2

3

Hnh 7. Mch c th chn & hin th 1 trong 4 k t.

SW9 SW8 Hin th

0 0 H

0 1 E

1 0 L1 1 O

Bng 2. Hin th ch xoay HELLO.

Cc bccn thchin:1. To project mi.2. Vit chng trnh Verilog vi:

3. Gn chn

4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.

Chng trnh ca nhm:module TN1_5(SW,HEX0,HEX1,HEX2,HEX3);

input [9:0]SW;

output [6:0]HEX0;

output [6:0]HEX1;

output [6:0]HEX2;

output [6:0]HEX3;


9/28

pg. 9

wire [1:0]A,B,C,D;

Mux412b(SW[9:8],SW[1:0],SW[7:6],SW[5:4],SW[3:2],A);

Mux412b(SW[9:8],SW[3:2],SW[1:0],SW[7:6],SW[5:4],B);

Mux412b(SW[9:8],SW[5:4],SW[3:2],SW[1:0],SW[7:6],C);

Mux412b(SW[9:8],SW[7:6],SW[5:4],SW[3:2],SW[1:0],D);

ganchu(A,HEX0);

ganchu(B,HEX1);

ganchu(C,HEX2);

ganchu(D,HEX3);

endmodule

module Mux412b(S,U,V,W,X,M);

input [1:0]S,U,V,W,X;

output [1:0]M;

Mux41(S[0],S[1],U[0],V[0],X[0],W[0],M[0]);

Mux41(S[0],S[1],U[1],V[1],X[1],W[1],M[1]);

endmodule

module Mux41(S0,S1,U,V,W,X,M);

input S0,S1,U,V,W,X;

output M;

wire t1,t0;

Mux21(S0,U,V,t0);

Mux21(S0,W,X,t1);

Mux21(S1,t0,t1,M);

endmodule


input S,X,Y;

output M;


endmodule


10/28

pg. 10

module ganchu(S,HE);

input [1:0]S;

output [6:0]HE;

reg [6:0] HE;

always @ (S[1:0])

begin

case (S[1:0])

2'b00: HE= 7'b0001001;

2'b01: HE= 7'b0000110;

2'b10: HE= 7'b1000111;

2'b11: HE= 7'b1000000;

default: HE= 7'b1111111;

endcase

end

endmodule


11/28

pg. 11

Bi th nghim 2Numbers &Displays

y l bi th nghim thit k mch t hp thc hin b bin i s nh phn sang sthp phn v mch cng hai s BCD.

1.Thnghim2.1:

Dng cc n 7 on HEX1 v HEX0 hin th cc s thp phn t 0 n 9. Gi tr hinth thay i cbng cc cng tc SW74 v SW30 tng ng.

Cc bccn thchin:1. To project mi.2. Vit chng trnh Verilog cho bi TN3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch bng cch thay i cc cng tc v quan st cc

n hin th.

Chng trnh ca nhm:

module TN2_1(SW,LEDR,HEX0,HEX1);

input [7:0]SW;

output [6:0]HEX0,HEX1;

output [7:0]LEDR;

assign LEDR=SW;

ganso (SW[3:0],HEX0);

ganso (SW[7:4],HEX1);

endmodule

module ganso(S,M);

input [3:0]S;

output [6:0]M;

reg [6:0]M;

always@(S[3:0])

case(S[3:0])

4'b0000: M=7'b1000000;

4'b0001: M=7'b1001111;

4'b0010: M=7'b0100100;

4'b0011: M=7'b0110000;


12/28

pg. 12

4'b0100: M=7'b0011001;

4'b0101: M=7'b0010010;

4'b0110: M=7'b0000010;

4'b0111: M=7'b1111000;

4'b1000: M=7'b0000000;

4'b1001: M=7'b0010000;

default: M=7'b1111111;

endcase

endmodule

2.Thnghim2.2:

Thc hin 1 phn ca mch chuyn i s nh phn 4 bit V = v 3 v2 v1 v0 thnh s thp phn

D=

d1 d0 nh hnh 1,bn g 1. Mch bao gm mch so snh ( kim tra V > 9), mchmultiplexer v mch A (cha cn thc hin mch B v b gii m 7 on). Mch s c ngvo V 4 bit, ng ra M 4 bit v ng ra z.

Binary value Decimal digits

0000 0 00001 0 10010 0 2. . . . . . . .

1001 0 91010 1 01011 1 1

1100 1 21101 1 31110 1 41111 1 5

Bng1. Bng gi tr chuyn i nh phn thp phn.

Cc bccn thchin:1. To project mi. Vit chng trnh

2. Bin dch project v thc hin m phng3. Vit thm on chng trnh cho mch B v mch gii m 7 on. Dng cc

cng tc SW30 nhp s nh phn V v cc n 7 on HEX1, HEX0 hin th s thp phn d1 d0

4. Bin dch li ri np project vo kit TN.5. Th mch: thay i gi tr V v quan st cc n hin th.


13/28

pg. 13

z

Comparator

Circuit B

d1

0

75

61

4 2

v3 0m3 3

0 1

v2 0m2

17-segment 7

decoder

d0

0

56

1

v1 0

1 m1

v0 0m0

1

4 2

3

Circuit A

Hnh 1. Mch chuyn i nh phn-thp phn. Chng trnh ca nhm:


input [3:0]SW;

output [3:0]LEDR;


assign LEDR=SW;

wire [3:0]M,N;

ss4bvoi9(SW,M,N);

ganso(M,HEX0);

ganso(N,HEX1);

endmodule

module ss4bvoi9(B,M,N);


14/28

pg. 14

input [3:0]B;

output [3:0]M,N;

reg [3:0]M;

reg [3:0]N;

always@(B[3:0] or M or N)

if (B[3:0]


15/28

pg. 15

3.Thnghim2.3:

Cho mch cng ton phn (FA) nh hnh 2a vi cc ng vo a, b, and ci, c c ng ra s vco .

co s = a +b + ci.

Dng 4 mch cng FA nh trn thc hin mch cng 4 bit nh hnh 2d.Ci

a s cis

a FA

b 0 bco

co1

a) Mch cng FA b) K hiu

b a ci co sb3 a3 c3

b2 a2 c2b1 a1 c1

b0 a0 cin

0 0 0 0 0

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 1

1 0 1 1 01 1 0 1 01 1 1 1 1

FA FA FA FA

c s

Cout S3s2 s1 s0

c) Bng s tht d) Mch cng 4 bit

Hnh 2. Mch cng.

Cc bccn thchin:1. To project mi v vit chng trnh Verilog cho mch cng:

Ni cc ng vo A, B v cin vi cc cng tc tng ng SW74 , S

W30 v SW8 v vi cc n LED mu LEDR

Ni cc ng ra cout v S vi cc n LED mu xanh LEDG

2. Gn chn, bin dch v np project vo kit TN

3. Th mchbng cch thay i cc gi tr khc nhau ca A, B v c in, quan st cc n

hin th.


16/28

pg. 16


input [8:0]SW;

output [8:0]LEDR;

output [4:0]LEDG;

assign LEDR=SW;

wire [3:1]c;

wire [2:0]s;

FA(SW[4],SW[0],SW[8],c1,LEDG[0]);

FA(SW[5],SW[1],c1,c2,LEDG[1]);

FA(SW[6],SW[2],c2,c3,LEDG[2]);

FA(SW[7],SW[3],c3,LEDG[4],LEDG[3]);

endmodule

module FA(a,b,ci,co,s);

input a,b;

input ci;

output co;

output s;

assign s = a^b^ci;

Mux21(a^b,b,ci,co);

endmodule


input S,X,Y;

output M;


endmodule


17/28

pg. 17

4.Thnghim2.4:

Thc hin mch cng 2 s BCD. Ng vo ca mch l 2 s A, B v ng vo cho s nhcin.Ng ra l s BCD, tng S1 S0 v s nhcout.

Cc bccn thchin:1. To project mi cho mch cng s BCD. Phi thc hin mch cng 2 s 4 bit A, B(th nghim 2.3)

v 1 mch chuyn i 5 bit tng s3s2s1s0co thnh 2 s BCD S1 S0 (th nghim 2.2)2. Vit chng trnh Verilog:

Ni cc ng vo A, B v cin vi cc cng tc tng ng SW74 , SW30v SW8 v vi cc n LED mu LEDR70

Ni cc ng ra cout v S vi cc n LED mu xanh LEDG40

Dng cc n 7 on HEX3, HEX2 hin th gi tr ca 2 s A v B vHEX1, HEX0 hin th kt quS1 S0 .

3. Gn chn, bin dch v np project vo kit TN4. Th mchbng cch thay i cc gi tr khc nhau ca A, B v c in, quan st cc nhin th.

Chng trnh ca nhm:module TN2_4(SW,LEDR,LEDG,HEX0,HEX1,HEX2,HEX3);

input [8:0]SW;

output [4:0]LEDG;

output [9:0]LEDR;

output [6:0]HEX0,HEX1,HEX2,HEX3;

wire [4:0]a;

assign LEDR=SW;

assign a[4:0] = SW[7:4] + SW[3:0] + SW[8];

assign LEDG = a;

reg [3:0]c;

reg [3:0]b;

always @ (a or c or b)

if (a


18/28

pg. 18

b = 4'b0001; end

else if (a


19/28

pg. 19

5.Thnghim2.5:

Thit k mch t hp chuyn i 1 s nh phn 6 bit thnh s thp phn di dng 2 s BCD.Dng cc cng tcSW50 nhp s nh phn v cc n 7 on HEX1 v HEX0 hin th s thp phn.

Chng trnh ca nhm:


input [5:0]SW;

output [9:0]LEDR;


wire [5:0]a;

assign LEDR=SW;

assign a[5:0] = SW[5:0];

reg [5:0]c;

reg [5:0]b;

always @ (a or c or b)

if (a


20/28

pg. 20

b = 6'b000100; end

else if (a


21/28

pg. 21

Bi th nghim 3Latches, Flip-flops, Registers

1.Thnghim3.1:

Hnh 1 m t mch RS latch dng cng logic.C 2 cch dng Verilog m t mch ny: dng cng logic (hnh 2a) v dng cng thclogic (hnh 2b).

R R_g

Qa (Q)

Clk

Qb

S S_g

Hnh 1. Mch RS latch dng cng logic.

// A gated RS latch

module part1 (Clk, R, S, Q);

input Clk, R, S;

output Q;

wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

and (R_g, R, Clk);

and (S_g, S, Clk);

nor (Qa, R_g, Qb);

nor(Qb, S_g, Qa);

assign Q = Qa;

endmodule

Hnh 2a. Dng cng logic m t mch RS latch.

// A gated RS latch

module part1 (Clk, R, S, Q);

input Clk, R, S;

output Q;

wire R_g, S_g, Qa, Qb /* synthesis keep */ ;

assign R_g = R & Clk;assign S_g = S & Clk;

assign Qa = (R_g Qb);

assign Qb = (S_g Qa);

assign Q = Qa;

endmodule

Hnh 2b. Dng cng thc logic m t mch RS latch.


22/28

pg. 22

C 2 cch thc hn: dng 1 LUT 4 ng vo (hnh 3a) v dng 4 LUT 2 ng vo (hnh 3b).

Clk

S4-LUT

Qa (Q)

(a) RS latch ch dng 1bng tham chiu 4 ng vo.

R4-LUT

R_g

4-LUT

Qa (Q)

Clk

4-LUT

S

S_g

4-LUT

Qb

(b) RS latch dng 4bng tham chiu 2 ng vo.Hnh 3. Cc cch thc hin mch RS latch

Cc bccn thchin:

1. To project RS latch2. Vit chng trnh Verilog theo hai cch 2a v 2b.3. Bin dch. Dng tin ch RTL Viewer so snh vi s mch hnh 1. Dng tinch Technology Viewer so snh vi s mch hnh 3b.4. To VectorWaveform File (.vwf) cho cc ng vo/ra. To dng sng cho cc

ng vo R v S ri dng tin ch Quartus II Simulator quan st cc dng sngR_g, S_g, Qa v Qb

Chng trnh ca nhm:module TN3_1(Clk,R,S,Q);

input Clk,R,S;

output Q;

wire R_g,S_g,Qa,Qb;

and (R_g,R,Clk);

and (S_g,S,Clk);

nor (Qa,R_g,Qb);

nor (Qb,S_g,Qa);

assign Q=Qa;

endmodule


23/28

pg. 23

2.Thnghim3.2:

Cho mch D latch dng cng nh hnh 4.

DS

S_g

Qa (Q)

Clk

QbR

R_g

Hnh 4. Mch D latch dng cng logic.

Cc bccn thchin:

1. To project mi vi chng trnh Verilog dng 2b cho mch D latch.2. Bin dch chng trnh. Dng tin ch Technology Viewer kho st mch.

3. M phng kim tra hot ng ca mch.4. Dng cng tc SW0 cho ng vo D, v SW1 cho ng vo Clk. Ni ng ra Q n LEDR0.5. Bin dch chng trnh li v np project vo kit TN.6. Th mchbng cch thay i cc ng vo D, Clk v quan st ng ra Q.


input [1:0]SW;

output [1:0]LEDG,LEDR;

assign LEDR=SW;

wire S,R,R_g,S_g,Qa,Qb;

assign S=SW[0];

not (R,SW[0]);

nand (S_g,S,SW[1]);

nand (R_g,R,SW[1]);

nand (Qa,S_g,Qb);

nand (Qb,R_g,Qa);

assign LEDG[0]=Qa,LEDG[1]=Qb;

endmodule


24/28

pg. 24

3.Thnghim3.3:

Cho mch master-slave D flip-flop hnh 5.

Master Slave

Qm QsD D Q D Q Q

Clock Clk Q Clk Q Q

Hnh 5. Mch master-slave D flip-flop. Cc bccn thchin:

1. To project mi dng 2 D flip-flop ca th nghim 3.2.2. Dng cng tc SW0cho ng vo D, v SW1 cho ng vo Clk. Ni ng ra Q n LEDR0.3. Bin dch chng trnh.4. Dng tin ch Technology Viewer kho st mch. M phng kim tra hot ngca mch.5. Th mchbng cch thay i cc ng vo D, Clk v quan st ng ra Q.

Chng trnh ca nhm:module TN3_3(SW,LEDG,LEDR);

input [1:0] SW;

output [1:0] LEDR,LEDG;

assign LEDR=SW;

wire t1,t0;

Dlatch1(SW[0],~SW[1],t1,t0);

Dlatch1(t1,SW[1],LEDG[0],LEDG[1]);

endmodule

module Dlatch1(D,Clk,Q,Q0);

input Clk,D;

output Q,Q0;


assign S=D;not (R,D);

nand (S_g,S,Clk);

nand (R_g,R,Clk);

nand (Qa,S_g,Qb);

nand (Qb,R_g,Qa);

assign Q=Qa,Q0=Qb;

endmodule


25/28

pg. 25

Clk Q

D Q Qb

D

Q

Q

Qb

Qc

Q Qc

4.Thnghim3.4:

Cho mch in hnh 6 vi D latch, D flip- flop kckcnh ln v D flip- flop kckcnh xung.

D D Q Qa

Clock

(a) Smch

Clock

D

Qa

Qb

Qc

(b) Gin d thi gian

Hnh 6. S mch v dng sng ca th nghim 3.4.

Cc b

c

cn th

chin:

1. To project mi.2. Vit chng trnh da trn on chng trnh gi nh hnh 7.3. Bin dch chng trnh.4. Dng tin ch Technology Viewer kho st mch.5. M phng kim tra hot ng ca mch. So snh hot ng ca cc phn

t trong mch.


26/28

pg. 26

Chng trnh ca nhm:module TN3_4(SW,LEDG,LEDR);

input [1:0] SW;

output [2:0] LEDG,LEDR;

assign LEDR=SW;

Dlatch1(SW[0],SW[1],LEDG[0]);

Dflipflop(SW[0],SW[1],LEDG[1]);

Dflipflop(~SW[0],SW[1],LEDG[2]);

endmodule

module Dflipflop(Clk,D,Q);

input Clk,D;

output Q;

wire t1;

Dlatch1(~Clk,D,t1);

Dlatch1(Clk,t1,Q);

endmodule

module Dlatch1(Clk,D,Q);

input Clk,D;

output reg Q;

always @(Clk,D)

if (Clk) Q=D;

endmodule


27/28

pg. 27

Bi th nghim 4Counters

1. Thnghim4.1:

Cho mch m ng b 4 bit dng 4 T flip-flops nh hnh 1.

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear

Hnh 1. Bm 4bit. Cc bccn thchin:

1. To project mi thc hin bm 16 bit dng 4 mch m nh hnh 1. Bin dchchng trnh. Ghi nhn s phn t logic (LEs) c dng? Tn s hot ng ti a(Fmax) ca mch m l bao nhiu?

2. M phng hot ng ca mch.3. Gn thm nt nhn KEY0 lm ng vo Clock, cc cng tc SW1, SW0 lm ng vo

Enable, Reset vcc n 7 on HEX3-0 hin th gi tr thp lc phn ca ng ramch m.

4. Bin dch li v np project vo kit TN.5. Th hot ng ca mch bng cch thay i cc cng tc v quan st cc n 7 on.6. Thc hin mch m 4 bit ri dng tin ch RTL Viewer quan st mch v so snh vimch in hnh 1.

Chng trnh ca nhm:moduleTN4_1(SW,LEDR,LEDG);

input [1:0]SW;

output [3:0]LEDR,LEDG;

assign LEDR=SW;

wire Q0,Q1,Q2,Q3,T1,T2,T3;

Tflipflop(SW[0],SW[1],Q3);and (T1,Q3,SW[1]);

Tflipflop(SW[0],T1,Q2);

and (T2,Q2,T1);


and (T3,Q1,T2);



28/28

assign LEDG[3]=Q0,LEDG[2]=Q1,LEDG[1]=Q2,LEDG[0]=Q3;

endmodule

module Tflipflop(Clk,T,Q);

input T,Clk;

output Q;

wire D;

xor (D,T,Q);

Dflipflop(Clk,D,Q);

endmodule

module Dflipflop(Clk,D,Q);

input D,Clk;

output Q;

wire t1;

Dlatch1(~Clk,D,t1);

Dlatch1(Clk,t1,Q);endmodule

module Dlatch1(Clk,D,Q);

input Clk,D;

output Q;


assign S=D;

not (R,D);

nand (S_g,S,Clk);

nand (R_g,R,Clk);

nand (Qa,S_g,Qb);nand (Qb,R_g,Qa);

assign Q=Qa;

endmodule

2.Thnghim4.2:

Thc hin li th nghim 4.1 dng m Verilog sau:

Q

Documents

Báo cáo thí nghiệm kĩ thuật số