CDF sensors processed on 6” wafers

OUTLINE: Material description Masks layout Sensor performances Process related

problems Conclusions

DPG Frühjahrstagung

Heidelberg, 15. - 19.März 99

•Frank Hartmann

Institut für Experimentelle

Kernphysik

Die CDF Silizium Sensoren in 6“ Technologie

Sensor Dimensions

Type Width(mm)

Length(mm)

Diagonal(mm)

SVXII L2 40.30 74.30 84.53

SVXII L4 60.17 74.30 95.61

ISL 59.26 74.77 95.41

Only 1 of these sensor can fit in a 4” wafer.

6” = cheaper6” detectors are even

longer than their 4” counterparts

Double sidedAC coupledPolySi BiasedSingle metalCommon P-stopsThickness 300mu

Type Pitch P (m) Pitch N (m)

SVXII L2 60 60

SVXII L4 65 65

ISL 112 112

Masks layout

ISL SVXII

L4 L2

Masks layout (details)

P-side N-side

Performances

SVXII L2 SVXII L4 ISL

P-side 6.1 pF 5.8 pF 5.25 pF

N-side 6.8 pF 6.6 pF 6.5 pF

Capacitance

Other parameters:SVXII L2p/n

SVXII L4p/n

ISL p/n

Coupling capacitor 100/130 pF 100/130 pF 150/150 pF

Bias resistance 4-6 M 4-6 M 4-6 M

Interstripresistance

> 2 G > 2 G > 2 G

ProblemsCoupling capacitor variation across the wafer

Uneven metal deposition due to sputtering problems

At the edges of the wafer the coupling capacitor falls below specifications

ProblemsCoupling capacitor breakdown voltage

Creation of pin-holes during operation in test beam

“Weak” coupling capacitor

Different “mix” of wet and dry oxide fixed the problem

Breakdown voltage of ISL sensors is currently under test with respect to bonding force at KA

ProblemsLeaky strips

Isolated strips and regions show high leakage current

Good strip

Leaky strip

Most strips are about 1 nA but a few go as high as A

Log scale

ProblemsLeaky strips

Leaky strips do not affect neighbors

The noise on them follow predictions (proportional to the square root of the current)

Get worse on the p-side if bias is present (MOS effect)

Breakdown at the Junction edges

Verified with Infrared CameraPresent even on the n-side when

defects are present at the p-stops edges

Most likely related to handling and cleaning conditions

Dust

Leaky strips (2)

Dust particles during processing

-> Inaccessible short between implant and p-stop (N-side)

-> fully biased strip Large effect on p-side stripsDistortion in local field--> clean room

improvements

Effect of isolation-diff shorts on the current profile Sensor ISL 1690-09 chip1

12914055-20

-224

0,1

1

10

100

1000

10000

100000

256

231

206

181

156

131

1068156316

-20

-45

-70

-95

-120

-145

-170

-195

-220

-245

strip# (n-side)cu

rre

nt

(nA

)

P-side leakage profile

N-side leakage profile

Latest deliveries

Problems got fixed

Pin-holes

SVXII and ISL sensors are double side and the bias will be split. PH is a connection of the implant to input of the PA (virtual GND)The PA will then have to deal with a DC coupled stripCurrent is not driven by the Si but by the bias circuit.Neighbors channels

will be noisy.

Pin-holes

On the N-side the electric field is weak. The effect is enhanced and up to 5 channels on each side will show higher noise.

Low interstrip resistance

•First appearance at 2nd step of quality control at KA

100nA10nA

1G

100k

3M

200k

Leakage current

Interstrip resistance

Bias resistor

Rbias

RintSolve: add. cleaning (charge up?)

Will it remain good after cleaning?

Conclusions

The workable area of a 6” wafer is almost twice the one of a 4” wafer6” Silicon performs as well as 4”.Switching from 4” to 6” can be painful but is surely feasible.Radiation hardness is the same as 4”.Availability of material in the market is not an issue.