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ISQED 2012, 13th International Symposium & Exhibits on

QUALITY ELECTRONIC DESIGN

Final CallFor PaPers

March 19-21, 2012. Santa Clara, CA, USA

PaPersareaCCePtedintheFollowingareas

System-level Design, Methodologies & Tools (SDM)Emerging system-level design paradigms, methods and tools aiming at quality. ESL design process and ow management. System-level design

modeling, analysis, synthesis, estimation and verifcation or correct high-quality hardware/sotware systems. Development o reliable, responsive

secure, and deect-tolerant systems. New concepts, methods and tools addressing the hardware and system design complexity, multitude o aspects

manuacturability, and usage o technology inormation and manuacturing eedback in the system-, RTL- and logic level design. The inuence o

the nanometer technologies issues on the system-, RTL- and logic-level design. System-level trade-o analysis and multi-objective (yield, powe

delay, area ) optimization. Eective and efcient development, implementation, analysis and validation o large SoCs integrating IP blocks rom

multiple vendors. Global, social, and economical implications o Electronic System and Design Quality. Emerging standards and regulations inu

encing system quality.

Robust & Power-conscious Devices, Interconnects, and Circuits (PCC)Power-conscious design methodologies and tools; low power devices, circuits and systems; power-aware computing and communication; system

level power optimization and management. Design techniques or leakage current management.

Design Verifcation and Design or Testability (DVFT)Hardware and sotware, ormal and simulation based design verifcation techniques to ensure the unctional correctness o hardware early in

the design cycle. DFT and BIST or digital and SoC. DFT or analog/mixed-signal ICs and systems-on-chip, DFT/BIST or memories. Test synthesi

and synthesis or testability. DFT economics, DFT case studies. DFT and ATE. Fault diagnosis, IDDQ test, novel test methods, eectiveness o test

methods, ault models and ATPG, and DPPM prediction. SoC/IP testing strategies. Design methodologies dealing with the link between testability

and manuacturing.

Design or Manuacturability/Yield & Quality (DFQ)DFM/DFY/DFQ defnitions, methodologies, matrices, and standards. Quality-based design methodologies and ows or custom, semi-custom, ASIC

FPGA, RF, memory, networking circuit, etc. Design ows and methodologies or SoC, and SiP. Analysis, modeling, and abstraction o manuacturing

process parameters and eects or highly predictable silicon perormance. Design and synthesis o ICs considering actors such as: signal integrity

transmission line eects, OPC, phase shiting, and sub-wavelength lithography, manuacturing yield and technology capability. Design or diagno

sability, deect detection and tolerance; sel-diagnosis, calibration and repair. Design and manuacturability issues or digital, analog, mixed signa

RF, MEMS, opto-electronic, biochemical-electronic, and nanotechnology based ICs. Redundency and other yield improving techniques. Global, social

and economic implications o design quality. Mask making methods and advances impacting manuacturability and yield.

Physical Design, Methodologies & Tools (PDM)Physical design or manuacturing; Physical synthesis ows or correct-by-construction quality silicon, implementation o large SoC designs. Too

rameworks and data-models or tightly integrated incremental synthesis, placement, routing, timing analysis and verifcation. Placement, opti

mization, and routing techniques or noise sensitivity reduction and fxing. Algorithms and ows or harnessing crosstalk-delay during physica

synthesis. Tool ows and techniques or antenna rule and electromigration rule avoidance and fxing. Spare-cell strategies or ECO, decoupling

capacitance and antenna rule fxing. Physical planning tools or predictable power-aware circuits. Reliable clock tree generation and clock distri

bution methodologies or Gigahertz designs. EDA tools, design techniques, and methodologies, dealing with issues such as: timing closure, R, L, C

extraction, ground/Vdd bounce, signal noise/cross-talk /substrate noise, voltage drop, power rail integrity, electromigration, hot carriers, EOS/ESD

plasma induced damage and other yield limiting eects, high requency eects, thermal eects, power estimation, EMI/EMC, proximity correction

& phase shit methods, verifcation (layout, circuit, unction, etc.).

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The International Symposium on Quality Electronic Design (ISQED) is the leading Electronic Design & Design Automation conerence, aimed a

bridging the gap among electronic design tools and processes, integrated circuit technologies, processes & manuacturing, to achieve design quality

ISQED is the pioneer and leading international conerence dealing with design or manuacturability and quality issues ront-to-back. ISQED empha

sizes a holistic approach toward electronic design and intends to highlight and accelerate cooperation among the IC Design, EDA, Semiconducto

Process Technology and Manuacturing communities. ISQED spans three days, Monday through Wednesday, in three parallel tracks, hosting ove

100 technical presentations, several keynote speakers, panel discussions, workshops/tutorials and other inormal meetings. Conerence proceeding

CDs are published by IEEE and posted in the IEEE Xplore digital library.

A pioneer and leading multidisciplinary conerence, ISQED accepts and promotes papers related to the manuacturing, design and EDA. Authors are invited to submi

papers in the various discipl ines o high level design, circuit design (digital, analog, mixed-signal, RF), test & verifcation, design automation tools; processes; ows, device

modeling, semiconductor technology, advance packaging, and biomedical & bioelectronic devices. The details o various topics o paper submission are as ollows:

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submissionoF PaPersPaper submission must be done on-line through the conerence web site at www.isqed.org. The guidelines or the fnal paper ormat are provided

on the conerence web site . Authors should submit FULL-LENGTH, original, unpublished papers (Minimum 4, maximum 8 pages) along with an

abstract o about 200 words. To permit a blind review, do not include name(s) or afliation(s) o the author(s) on the manuscript and abstract. The

complete contact author inormation needs to be entered separately. Please check the as-printed appearance o your paper beore sending you

paper. In case o any problems email isqed2012@isqed.org. Please note the ollowing important dates:

EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse (EDA)EDA tools addressing design or manuacturing, yield, and reliability. Management o design process, design ows and design databases. EDA tool

interoperability issues and implications. Eect o emerging technologies, processes & devices on design ows, tools, and tool interoperability. Emer

ging EDA standards. EDA design methodologies and tools that address issues which impact the quality o the realization o designs into physica

integrated circuits. IP modeling and abstraction. Design and maintenance o technology independent hard and sot IP blocks. Methods and tool

or analysis, comparison and qualifcation o libraries and hard IP blocks. Challenges and solutions o the integration, testing, qualiying, and manu

acturing o IP blocks rom multiple vendors. Third party testing o IP blocks. Risk management o IP reuse. IP authoring tools and methodologies

Emerging/Innovative Process & Device Technologies and Design Issues (EDT)

Emerging processes & device technologies and implications on IC design with respect to designs time to market, yield, reliability, and qualityEmerging issues in DSM CMOS: e.g. sub-threshold leakage, gate leakage, technology road mapping and technology extrapolation techniques. New

and novel technologies such as SOI, Double-Gate (DG)-MOSFET, Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth

metallization, 3D integrated circuits, nanoelectronic, biomedical & bioelectronic devices, etc.

Advanced IC Package - Design Interactions & Co-Design (PDI)Concurrent circuit, package, and PCB/PWB design and eect on quality. EDA tools and methodologies dealing with the IC Packaging electrical and

thermal modeling and simulation or improved quality o product. SoC versus system in a package (SiP): design and technology solutions and

tradeos; MCM, BGA, Flip Chip, 3D, TSV, and other innovative packaging techniques or various applications such as mixed-signal and RFIC.

Design o Reliable Circuits and Systems (DFR)Device and process reliability issues and eect on design o reliable circuits and systems. ESD design or digital, mixed signal and RF applications

Exploration o critical actors such as noise, substrate coupling, cross-talk and power supply noise. Signifcance and trends in process reliability

eects such as gate oxide integrity, electromigration, ESD, etc., and their relation to electronic design.

www.isqed.org

Paper Submission Deadline

Acceptance Notifications

Final Camera-Ready paper

Oct. 12, 2011

November 26, 2011

January 10, 2012

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nternationalSocietyfor

QualityElectronicDesign

POBox607

LosAltos,CA94023

www.isqed.org March19-21,2012

CallforPapers,ISQED2012

ISQED-LeadingDesignforManufacturingandQualityTM