Chapter 6 FPGA Modules and Hardware Interface Design Professor Tzyy-Kuen Tien E-mail: [email protected] Http:

Chapter 6Chapter 6

FPGA Modules and Hardware FPGA Modules and Hardware Interface DesignInterface Design

Professor Tzyy-Kuen TienProfessor Tzyy-Kuen TienE-mail: [email protected]: [email protected]

Http://www.eecs.stut.edu.twHttp://www.eecs.stut.edu.twSTUT/EESTUT/EE

P-2/93教育部顧問室 PAL聯盟 /系統雛型與軟硬體整合設計

第六章： FPGA模組與硬體介面設計

OutlineOutline6.1 The Implementation of IDCT on FPGA6.1 The Implementation of IDCT on FPGA

6.2 AMBA I/O Interface Design6.2 AMBA I/O Interface Design

6.3 I/O Interface Design6.3 I/O Interface Design



6.1 The Implementation of IDCT on 6.1 The Implementation of IDCT on FPGAFPGA

6.16.1 The Implementation of IDCT on FPGAThe Implementation of IDCT on FPGA





6.1 Compression/Decompression 6.1 Compression/Decompression SystemSystem

A block diagram of a compression/decompression system.

DCT/IDCT can be used in the system to reduce the bandwidth requirements.

SourceCoder

ChannelCoder

SourceDecoder

ChannelDecoder

Decoder

EncoderInput Signal

ReconstructedOutput Signal



6.1 Introduction to IDCT6.1 Introduction to IDCT Inverse Discrete Cosine Transform.

IDCT is used to decompress DCT compressed data in the decoder.

IDCT is one of the most computation-intensive parts of the MPEG decoding process.

A fast, hardware based IDCT implementation is crucial to speed the MPEG decoding process.



6.1 2D IDCT Equations (1/2)6.1 2D IDCT Equations (1/2) The algorithm used for the calculation of the 2D

IDCT coefficients is based on the following equation:

First, the 1D DCT of the rows are calculated and then the 1D IDCT of the columns are calculated.

XCpq = ∑ ∑ XNmn · M-1 N-1

m = 0 n = 0

c(p)c(q)

4·cos

Π(2m+1)p

2M·cos

Π(2n+1)q

2N(EQ 1)



6.1 2D IDCT Equations (2/2)6.1 2D IDCT Equations (2/2) The 1D IDCT coefficients for the rows and

columns can be calculated by separating equation 1 into the row part and the column part.

C = K · cos(2·col number + 1) · row number ·Π

2 · M

K = √1

N for row = 0,

√2 K =

N for row ≠ 0

Ct = K · cos(2·row number + 1) · col number ·Π

2 · N

K = √1

M for col = 0, K =

√2 for col ≠ 0

M

(EQ 2)

(EQ 3)

M = total number of columns, N = total number of rows.



6.1 Constant Values of C and 6.1 Constant Values of C and CCtt

The constant values for C and Ct calculated from equations 2 and 3 are as follows:

23170 23170 23170 23170 23170 23170 23170 2317032138 27246 18205 6393 –6393 –18205 –27246 –3213830274 12540 –12540 –30274 –30274 –12540 12540 3027427246 –6393 –32138 –18205 18205 32138 6393 –2724623170 –23170 –23170 23170 23170 –23170 –23170 2317018205 –32138 6393 27246 –27246 –6393 32138 –1820512540 –30274 30274 –12540 –12540 30274 –30274 125406393 –18205 27246 –32138 32138 –27246 18205 –6393

C =

Ct =

23170 32138 30274 27246 23170 18205 12540 639323170 27246 12540 –6393 –23170 –32138 –30274 –1820523170 18205 –12540 –32138 –23170 6393 30274 2724623170 6393 –30274 –18205 23170 27246 –12540 –3213823170 –6393 –30274 18205 23170 –27246 –12540 3213823170 –18205 –12540 32138 –23170 –6393 30274 –2724623170 –27246 12540 6393 –23170 32138 –30274 1820523170 –32138 30274 –27246 23170 –18205 12540 –6393



6.1 2D IDCT using Vector 6.1 2D IDCT using Vector ProcessingProcessing

A one-dimensional 8-point IDCT followed by an internal double buffer memory, followed by another one-dimensional 8-point IDCT provides the 2D IDCT architecture.

Vector processing using parallel multipliers is a method used for implementation of IDCT.

Advantages of vector processing method. Regular structure, simple control and

interconnect, good balance between performance and complexity of implementation.

1D IDCTRAM Double

Buffer1D IDCT



6.1 Behavioral Model (1/2)6.1 Behavioral Model (1/2) The output Y of an 8‧8 IDCT for input X is given by Y = C

‧X‧Ct, where C is the cosine coefficients and Ct is the transpose coefficients.

The equation can also be written as Y = Ct‧Z, where Z = X‧C.

X =

x00 x01 x02 x03 x04 x05 x06 x07x10 x11 x12 x13 x14 x15 x16 x17x20 x21 x22 x23 x24 x25 x26 x27x30 x31 x32 x33 x34 x35 x36 x37x40 x41 x42 x43 x44 x45 x46 x47x50 x51 x52 x53 x54 x55 x56 x57x60 x61 x62 x63 x64 x65 x66 x67x70 x71 x72 x73 x74 x75 x76 x77

C =

23170 23170 23170 23170 23170 23170 23170 2317032138 27246 18205 6393 –6393 –18205 –27246 –3213830274 12540 –12540 –30274 –30274 –12540 12540 3027427246 –6393 –32138 –18205 18205 32138 6393 –2724623170 –23170 –23170 23170 23170 –23170 –23170 2317018205 –32138 6393 27246 –27246 –6393 32138 –1820512540 –30274 30274 –12540 –12540 30274 –30274 125406393 –18205 27246 –32138 32138 –27246 18205 –6393



6.1 Behavioral Model (2/2)6.1 Behavioral Model (2/2)Z(0,0) = 23170x00 + 32138x01 + 30274x02 + 27246x03 + 23170x04 + 18205x05 + 12540x06 + 6393x07Z(0,1) = 23170x00 + 27246x01 + 12540x02 – 6393x03 – 23170x04 – 3213805 – 30274x06 – 18205x07Z(0,2) = 23170x00 + 18205x01 – 12540x02 – 32138x03 – 23170x04 + 6393x05 + 30274x06 + 27246x07Z(0,3) = 23170x00 + 6393x01 – 30274x02 – 18205x03 + 23170x04 + 27246x05 – 12540x06 – 3213807Z(0,4) = 23170x00 – 6393x01 – 30274x02 + 18205x03 + 23170x04 – 27246x05 – 12540x06 + 32138x07Z(0,5) = 23170x00 – 18205x01 – 12540x02 + 32138x03 – 23170x04 – 6393x05 + 30274x06 – 27246x07Z(0,6) = 23170x00 – 27246x01 + 12540x02 + 6393x03 – 23170x04 + 32138x05 – 30274x06 + 18205x07Z(0,7) = 23170x00 – 32138x01 + 30274x02 – 27246x03 + 23170x04 – 18205x05 + 12540x06 – 6393x07

Or:Z(k,0) = (23170xk0 + 30274xk2 + 23170xk4 + 12540xk6) + (32138xk1 + 27246xk3 + 18205xk5 + 6393xk7) = P01 + P02Z(k,1) = (23170xk0 + 12540xk2 – 23170xk4 – 30274xk6) + (27246xk1 – 6393xk3 – 32138xk5 – 18205xk7) = P11 + P12Z(k,2) = (23170xk0 – 12540xk2 – 23170xk4 + 30274xk6) + (18205xk1 – 32138xk3 + 6393xk5 + 27246xk7) = P21 + P22Z(k,3) = (23170xk0 – 30274xk2 + 23170xk4 – 12540xk6) + (6393xk1 – 18205xk3 + 27246xk5 – 32138xk7) = P31 + P32Z(k,4) = P31 – P32Z(k,5) = P21 – P22Z(k,6) = P11 – P12Z(k,7) = P01 – P02where k = 0, 2, …, 7



6.1 1D IDCT6.1 1D IDCT The block diagram for the implementation of the

1D IDCT is shown below.

Shift

Regist

23170 23170 23170 23170 23170 23170 23170 23170

32138 27246 18205 6393 -6393 -18205 -27246 -32138

30274 12540 -12540 -30274 -30274 -12540 12540 30274

27246 -6393 -32138 -18205 18205 32138 6393 -27246

23170 -23170 -23170 23170 23170 -23170 -23170 23170

18205 -32138 6393 27246 -27246 -6393 32138 -18205

12540 -30274 30274 -12540 -12540 30274 -30274 12540

6393 -18205 27246 -32138 32138 -27246 18205 -6393

Adder

×

×

×

×

×

×

×

××K7

×K6

×K5

×K4

×K3

×K2

×K1

×K0

×IN

ZK(0 to 7)



6.2 AMBA I/O Interface Design6.2 AMBA I/O Interface Design6.1 The Implementation of IDCT on FPGA6.1 The Implementation of IDCT on FPGA

6.26.2 AMBA I/O Interface DesignAMBA I/O Interface Design




6.2 AMBA I/O Interface Design6.2 AMBA I/O Interface Design Introduction to the AMBA busesIntroduction to the AMBA buses AMBA AHB busAMBA AHB bus AMBA ASB busAMBA ASB bus AMBA APB busAMBA APB bus



6.2 6.2 IntroductionIntroduction (1/5) (1/5) What is AMBA?

The Advanced Microcontroller Bus Architecture specification.

An on-chip communication standard for designing high-performance embedded microcontroller.

Three distinct buses. AHB (the Advanced High-performance Bus).

High-performance system backbone bus. ASB (the Advanced System Bus).

An alternative system bus. APB (the Advanced Peripheral Bus).

Minimal power consumption.Reduced interface complexity.



6.2 6.2 Introduction Introduction (2/5)(2/5) Objectives of the AMBA specification.

To facilitate the right-first-time development of embedded microcontroller products.

To be technology-independent. To ensure that highly reusable peripheral and

system. macrocells can be migrated across a diverse range of IC processes.

To encourage modular system design. To minimize the silicon infrastructure required

for both operation and manufacturing test.



6.2 6.2 IntroductionIntroduction (3/5) (3/5) Typical AMBA system.

High-bandwidthExternal Memory

Interface

High-bandwidthOn-chip RAM

High-performanceARM-processor

DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge



6.2 6.2 IntroductionIntroduction (4/5) (4/5)

　 AMBA AHB AMBA ASB AMBA APB

Feature High performance High performance Low power

　 Pipelined operation Pipelined operation Latched address and control

　 Multiple bus masters Multiple bus masters Simple interface

　 Burst transfers Burst transfersSuitable for many peripherals

　 Split transactionsDual-clock edge operation

Single-clock edge operation (rising edge)

　 Single-cycle bus master handover

　　

　 Single-clock edge operation (rising edge)

　　

　 Wider data bus configuration

　　

Components AHB master ASB masterAPB bridge (slave on AHB or ASB)

　 AHB slave ASB slave APB slave

　 AHB arbiter ASB arbiter 　

　 AHB decoder ASB decoder 　

Feature



6.2 6.2 IntroductionIntroduction (5/5) (5/5) When to use AMBA AHB/ASB or APB.

A full AHB or ASB. Bus masters. On-chip memory blocks. External memory interface. High-bandwidth peripherals with FIFO

interfaces. DMA slave peripherals.

A simple APB interface. Simple register-mapped slave devices. Very low power interfaces where clocks

cannot be globally routed. Grouping narrow-bus peripherals to avoid

loading the system bus.






6.2 A Typical 6.2 A Typical AA HB and APB SystemHB and APB System

High-bandwidthMemory Interface

High-bandwidthon-chip RAM


DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge

AMBA Advanced High-performance Bus (AHB)

*High performance

*Pipelined operation

*Burst transfers

*Multiple bus masters

*Split transactions

AMBA Advanced Peripheral Bus (APB)

*Low power

*Latched address and control

*Simple interface

*Suitable for many peripherals



6.2 6.2 AMBA AHB AMBA AHB Bus InterconnectBus Interconnect Multiplexor interconnection.

Master#1

Arbiter

Master#2

Master#3

Slave#2

Slave#3

Slave#4

Slave#1

Decoder

HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

Address andcontrol mux

Write data muxRead data mux



6.2 6.2 AMBA AHB AMBA AHB Transfer TypeTransfer Type Transfer type encoding.

HTRANS[1:0] 00 – IDLE

No data transfer is required. 01 – BUSY

Bus masters insert IDLE cycles in the middle of bursts of transfers.

10 – NONSEQThe first transfer of a burst or a single transfer is

initiated. 11 – SEQ

The remaining transfers are in a burst.The address is related to the previous transfer.



6.2 Slave Transfer Responses6.2 Slave Transfer Responses Response encoding.

HRESP[1:0] 00 – OKAY. 01 – ERROR. 10 – RETRY.

The signal shows the transfer has not yet completed, so the bus master should retry the transfer.

11 – SPLITThe slave will request access to the bus on

behalf of the master when the transfer can complete.

If the response is the one among ERROR, RETRY and SPLIT, a two-cycle response is required.



6.2 6.2 AMBA AHB AMBA AHB BBusus Arbitration Arbitration Bus master grant signals.

The HGRANTx signal is only used by the master to determine when it owns the bus.

DecoderMaster

#1

Master

#2

Master

#3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[31:0]

HADDR_M2[31:0]

HADDR_M3[31:0]

HADDR to all slaves

HMASTER[3:0]

Address and Control

multiplex

Arbiter



6.2 AMBA AHB Bus Slave6.2 AMBA AHB Bus Slave AHB bus slave interface.

AHBslave

Split-capableslave

HSELx

HADDR[31:0]

HWRITE

HTRANS[1:0]

HSIZE[2:0]

HBURST[2:0]

HWDATA[31:0]

HRESETn

HCLK

HMASTER[3:0]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[31:0]

HREADY

HRESP[1:0]

HSPLITx[15:0]

Data

Transferresponse



6.2 AMBA AHB Bus Master6.2 AMBA AHB Bus Master AHB bus master interface.

AHBmaster

HGRANTx

HREADY

HRESP[1:0]

HRESETn

HCLK

HRDATA[31:0]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[1:0]

HADDR[31:0]

HWRITE

HSIZE[2:0]

HBURST[2:0]

HPROT[3:0]

HWDATA[31:0]

Arbiter

Transfer type

Addressandcontrol

Data



6.2 AMBA AHB Arbiter6.2 AMBA AHB Arbiter AHB arbiter interface.

AHBarbiter

HBUSREQx1

HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[31:0]

HSPLITx[15:0]

HTRANS[1:0]

HBURST[2:0]

HRESP[1:0]

HRESETn

HCLK

Arbiterrequests

and locks

Addressand control

Reset

Clock

HGRANTx1

HGRANTx2

HGRANTx3

HMASTER[3:0]

HMASTLOCK

Arbitergrants

HREADY






6.2 A Typical AMBA ASB-based 6.2 A Typical AMBA ASB-based MicrocontrollerMicrocontroller

A typical AMBA system.




DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge

AMBA Advanced System Bus (ASB)

*High performance

*Pipelined operation

*Burst transfers

*Multiple bus masters


*Low power


*Simple interface




6.2 AMBA ASB Description6.2 AMBA ASB Description Basic flow of the bus operation.

The arbiter determines which master is granted access to the bus.

When granted, a master initiates transfers on the bus.

The decoder uses the high order address lines to select a bus slave.

The slave provides a transfer response back lines to the bus master and data is transferred between the master and slave.



6.2 ASB Transfers6.2 ASB Transfers Three types of transfer.

NONSEQUENTIALUsed for signal transfers or the first

transfer of a burst. SEQUENTIAL

Used for transfers in a burst. The address of a SEQUENTIAL transfer is always related to the previous transfer.

ADDRESS-ONLYUsed when no data movement is required.



6.2 AMBA ASB Bus Slave6.2 AMBA ASB Bus Slave ASB bus slave interface.

ASBslave

DSELSelect

BA[31:0]

BWRITE

BSIZE[1:0]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[31:0]

Transfer response

Data



6.2 AMBS ASB Bus Master6.2 AMBS ASB Bus Master ASB bus master interface.

ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[1:0]

BA[31:0]

BWRITE

BSIZE[1:0]

BPROT[1:0]

BD[31:0]

Arbiter

Transfer type

Addressandcontrol

Data



6.2 AMBA ASB Bus Decoder6.2 AMBA ASB Bus Decoder ASB decoder interface.

ASBdecoder

BTRAN[1:0]

BA[31:0]

BWRITE

BSIZE[1:0]

BPROT[1:0]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1

DSEL1…..

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



6.2 AMBA ASB Bus Arbiter6.2 AMBA ASB Bus Arbiter ASB arbiter interface.

ASBarbiter

AREQx1

AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1

AGNTx2

AGNTx3

Arbitergrants



6.26.2 AMBA I/O Interface DesignAMBA I/O Interface Design Introduction to the AMBA busesIntroduction to the AMBA buses AMBA AHB busAMBA AHB bus AMBA ASB busAMBA ASB bus AMBA APB busAMBA APB bus



6.2 A Typical AMBA-based Microcontrolle6.2 A Typical AMBA-based Microcontrollerr AMBA Advanced Peripheral Bus (APB).




DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


*Low power


*Simple interface




6.2 Avtivity of the Peripheral Bus6.2 Avtivity of the Peripheral Bus State diagram.

IDLE The default state for the peripheral

bus. SETUP

The bus moves into this state when a transfer is required.

The bus remains in the SETUP state for one clock and will always move to the ENABLE state.

PSELx is asserted. ENABLE

PENABLE is asserted. The address, write and select signals

all remain stable during SETUPENABLE.

Glitch is acceptable during ENABLESETUP.

IDLEPSELx = 0

PENABLE = 0

SETUPPSELx = 1

PENABLE = 0

ENABLEPSELx = 1

PENABLE = 1

No transfer

Transfer

TransferNo transfer



6.2 6.2 AMBA APB AMBA APB Interface DesignInterface Design APB bridge interface.

APBslave

PRDATA

PSEL1

PSEL2

PSELn

.

.

.

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data

System busslave interface

PRDATARead data

PRESETn

PCLKReset

Clock



6.2 6.2 AMBA APB AMBA APB SlaveSlave APB slave interface.

APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



6.3 I/O Interface Design6.3 I/O Interface Design6.1 The Implementation of IDCT on FPGA6.1 The Implementation of IDCT on FPGA





6.3 I/O Interface6.3 I/O Interface Provides a method for transferring information

between CPU (or internal storage) and external I/O devices.

I/O devices connected to a computer need special communication links for interfacing them with the CPU.



6.3 Purposes of the 6.3 Purposes of the Communication LinkCommunication Link

Conversion of signal values. The manner of operation for an I/O device

may be different from the operation of the CPU.

Providing a synchronization mechanism. The data transfer rate of I/O devices is

usually slower than the transfer rate of the CPU.

Word format transformation. Data codes and formats in I/O differ from the

word format in the CPU. The control of I/O devices.

To ensure the operation of an I/O device is not disturbed by another I/O devices.



6.3 I/O Bus and Interface 6.3 I/O Bus and Interface ModulesModules

The I/O bus consists of data lines, address lines, and control lines.

Processor

Data

AddressControl

Processor Interface Interface Interface

Keyboardand

displayterminal

Printer Magneticdisk

Magnetictape



6.3 I/O versus Memory Bus6.3 I/O versus Memory Bus There are three ways that computer buses can

be used to communicate with memory and I/O: Use two separate buses, one for memory and

the other for I/O. Use one common bus for both memory and

I/O but have separate control lines for each. Use one common bus for memory and I/O with

common control lines.



6.3 Isolated versus Memory-6.3 Isolated versus Memory-Mapped I/OMapped I/O

Isolated I/O. Isolate all I/O interface addresses from the

addresses assigned to memory. Distinct input and output instructions for I/O

transfer. Memory-mapped I/O.

Use the same address space for both memory and I/O.

No specific input or output instructions. The CPU manipulates I/O data with the same

instructions that are used to manipulate memory words.



6.3 Example of I/O Interface6.3 Example of I/O Interface

Busbuffers

Bidirectional

data bus

Port Aregister

Port Bregister

Controlregister

Statusregister

CS

RS1

RS0

RD

WR

Timingand

control

Inte

rnal

bus

Chip select

Register select

I/O read

I/O write

I/O data

I/O data

Control

Status

To I/O deviceTo CPU

CS RS1 RS0 Register selected

0 X X None: data bus in high-impedance

1 0 0 Port A register

1 0 1 Port B register 1 1 0 Control register

1 1 1 Status register



6.3 Asynchronous Data 6.3 Asynchronous Data TransferTransfer

Asynchronous data transfer between two independent units requires control signals to transmit data.

Two different types of control mechanism for data transferring between two independent units . Strobe control. Handshaking.



6.3 Strobe Control (1/3)6.3 Strobe Control (1/3) The strobe control method employs a single

control line to time each transfer.

The strobe may be activated by either the source or the destination.



Source-initiated strobe for data transfer.

6.3 Strobe Control (2/3)6.3 Strobe Control (2/3)

Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram



Destination-initiated strobe for data transfer.

6.3 Strobe Control (3/3)6.3 Strobe Control (3/3)

Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram



6.3 Problem of Strobe Method6.3 Problem of Strobe Method The disadvantage of the strobe method is that

the source (destination) unit that initiates the transfer has no way of knowing whether the destination (source) unit has actually received the data item that was placed in the bus.



6.3 Handshaking6.3 Handshaking The basic principle of the two-wire handshaking

method of data transfer is as follows. One control line from the source unit is used

to inform the destination whether there are valid data in the bus.

The other control line from the destination unit is used to inform the source whether it can accept data.



6.3 Data Transfer by 6.3 Data Transfer by Handshaking (1/2)Handshaking (1/2)

Data transfer procedure initiated by the source.

Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted

Place data on bus.Enable data valid.

Disable data valid.Invalidate data on bus.

Accept data from bus.Enable data accepted.

Disable data accepted.Ready to accept data

(initial state).

(c) Sequence of events

Source unit Destination unit



6.3 Data Transfer by 6.3 Data Transfer by Handshaking (2/2)Handshaking (2/2)

Data transfer procedure initiated by the destination.

Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus

Place data on bus.Enable data valid.

Disable data valid.Invalidate data on bus

(initial state).

Ready to accept data.Enable ready for data.

Accept data from bus.Disable ready for data.

(c) Sequence of events

Source unit

Destination unit



6.3 Asynchronous Serial 6.3 Asynchronous Serial TransferTransfer

A serial asynchronous data transmission technique employs special bits that are inserted at both ends of the character code.

With this technique, each character consists of three parts: A start bit. The character bits. Stop bits.

1 1 1 10 0 0 0

Startbit

Character bits Stopbits



6.3 Asynchronous Communication 6.3 Asynchronous Communication InterfaceInterface

CS RS

0 X

Operation Register selected

X None ： data bus in high-impedance1 0 WR Transmitter register1 1 WR Control register1 0 RD Receiver register1 1 RD Status register

Busbuffer

Bidirectional

data bus

CS

RS

Chip select

Register select

RDI/O read

WRI/O write

Timingand

control

Inter

nal b

us

Transmitterregister

Shiftregister

Transmitdata

Controlregister

Transmittercontrol

and clock

Transmitterclock

Statusregister

Receivercontrol

and clock

Receiverclock

Receiverregister

Shiftregister

Receivedata



6.3 Modes of Transfer6.3 Modes of Transfer Data transfer to and from I/O devices may be

handled in one of three possible modes. Programmed I/O. Interrupt-initiated I/O. Direct memory access (DMA).



6.3 Programmed I/O6.3 Programmed I/O Programmed I/O operations are the result of I/O

instructions written in the computer program. Each data item transfer is initiated by an

instruction in the program. Transferring data under program control

requires constant monitoring of the I/O by the CPU.

The I/O device does not have direct access to memory.



6.3 Example of Programmed 6.3 Example of Programmed I/OI/O

The steps of data transfer. I/O device places data to the I/O bus and

enables the data valid line. The interface accepts the data into its

register and enables the data accepted line. The interface sets a bit of flag “F”. The CPU reads the data from the interface

according to flag “F”.

CPU

InterfaceData bus

Address bus

I/O read

I/O write

Data register

Statusregister

F

F = Flag bit

I/Odevice

I/O bus

Data valid

Data accepted



6.3 Flowchart for CPU Reads Data 6.3 Flowchart for CPU Reads Data From I/OFrom I/O

Read data register

Check flag bit

Flag

Read status register

Transfer data to memory

OperationComplete?

Continuewith

program

= 0

= 1

yes

no



6.3 Interrupt-Initiated I/O6.3 Interrupt-Initiated I/O Instead of constantly monitoring the flag, the

CPU is informed to receive data when an interrupt signal happens from the interface.

The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer.



6.3 Priority Interrupt6.3 Priority Interrupt The system establishes a priority over the

various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously .

Two methods of priority interrupt. Software priority-interrupt.

A polling procedure. Hardware priority-interrupt.

Daisy-chaining priority.Parallel priority-interrupt.



6.3 Daisy-Chain Priority 6.3 Daisy-Chain Priority InterruptInterrupt

Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request

Interrupt acknowledge

Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request

Interrupt acknowledge

Processor data bus



6.3 Parallel Priority-Interrupt6.3 Parallel Priority-Interrupt

0

1

2

3

Interruptregister

Disk

Printer

Reader

Keyboard

0

1

2

3

Maskregister

I0

I1

I2

I3

Priorityencoder

y

x

0

0

0

0

0

0

IEN IST

Enable

Interruptto CPU

INTACKfrom CPU

VADto CPU



6.3 DMA6.3 DMA Removing the CPU from the path and letting the

I/O devices manage the memory directly. During DMA transfer, the CPU is idle and has no

control of the memory buses. Two signals are used to facilitate the DMA

transfer. Bus request: a signal from DMA controller. Bus grant: the CPU informs the DMA that the

buses are in high-impedance state.

BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write

High-impedance(disable)when BG isenable



6.3 DMA Controller6.3 DMA Controller Block diagram of DMA controller.

Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant

InterruptDMA request

DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to I/O device



6.3 Initialization of DMA6.3 Initialization of DMA The CPU initializes the DMA by sending the

following information through the data bus. Starting address of the memory block. Word count. Mode of transfer. A start signal to do DMA transfer.



6.3 DMA Transfer6.3 DMA Transfer

CPU

WR Address DataRD

Random-accessmemory (RAM)

WR Address DataRD

Direct memoryaccess (DMA)

controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control

Write controlData bus

Address bus

Interrupt

BG

BR

I/OPeripheral

device

DMA acknowledge

DMA request



ReferencesReferences http://www.xilinx.com/bvdocs/appnotes/xapp611.pdf http://www.arm.com/products/solutions/AMBA_Spec.h

tml Mano, M. Morris, “Computer system architecture,” Pr

entice Hall,1993.

Documents

Chapter 6 FPGA Modules and Hardware Interface Design Professor Tzyy-Kuen Tien E-mail: [email protected] Http: