Clock Jitter and Excess Loop Delay in

Continuous-Time Delta-Sigma Modulators

ECE1352F Prof. Phang

November 15, 2002

Trevor Caldwell

981708360

2

Table of Contents Description Page Title Page 1

Table of Contents 2

Abstract 3

1.0 Introduction 4

2.0 Background 6

2.1 Delta-Sigma Modulation 6

2.2 Comparison 8

2.3 Continuous-Time and Discrete-Time Equivalence 9

2.4 Typical Example of a CT ∆Σ modulator 10

3.0 Non-Idealities 12

3.1 Clock Jitter 12

3.2 Excess Loop Delay 14

4.0 Solutions 18

4.1 SC-R Feedback 18

4.2 Compensation Solution 20

5.0 Future Considerations 22

6.0 Conclusion 23

References 24

3

Abstract

Continuous-time ∆Σ modulators are able to operate at higher frequencies than

their discrete-time counterparts. However, they suffer more severely from non-idealities

such as clock jitter and excess loop delay. The effects of these two non-idealities are

explained and a continuous-time to discrete-time conversion method is presented in order

to aid in the analysis of these non-idealities. Two circuits are presented that alleviate

these problems: the SC-R feedback circuit helps eliminate clock jitter noise while the

compensation solution lessens the effects of excess loop delay.

4

1.0 Introduction

Oversampled delta-sigma ( ∆Σ ) modulators provide a relatively low cost means of

converting an analog signal to a digital signal while obtaining high dynamic range and

excellent linearity with the use of a 1-bit quantizer [1]. Most often these converters

operate with the use of discrete-time topologies. However, due to the fact that they

oversample the data in order to achieve a high signal to quantization noise ratio (SQNR),

and hence signal to noise ratio (SNR), the input bandwidth is limited by the speed at

which the filter sampler can operate. The sampler must operate at a speed much greater

than the bandwidth of the input signal, since it must oversample the data. Using standard

technology, the sampling frequency of the modulator is limited to about 50 MHz [2].

This limits the bandwidth of the input signal to between 50 kHz and a few MHz.

The use of continuous-time filters provides some improvements. Their advantage

lies in the fact that they do not operate at a given sampling frequency since no sampling

is performed within the filter, so the restriction of the maximum sampling frequency is

only imposed on the sampler within the quantizer. Recently studied continuous-time

(CT) ∆Σ modulators have been found to operate between 10MHz and a few GHz [2].

CT ∆Σ modulators also remove the need for an anti-aliasing filter on the input [3]. The

drawback is that the continuous-time filters are much more difficult to design and

simulate [2] than discrete-time filters since discrete-time filters are simply made up of

delays and gain stages in various loops. Another disadvantage of CT ∆Σ modulators is

that they exhibit several non-idealities from the continuous-time filters, such as clock

jitter and excess loop delay [4,5].

5

The following paper will concentrate on the two main non-idealities of CT ∆Σ

modulators, namely clock jitter and excess loop delay. The negative effects of these non-

idealities will be explained, and solutions to minimize the effects will be presented.

Section 2 will provide some background information on both discrete-time and

continuous-time ∆Σ modulators. Section 3 will explain the effects of clock jitter and

excess loop delay on CT ∆Σ modulators. Section 4 will provide a solution for the clock

jitter and excess loop delay, while Section 5 will discuss some future issues to consider.

Section 6 will summarize the discussion.

6

2.0 Background

This section will provide some basic information on delta-sigma modulation, a

comparison between CT and DT ∆Σ modulators, and a method of equivocating

continuous-time and discrete-time filters.

2.1 Delta-Sigma Modulation

Oversampled ∆Σ modulators offer an efficient means of converting an analog

signal to a digital signal while achieving high dynamic range and linearity with a 1-bit

quantizer [1]. A block diagram of a first-order low-pass ∆Σ modulator is shown in

Figure 1. The input signal x[n] (or )(txc in the continuous-time case) passes through the

summing junction, then through the integrator to the 1-bit quantizer (which is essentially

a comparator) where the output y[n] is either +/- 1. The feedback forces the average of

the output y[n] to be equal to x[n]. Note that the digital-to-analog converter (D/A or

DAC) in the feedback path can be eliminated in a DT ∆Σ modulator since the output y[n]

and the input x[n] are both discrete-time signals. A digital low-pass filter will generally

follow the ∆Σ modulators on the output in order to attenuate signals outside the

frequency band of interest, where most of the noise is concentrated.

Figure 1 A block diagram of the 1st order ∆Σ modulator.

A second-order low-pass ∆Σ modulator is shown in Figure 2. The basic operation of the

modulator is the same, as the average of the output y[n] will be equal to x[n].

7

Figure 2 A block diagram of the 2nd order ∆Σ modulator.

The output spectrum of a signal after passing through a ∆Σ modulator will

contain the original signal as well as some shaped quantization noise. This quantization

noise will be low in the bandwidth of interest, and it will rise as the frequency increases

beyond the bandwidth of interest (Figure 3). This shaped quantization noise is what

allows a ∆Σ modulator to have a high SQNR (up to 20 bits have been reported [1]),

given that it only uses a 1-bit quantizer.

Figure 3 Output frequency spectrum of a ∆Σ modulator.

The ∆Σ modulator has both a signal transfer function (STF) and a noise transfer

function (NTF). The signal transfer function of a ∆Σ modulator (which is )(1

)(

zH

zH

+ in

the first-order discrete-time case) is ideally designed to pass the signal through with no

change, or perhaps a delay. The noise transfer function ()(1

1

zH+ in the discrete-time

case) affects noise introduced at the quantizer and is generally a high-pass filter designed

to shape the quantization noise. As the order of the modulator increases, the signals

filtered by the noise transfer function become less dominant in the frequency band of

8

interest, and the shaped quantization noise has a shaper rise/fall. Figure 3 illustrates the

high-pass characteristic of the noise, where the signal is allowed to propagate through the

∆Σ modulator with little change, while the noise is almost removed from the frequency

band of interest.

2.2 Comparison

An illustration of a first-order DT ∆Σ modulator is shown in Figure 4, while a

first-order CT ∆Σ modulator is shown in Figure 5. The difference between the two

modulators is that the input of the CT ∆Σ modulator is a time-varying signal )(txc ,

while the input to the discrete-time filter is a series of sampled points of the input signal,

according to the equation )()(][ txnTxnx cc == . Also, the quantizer in the continuous-

time ∆Σ modulator samples the signal (the sampling is illustrated as occurring before the

quantizer in Figure 5 for an understanding of the operation). Furthermore, the CT ∆Σ

modulator has the need for a 1-bit DAC in the feedback path since the signal entering the

summer is supposed to be continuous-time. Therefore the discrete-time signal being fed

back must be converted with a simple first-order hold operating at T. This DAC can also

exhibit different pulse shapes such as Return to Zero (RZ) or Non-Return to Zero (NRZ),

depending on the length of the pulse.

Figure 4 1st order discrete-time ∆Σ modulator.

9

Figure 5 1st order continuous-time ∆Σ modulator.

2.3 Continuous-Time and Discrete-Time Equivalence

An equivalence between the discrete-time and continuous-time loop filter is

necessary to analyze the nature of the continuous-time filter. Due to the difficulty in

simulating continuous-time filters, finding an equivalent discrete-time filter and

analyzing it is a much simpler way of determining the properties of the continuous-time

filter. The reason that this equivalence exists is because the quantizer in the CT ∆Σ

modulator is clocked, meaning that an implicit sampling action occurs inside the

quantizer [5]. Sampled circuits are discrete-time circuits, and thus an explicit sampler

before the quantizer (as shown in Figure 5) does not change the behaviour of the

modulator, but it allows an equivalence to be drawn between the continuous-time and

discrete-time filter.

In order to determine the equivalence, it is instructive to zero the inputs and open

the loop of the ∆Σ modulator around the quantizer. Figure 6a shows the open loop

around the quantizer for the discrete-time case, while Figure 6b shows the open loop

around the quantizer for the continuous-time case. A continuous-time modulator would

produce the same output bits as the discrete-time modulator if the outputs were equal at

the sampling instants, meaning that z[n]=z(nT) [5]. This would be satisfied if the

following condition were satisfied [6]:

10

{ }nTtsHsDACLZzH =− ⋅= )]()([)( 1 (1)

where DAC(s) is the transfer function of the DAC in Figure 6b, Z represents the Z-

transform, and 1−L represents the inverse Laplace transform. The DAC pulse can be

assumed to be a perfectly rectangular pulse of magnitude 1 that lasts from a to b [5].

Thus,

=,0

,1)(tDAC

otherwise

babta 10, ≤<≤<≤ (2)

and the s-domain equivalent for this is [5]

s

bsassDAC

)exp()exp()(

−−−= (3)

For a=0 and b=1, this becomes an NRZ DAC pulse. An RZ DAC pulse would exist if

a=0 and b=1/2. Equation (1) allows the transformation between continuous-time and

discrete-time filters, and thus allows an analysis of the effects of non-ideal DAC output

pulses to be performed on discrete-time equivalents of continuous-time filters.

Figure 6a Open loop for discrete-time modulator. Figure 6b Open loop for continuous-time modulator.

2.4 Typical Example of a CT ∆Σ modulator

A typical example of a differential low-pass second-order CT ∆Σ modulator that

can be clocked at speeds of up to a few GHz [7] is shown in Figure 7. Each stage

consists of a transconductor (which converts a voltage to a current) and an integrator

(which converts a current to a voltage) [7]. The output voltage from the quantizer, which

is a latched comparator, drives the differential pair, which acts as the feedback DAC [7].

11

Since the output of the differential pair as well as the output of the transconductors are

currents, these currents sum via Kirchoff’s current law (KCL) [5].

Figure 7 Implementation of 2nd order CT ∆Σ modulator [7].

The continuous-time loop transfer function can be found to be [7]

221

11

2

2

)(s

CC

gks

C

k

sH

m+= (4)

while the discrete-time equivalent can be found as [7]

22

21

212

1

22

)1(

22)(

−

−+

+

=z

T

C

kTC

gkzkT

C

gk

zH

mm

(5)

12

3.0 Non-Idealities

Clock jitter and excess loop delay will be explained and modeled in the following

sections.

3.1 Clock Jitter

Clock jitter is statistical variations of clock edges [8]. Two clocks are present in a

CT ∆Σ modulator and both can be affected by clock jitter. One of the clocks controls the

decision instant of the quantizer (or comparator) while the other clock controls the DAC

output. Since the output of the comparator is shaped by the noise transfer function (like

the quantization noise), the impact of this error will be relatively small. Conversely, the

output of the DAC is shaped by the signal transfer function since this signal adds to the

input signal, and thus the impact of this error will affect the passband noise in the ∆Σ

modulator [9].

There are two varieties of clock jitter, delay clock jitter and pulse-width clock

jitter. [4] demonstrates that in a second-order ∆Σ modulator, the delay clock jitter is

affected by one noise transfer function (like a high-pass discrete-filter of 11 −− z ) while

the pulse-width clock jitter manifests itself as white noise. This degrades the SNR of the

∆Σ modulator more severely since the white noise spreads evenly across the frequency

spectrum in Figure 3. Therefore the clock jitter discussed will be the pulse-width clock

jitter incurred in the DAC.

DT ∆Σ modulators are relatively insensitive to pulse-width clock jitter since they

utilize switched-capacitor circuits. The insensitivity is due to the sloping pulse form of

the feedback [8]. Since most of the charge transfer in a switched-capacitor circuit occurs

at the beginning of the clock period, clock jitter introduces a minimal amount of error in

13

the charge lost DQ∆ [10] (see Figure 8a). The capacitor is discharged over a switch with

very low on-resistance, thus reducing the value of RC=τ and causing a fairly steep

slope as the DAC discharges [10]. In contrast, CT ∆Σ modulators transfer charge at a

constant rate over the clock period (ideally), and thus the charge loss CQ∆ due to a

timing error is proportionally much greater than that of the DT ∆Σ modulator (see Figure

8b).

Figure 8a Clock jitter in discrete-time modulator. Figure 8b Clock jitter in continuous-time modulator.

Assuming white clock jitter, the sampling times of the output bits (for a sampling

period T) are given by tnTtn ∆+= where t∆ is an independent and identically

distributed random variable with variance 2t∆σ . The resulting noise power of the clock

jitter for a 1-bit quantizer with a step size of U and a typical RZ DAC pulse (a=0, b=1/2)

from [8] is

2

22

TOSR

UN t

jitter ⋅= ∆σ

(6)

The quantization noise power of a general Kth order ∆Σ modulator is [11]

)12(

22

)1224( ++=

K

K

quantizer OSRK

UN

π (7)

14

An figure of merit for the noise can be defined as the point at which the noise power of

the clock jitter is equal to the noise power of the quantization noise, thus reducing the

SNR by 3dB [8]. Equating (6) and (7), this critical value is found to be

K

Kt

OSRKT )1224( +=∆ πσ

(8)

This value decreases with increasing OSR, meaning that as the OSR increases the clock

jitter becomes more detrimental. Also, as the order of the modulator is increased, T

t∆σ

decreases, indicating that proportionally the clock jitter becomes more significant in

higher order CT ∆Σ modulators. A potential solution to this problem will be discussed

in Section 4.1.

3.2 Excess Loop Delay

Ideally DAC currents respond immediately to the quantizers clock edge, but the

non-zero transistor switching time of the latched comparator (quantizer) and the DAC

result in a finite delay between the comparator and the DAC [5]. This delay is called

Excess Loop Delay.

Excess loop delay can be modeled as Tt dd ⋅= ρ as depicted in Figure 9 for an

NRZ DAC pulse. dρ is dependent on the switching speed of the transistors tf , the

quantizer clock sf , the number of transistors in the feedback path tn , as well as the

loading on each transistor, and a rough approximation ist

std f

fn≈ρ [5]. In order to

quantify the results of this delay, a given discrete-time filter can be altered to account for

this delay.

15

Figure 9 Excess Loop Delay

A possible second-order low-pass DT ∆Σ modulator has a loop filter (determined

using the procedure in Figure 6) 2)1(

12)(

−+−=

z

zzH (note the similarity to equation (5)). To

convert this filter to a continuous-time equivalent, it must be broken into its partial

fractions.

2)1(

1

1

2)(

−−+

−−=

zzzH (9)

Using an appropriate table for the conversion from the z-domain to the s-domain (for

example Table II from [5]), the equivalent continuous-time loop filter can be written as

2222

5.115.012)(

sT

Ts

sT

Ts

TssH

+−=+−+−= (10)

where the transformations used were

Ts

ab

z

)(1

1

1 −→−

(11)

and ( )

222

)(1)()2(5.0

)1(

1

sT

abTsabba

z

−+−−+→−

(12)

Since this is the ideal case for the NRZ DAC pulse, b=1 and a=0. Since CT ∆Σ

modulators are often designed by transforming a given DT ∆Σ modulator, this illustrates

the technique while also setting up the equations for the following analysis of excess loop

delay on this loop filter. Note that while this method for conversion between continuous-

time and discrete-time loop filters is very helpful for analyzing the excess loop delay, this

16

procedure alone may not fully characterize higher-order ∆Σ modulators. The method

provides the loop filter but not the entire equivalent filter between the input and the

output of the ∆Σ modulator, except in the first-order case. The addition of another filter

on the input is sometimes necessary in order to fully design the ∆Σ modulator with the

appropriate STF and NTF. These finer points of the conversion are discussed in [12].

To add the excess loop delay factor it is assumed that the DAC pulse is NRZ.

Since the DAC pulse is of length T, Figure 9 indicates that the pulse will extend into the

next sampling period making 1>b . It was assumed however in (2) that 1≤b . To

correct this problem, the time response of DAC(t) can be written as the linear

combination of two pulses, one from ( dt ,1) and the other from (0, dt ) shifted by one time

unit. This is shown by

)1()()( ),0()1,()1,( −+=+ tDACtDACtDAC tdtdtdtd (13)

Table III of [5] provides the conversions necessary to transform (10) back to a z-domain

equivalent. The necessary equivalencies are

2

22

22 )1(

)(5.0)]2()2([5.01

−−+−−−→

z

abzaabb

sT (14)

and 1

1

−−→

z

ab

Ts (15)

For )()1,( tDAC td , b=1 and a= dt . But for )1(),0( −tDAC td , b= dt and a=0, while a 1−z

factor must be added due to the delay of this pulse. Therefore the resulting transforms

are

1

5.1

1

)1(5.15.1 1

−−

+−

−−→− −

z

tz

z

t

Tsdd (16)

17

and 2

21

2

22

22 )1(

5.0)5.01(

)1(

)1(5.0)5.05.0(1

−−+−

+−

+−+−+−→− −

z

tzttz

z

tztt

sTdddddd (17)

The resulting discrete-time loop filter is

2

2222

)1(

)5.05.1()41()5.05.22()(

−−++−+−+−

=zz

ttzttzttzH dddddd (18)

This derivation illustrates a relatively easy way to analyze a CT ∆Σ modulator that

suffers from excess loop delay. Depending on the amount of loop delay, the parmeter dt

can be varied to determine the tolerances of the filter.

This excess loop delay increases the noise floor for a given ∆Σ modulator [5]

since this noise adds to the quantization noise of the ∆Σ modulator and is shaped by the

noise transfer function. The excess loop delay also potentially increases the instability of

the ∆Σ modulator by adding another order to the loop filter [6]. This is evident in (18) as

the original second-order loop filter in (9) is now third order. This can be simulated quite

easily now that an equivalent discrete-time filter has been obtained. A method for

compensating this non-ideality will be presented in Section 4.2.

18

4.0 Solutions

A solution to the problems of excess loop delay and clock jitter will be presented.

Section 4.1 will introduce a topology that can help eliminate clock jitter. In 4.2, the

compensation solution will be presented which is supposed to alleviate the effects of

excess loop delay.

4.1 SC-R Feedback

The proposed idea to reduce the clock jitter is to introduce a modified form of

switched-capacitor (SC) feedback into the CT ∆Σ modulator [8]. Since the signal path is

still only switched at the quantizer, the inherent anti-aliasing filter is still present in the

CT ∆Σ modulator [8]. However, the required bandwidth and the slew rate of the filter

integrators would have to be much higher due to the fast switching of the SC feedback

[8]. This would minimize some of the advantages of the CT ∆Σ modulator.

The solution is illustrated in Figure 10 for a second-order ∆Σ modulator where

the feedback has been modified from the typical SC feedback structure. A discharge

capacitor rC is introduced in series with a resistor rR at the input of the integrators in the

feedback path in order to slow down the switching, resulting in a discharge capacitor

current τ/exp t

r

OC R

VI −= where rrCR=τ [8].

Figure 10 2nd order continuous-time ∆Σ modulator with SC-R feedback [8].

19

This structure was analyzed in [8] using the same method discussed in Section 3.1

in order to derive the appropriate loop filter. The difference is that since the DAC pulse

is no longer a square pulse from a to b, the numerators on the s-domain terms in (11) and

(12) have changed. The changes to the transformations are as follows (with a sampling

period T):

−−→

− ))2/exp(1(

11

1

1

ττ Tsz (19)

and 2

012)1(

1

s

rsr

z

+→

− (20)

where

−+−−

= )2/exp()(2)1)2/(exp(

)2/exp(21 τττ

τττ

TTT

TT

Tr (21)

and )1)2/(exp()1)2/(exp(

)2/exp(20 −

−= τ

τττ

TTT

Tr (22)

Following a similar procedure as outlined in Section 3.1, the block diagram of Figure 11

was derived in [8] as a second-order implementation of the SC-R feedback CT ∆Σ

modulator with ))2/exp(1(1 ττ T

Ta

−−= and

))2/exp()2/exp(2(2

)2/exp()(2232 τττ

τττTT

TTTa

−−−+−+= .

Figure 11 Block Diagram of 2nd order CT ∆Σ modulator with SC-R feedback [8].

20

This circuit was found to increase the in-band noise (IBN) due to the clock jitter

by between 0dB and 10dB (depending on the settling time τ , better for low τ ) while a

typical RZ DAC increased the IBN by 25dB [8]. This shows a great improvement,

however it comes at a cost. A higher slew rate in the integrators is required, although it is

still less than that of DT ∆Σ modulators. Also, a higher gain bandwidth product is

required as the settling time factor τ decreases. Both of these issues put a constraint on

the speed of the system, requiring higher speed amplifiers [8].

4.2 Compensation Solution

The principle in the compensation solution is to remove the extra coefficients

obtained by modeling the excess loop delay in equation (18). Repeating the loop filter

equations for convenience,

2

2222

)1(

)5.05.1()41()5.05.22()(

−−++−+−+−

=zz

ttzttzttzH dddddd

with the loop delay, and

2)1(

12)(

−+−=

z

zzH

without the loop delay. The difference in these equations exists in the numerator where

the corruption due to the dt term is obvious, and if 0=dt , the two equations become

equal. A full degree of freedom is added in the topology of Figure 12 in order to

overcome this problem [6].

The coefficients K,, 11 ba kk of Figure 12 can be tuned in order to obtain a match

between the desired filter and the corrupted filter. Extra loop delay is added in the

feedback path in order to obtain two tuneable parameters that may alter the response of

21

the corrupted filter in order to regain the proper response. These parameters are tuned

based on the amount of excess loop delay.

Figure 12 The Compensation Solution [6].

The simulations were performed with LC resonator based second-order and

fourth-order band-pass ∆Σ modulators in [6]. It was found that the SNR was improved

by properly adjusting the tuning parameters to their optimal values [6]. It is also claimed

that this procedure could be generalized to correct other non-idealities such as finite DAC

rise and fall times [6].

In [2] it was shown that the compensation method could work in a second-order

low-pass CT ∆Σ modulator in order to minimize the damaging effects of the DAC delay

as well as the finite DAC rise and fall times. The block diagram of the solution is shown

in Figure 13 where δ is the DAC delay ( dt ). Note that the ∆Σ modulator has been

modeled somewhat differently as the input x(t) enters at two points, before the first and

second continuous-time integrator blocks. This is simply a variation on the ∆Σ topology.

Figure 13 The compensation solution for a 2nd order low-pass CT modulator [2].

22

5.0 Future Considerations

The SC-R feedback solution to the clock jitter problem is very effective, yet it

requires higher speed constraints on the speed of the amplifiers. Appropriate layout

techniques as well as the use of crystal oscillators can also help minimize the clock jitter

in a ∆Σ modulator [13], but further investigation into this topic is necessary in order to

find another technique that can reduce the effects of clock jitter without degrading the

speed of the CT ∆Σ modulators.

The compensation solution is a very promising solution, however some

quantifiable results for this method would be appreciated to prove that it reduces the

excess loop delay to a minimum.

Despite providing possible solutions to both the clock jitter and excess loop delay

problems, CT ∆Σ modulators still exhibit several other non-idealities that affect (to a

lesser degree) their performance. Some of these include the linearity of the integrating

stages, the memory effect of the feedback DAC [13], signal dependent quantizer delay,

DAC rise/fall times and quantizer clock jitter, among others. These all leave the potential

to further investigate the non-idealities involved with CT ∆Σ modulators.

23

6.0 Conclusion

It was shown that the equivalence between discrete-time and continuous-time

filters is of great benefit in analyzing CT ∆Σ modulators. These techniques were used to

help analyze and find solutions for the two main non-idealities in CT ∆Σ modulators,

clock jitter and excess loop delay.

The SC-R feedback technique helps alleviate the effects of clock jitter noise at a

cost of increased speed in the amplifiers, while the compensation solution provides one

method of reducing excess loop delay at the cost of increased circuit complexity. The

minimization of these effects is important in the design of high-speed CT ∆Σ modulators

in order to take advantage of the higher speed potential of CT ∆Σ modulators over their

discrete-time counterparts. While the techniques illustrated provide a means of

improving the performance of CT ∆Σ modulators, other non-idealities still exist that

must be investigated.

24

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25

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