Combinational Networks 1viplab.cs.nctu.edu.tw/course/VLSI_SOC2013_Fall/VLSI_Lecture_08.pdfProve that the P/N ratio that gives lowest average delay in a logic gate is the square root

Introduction to VLSI and System-on-Chip Design

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Fall, 2013

Gates

Lecture 8


Lan-Da Van VLSI-08-2

Outlines

Introduction

Static CMOS Circuits

Static Complementary Logic Gates

Asymmetric Gate

Skewed Gate

P/N ratios

Ratioed Circuits

Pseudo-nMOS Gates

Differential Cascode Voltage Switch Logic (DCVSL)

Dynamic CMOS Circuits

Domino Logic

Transmission Gate

Conclusion

Lecture 8



Universal/Complete

A set of functions f1, f2, ..fn is universal/complete iff

every Boolean function can be generated by a

combination of the functions.

{AND, OR, Inverter} is universal/complete. However,

{AND, OR} is not universal/complete.

AOI = and/or/invert; OAI = or/and/invert.

NAND is a universal/complete gate; NOR is a

universal/complete gate. How to prove??

Transmission gates are not universal/complete gate.

If your set of logic gates is not universal/complete,

you can’t design arbitrary logic.

Lecture 8



What makes a circuit fast? I=CdV/dt =>

Low capacitance

High current

Small swing

Logical effort is proportional to C/I

pMOS are the enemy!! High capacitance for a given current

Can we take the pMOS capacitance off the input?

Various circuit families try to do this…

VICt pd )/(

Logical Effort Factor

Lecture 8



Outlines

Introduction



Asymmetric Gate

Skewed Gate

P/N ratios

Ratioed Circuits

Pseudo-nMOS Gates



Domino Logic

Transmission Gate

Conclusion

Lecture 8



Static Complementary Gates

Static: do not rely on the stored charge.

Complementary: have complementary pullup (p-type)

and pulldown (n-type) networks.

Simple, effective, reliable; hence ubiquitous.

pullup network

pulldown network

VDD

VSS

out inputs

Lecture 8



Pullup/Pulldown Network Design

Pullup and pulldown networks are duals.

To design one gate, first design one network, and

then compute dual to get other network.

Design Steps

Step 1: Formulate Boolean function in fully complement form

Step 2: Implement the fully complement form using nMOS

(i.e., pull-down network).

Step 3: Complement the pull-down network to obtain dual

network (i.e., pull-up network) using pMOS.

Lecture 8



NAND Gate

Lecture 8



NOR Gate

Lecture 8



Compound Gate

An and-or-invert-21 (AOI-21) gate:

out = [ab+c]

symbol circuit

and

or

invert

Network

Dual Network

Lecture 8



Complex CMOS Gate

VDD

A

B

C

D

D

A

B C

OUT = D + A• (B+C)

Lecture 8



ABCD

Y

ABC

Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA = 6/3

gB = 6/3

gC = 6/3

p = 12/3

gD = 6/3

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE

Y

B

Y

B C

A

D

E

A

B

C

D E

gA = 5/3

gB = 8/3

gC = 8/3

gD = 8/3

2

2 2

22

6

6

6 6

3

p = 16/3

gE = 8/3

Complex AOI

Y A B C Y A B C D Y A B C D E Y A

Logical Effort of Compound Gate

Lecture 8



Example: Delay Calculation (1/3)

Calculate the minimum delay of the function F=AB+CD

using the following circuits. Each input has a maximum

of 20 ut of transistor width. The output must drive a load

equivalent to 100 ut of transistor width. Estimate the

transistor sizes to achieve this delay.

F

AB

CD

F

ABCD

H = 100 / 20 = 5

B = 1

N = 2

Lecture 8



NAND Solution (2/3)

F

AB

CD

10ˆ

0.3ˆ

9/8051)9/16(

9/16)3/4()3/4(

422

PfND

Ff

GBHF

G

P

N

Lecture 8



Compound Solution (3/3)

4.11ˆ

2.3ˆ

10512

2)1()3/6(

513/12

PfND

Ff

GBHF

G

P

N

F

ABCD

Lecture 8



Example: Width Calculation (1/2)

Annotate your designs with transistor sizes

that achieve this delay.

44ˆ,

,

f

gCC

iioutiin

YY

31ˆ,

,

f

gCC

iioutiin

p2

n2

p1

n1

p1

n1

Lecture 8



Example: Width Calculation (2/2)

Annotate your designs with transistor sizes

that achieve this delay.

7

7 7

7

13

13Y

21

10

13

13

10

10

1010

10

10

1010

22

22

2222Y

Lecture 8



Our parasitic delay model was too simple

Calculate parasitic delay for Y falling

If input A is critical….

If input B is critical….

6C

2C2

2

22

B

A

x

Y

Symmetric Gate

Lecture 8



Asymmetric Gates

Asymmetric gates favor one input over another

Ex: suppose input A of a NAND gate is most critical

Use smaller transistor on A (less capacitance)

Boost size of noncritical input

So total resistance is same

gA = 10/9

greset = 2

gavg = (gA + greset)/2 = 14/9

Asymmetric gate approaches g = 1 on critical input

But total logical effort goes up

A

resetY

4

4/3

22

reset

A

Y

Lecture 8



Skew Definition

Skewed gates favor one edge over another

Lecture 8



Skewed Gates

Skewed gates favor one edge over another

Ex: suppose rising output of inverter is most critical

Downsize noncritical nMOS transistor

Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.

gu = 2.5 / 3 = 5/6

gd = 2.5 / 1.5 = 5/3

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skew

inverter

unskewed inverter

(equal rise resistance)

unskewed inverter

(equal fall resistance)

Lecture 8



Logical Effort for Skew Gate

Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that

gate to the input capacitance of an unskewed inverter

delivering the same output current for the same

transition.

Skewed gates reduce size of noncritical transistors

HI-skew gates favor rising output (small nMOS)

LO-skew gates favor falling output (small pMOS)

Logical effort is smaller for favored direction; but

larger for the other direction

Lecture 8



Logical Effort of Skewed Gates

1/2

2A Y

Inverter

1

1

22

B

AY

B

A

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

B

A

11

2

2

gu = 5/6

gd = 5/3

gavg = 5/4

gu = 4/3

gd = 2/3

gavg = 1

gu = 1

gd = 2

gavg = 3/2

gu = 2

gd = 1

gavg = 3/2

gu = 3/2

gd = 3

gavg = 9/4

gu = 2

gd = 1

gavg = 3/2

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1

gd = 1

gavg = 1

gu = 4/3

gd = 4/3

gavg = 4/3

gu = 5/3

gd = 5/3

gavg = 5/3

Y

Lecture 8



Best P/N Ratio

Prove that the P/N ratio that gives lowest average delay in

a logic gate is the square root of the ratio that gives equal

rise and fall delays.

Sol: For an inverter, we have selected P/N ratio (i.e, k) for

unit rise and fall resistance.

Using logical effort => tpdf = (P+1)(1/(I+k

Using logical effort => tpdr = (P+1)(1/(P+P/k))

tpd = (P+1)(1+k/P)/(2x(1+k = (P + 1 + k + k/P)/)/

(2x(1+k

Differentiate tpd w.r.t. P

Least delay is P = k1/2

1

PA

1

kA

Ref. CKT

Lecture 8



P/N Ratios

In general, best P/N ratio is sqrt of that giving

equal delay.

Only improves average delay slightly for inverters

But significantly decreases area and power

Inverter NAND2 NOR2

1

1.414A Y

2

2

22

B

AY

B

A

11

2

2

fastest

P/N ratio gu = 1.15

gd = 0.81

gavg = 0.98

gu = 4/3

gd = 4/3

gavg = 4/3

gu = 2

gd = 1

gavg = 3/2

Y

Lecture 8



Pseudo-nMOS

In the old days, nMOS processes had no pMOS

Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON

Ratio issue

Make pMOS about ¼ effective strength of pulldown network

Vout

Vin

16/2

P/2

Ids

load

0 0.3 0.6 0.9 1.2 1.5 1.8

0

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout

Strong Pull-down

Weak Pull-up

Lecture 8



Pseudo-nMOS Characteristics

Logic 1 output is always at VDD.

Logic 0 output is above VSS.

VOL = 0.25 (VDD - VSS) is one plausible choice.

Consumes static power.

Has much smaller pullup network than static gate.

Asymmetrical response.

Pullup time is longer than pulldown time.

Lecture 8



Pseudo-nMOS NAND gate

VDD

GND

Lecture 8



Logical Effort of Pseudo-nMOS Gates

Design for unit current on output

to compare with unit inverter.

pMOS fights nMOS

Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3

gd = 4/9

gavg = 8/9

pu = 6/3

pd = 6/9

pavg = 12/9

Y

gu = 8/3

gd = 8/9

gavg = 16/9

pu = 10/3

pd = 10/9

pavg = 20/9

gu = 4/3

gd = 4/9

gavg = 8/9

pu = 10/3

pd = 10/9

pavg = 20/9

f

inputs

Y

Lecture 8



Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9

F = GBH = 8H/9

P = 1 + (4+8k)/9 = (8k+13)/9

N = 2

D = NF1/N + P =

In1

Ink

Y

Pseudo-nMOS

1

1H

4 2 8 13

3 9

H k

Lecture 8



Pseudo-nMOS Power

Pseudo-nMOS draws power whenever Y = 0

Called static power P = I•VDD

A few mA / gate * 1M gates would be a problem

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use

A B

Y

C

en

Lecture 8



DCVS Logic Operation

DCVSL = differential cascode voltage switch logic.

Static logic—consumes no static power.

Uses latch to compute output quickly.

Exactly one of true/complement pulldown networks

will complete a path to the power supply. (i.e.,

requires true/complement inputs, produces

true/complement outputs.)

Pulldown network will lower output voltage, turning on

other p-type, which also turns off p-type for node

which is going down.

Lecture 8



DCVS Structure

Lecture 8



Example: DCVSL

Lecture 8



Outlines

Introduction



Asymmetric Gate

Skewed Gate

P/N ratios

Ratioed Circuits

Pseudo-nMOS Gates



Domino Logic

Transmission Gate

Conclusion

Lecture 8



Dynamic Logic Operation

Uses precharge clock to compute output in two phases:

Controlled by clock .

Precharge: p-type pullup precharges the storage node; inverter

ensures that output goes low.

Evaluate: storage node may be pulled down, so output goes up.

Output inverter is needed for two reasons:

make sure that outputs start low, go high so that domino output

can be connected to another domino gate (monotonic input rising)

protects storage node from outside influence.

AY

foot

precharge transistor Y

inputs

Y

inputs

footed unfooted

f f

Lecture 8



Comparison of Three Gates

Dynamic gates uses a clocked pMOS pullup

Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

Static Pseudo-nMOS Dynamic

Precharge Evaluate

Y

Precharge

gSTATIC=1 gDYNAMIC=1/3 gPSEUDO=8/9

Lecture 8



Logical Effort of Dynamic Gates

Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3

pd = 2/3

gd = 2/3

pd = 3/3

gd = 1/3

pd = 3/3

Y

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3

pd = 3/3

gd = 3/3

pd = 4/3

gd = 2/3

pd = 5/3

Y

footed

unfooted

32 2

Lecture 8



Dynamic Effect with Monotonicity

Dynamic gates require monotonically rising inputs (A)

during evaluation

0 -> 0

0 -> 1

1 -> 1

But not 1 -> 0

Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicity

during evaluation

A

Gate outputs fall in sequence:

gate 1 gate 2 gate 3

Lecture 8



Monotonicity Woes

But dynamic gates produce monotonically falling

outputs during evaluation

Illegal for one dynamic gate to drive another!

AX

Y

Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation

Lecture 8



Domino Gates (1/2)

Lecture 8



Domino Gates (2/2)

Follow dynamic stage with inverting static gate

Dynamic / static pair is called domino gate

Produces monotonic outputs

Precharge Evaluate

W

Precharge

X

Y

Z

A

BC

C

AB

W XY

Z =X

ZH

H

A

W

B C

X Y Z

domino AND

dynamic

NAND

static

inverter

Lecture 8



Dual-Rail Domino

Domino only performs noninverting functions:

AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputs

Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged

0 1 ‘0’

1 0 ‘1’

1 1 invalid

Y_h

f

inputs

Y_l

f

Lecture 8



Example: AND/NAND

Given A_h, A_l, B_h, B_l

Compute Y_h = A * B, Y_l = ~(A * B)

Pulldown networks are conduction complements

Y_h

Y_l

A_h

B_hB_lA_l

= A*B= A*B

Lecture 8



Example: XOR/XNOR

Sometimes possible to share transistors

Y_h

Y_l

A_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B

Lecture 8



Leakage

Dynamic node floats high during evaluation

Transistors are leaky (IOFF 0)

Dynamic value will leak away over time

Formerly miliseconds, now nanoseconds!

Use keeper to hold dynamic node

Must be weak enough not to fight evaluation

A

H

2

2

1 kX

Y

weak keeper

Make Sable state but power still lose…

Lecture 8



Charge Sharing

Dynamic gates suffer from charge sharing

B = 0

A

Y

x

Cx

CY

A

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V V

C C

Lecture 8



Domino Summary

Domino logic is attractive for high-speed circuits

1.5 – 2x faster than static CMOS

But many challenges:

Monotonicity

Leakage

Charge sharing

Noise

Widely used in high-performance microprocessors

Lecture 8



Comparison of Circuit Families

Lecture 8



Outlines

Introduction: Combinational Logic Functions



Asymmetric Gate

Skewed Gate

P/N ratios

Ratioed Circuits

Pseudo-nMOS Gates

Cascode Voltage Switch Logic


Domino Logic

Transmission Gate

Conclusion

Lecture 8



Switch Logic

Can implement Boolean formulas as networks of

switches.

Can build switches from MOS transistors—

transmission gates.

Transmission gates do not amplify but have smaller

layouts.

Lecture 8



Boolean Functions and Switches

Pseudo-AND Pseudo-OR

b’

a

b

a’

ab’ + a’b

Switch network inputs may be connected to power supply

or logic signals.

If switch network output is not connected to power supply

through switch path, output will float.

Lecture 8



Switch Multiplexer

Lecture 8



Pass Transistor Circuits

Use pass transistors like switches to do logic

Inputs drive diffusion terminals as well as gates

CMOS + Transmission Gates:

2-input multiplexer

Gates should be restoring

A

B

S

S

S

Y

A

B

S

S

S

Y

Lecture 8



Behavior of n-type Switch

n-type switch has source-drain voltage drop when

conducting:

conducts logic 0 perfectly;

introduces threshold drop into logic 1.

Voltage drop causes next stage to be turned on

weakly.

VDD

VDD

VDD - Vt

VDD VDD - Vt

VDD

Lecture 8



Behavior of Complementary Switch

Complementary switch products full-supply voltages

for both logic 0 and logic 1:

n-type transistor conducts logic 0;

p-type transistor conducts logic 1.

Has two source/drain areas compared to one for

inverter.

Lecture 8



Charge Sharing

Interior nodes in a switch network may not be driven.

Charge can accumulate on small parasitic

capacitances.

Shared charge can produce erroneous output values.

At undriven nodes, charge is divided according to

capacitance ratio.

Lecture 8



Example: Charge Sharing

Long chains of switches have intermediate nodes

which may be disconnected from power supplies.

Cab Cia Cbc

Lecture 8



Charge Over Time

Make sure that for every input combination, there is a

path from the power supply to the output.

Time i Cia a Cab b Cbc c C

0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 1 0 1

2 0 0 0 1/2 1 1/2 0 1

3 0 0 0 1/2 0 3/4 1 3/4

4 0 0 1 0 0 3/4 0 3/4

5 0 0 0 3/8 1 3/8 0 3/4

Lecture 8



Conclusions

You should learn in depth about the following

topics:



Transmission Gates

Documents

Combinational Networks 1viplab.cs.nctu.edu.tw/course/VLSI_SOC2013_Fall/VLSI_Lecture_08.pdfProve that the P/N ratio that gives lowest average delay in a logic gate is the square root